SN5400, SN54LS00, SN54S00
SN7400, SN74LS00, SN74S00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SDLS025B - DECEMBER 1983 - REVISED OCTOBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Package Options Include Plastic
Small-Outline (D, NS, PS), Shrink
Small-Outline (DB), and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J) DIPs
D
Also Available as Dual 2-Input
Positive-NAND Gate in Small-Outline (PS)
Package
SN5400 . . . J PACKAGE
SN54LS00, SN54S00 . . . J OR W PACKAGE
SN7400, SN74S00 . . . D, N, OR NS PACKAGE
SN74LS00 . . . D, DB, N, OR NS PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
SN5400 . . . W PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
V
CC
2Y
2A
2B
4Y
4B
4A
GND
3B
3A
3Y
SN74LS00, SN74S00 . . . PS PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
V
CC
2B
2A
2Y
1A
1B
1Y
GND
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3B
1Y
NC
2A
NC
2B
1B
1A
NC
3Y
3A
V
4B
2Y
GND
NC
SN54LS00, SN54S00 . . . FK PACKAGE
(TOP VIEW)
CC
NC - No internal connection
description/ordering information
These devices contain four independent 2-input NAND gates. The devices perform the Boolean function
Y = A
B or Y = A + B in positive logic.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN5400, SN54LS00, SN54S00
SN7400, SN74LS00, SN74S00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SDLS025B - DECEMBER 1983 - REVISED OCTOBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SN7400N
SN7400N
PDIP - N
Tube
SN74LS00N
SN74LS00N
PDIP - N
Tube
SN74S00N
SN74S00N
Tube
SN7400D
7400
Tape and reel
SN7400DR
7400
SOIC - D
Tube
SN74LS00D
LS00
SOIC - D
Tape and reel
SN74LS00DR
LS00
0
C to 70
C
Tube
SN74S00D
S00
0 C to 70 C
Tape and reel
SN74S00DR
S00
SN7400NSR
SN7400
SOP - NS
Tape and reel
SN74LS00NSR
74LS00
SOP - NS
Tape and reel
SN74S00NSR
74S00
SOP - PS
Tape and reel
SN74LS00PSR
LS00
SOP - PS
Tape and reel
SN74S00PSR
S00
SSOP - DB
Tape and reel
SN74LS00DBR
LS00
SNJ5400J
SNJ5400J
CDIP - J
Tube
SNJ54LS00J
SNJ54LS00J
CDIP - J
Tube
SNJ54S00J
SNJ54S00J
-55
C to 125
C
SNJ5400W
SNJ5400W
-55
C to 125
C
CFP - W
Tube
SNJ54LS00W
SNJ54LS00W
CFP - W
Tube
SNJ54S00W
SNJ54S00W
LCCC - FK
Tube
SNJ54LS00FK
SNJ54LS00FK
LCCC - FK
Tube
SNJ54S00FK
SNJ54S00FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
A
B
OUTPUT
Y
H
H
L
L
X
H
X
L
H
logic diagram, each gate (positive logic)
A
B
Y
SN5400, SN54LS00, SN54S00
SN7400, SN74LS00, SN74S00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SDLS025B - DECEMBER 1983 - REVISED OCTOBER 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
schematic
'00
GND
Y
130
VCC
4 k
A
1.6 k
1 k
B
VCC
Resistor values shown are nominal.
Y
GND
3 k
4 k
120
8 k
20 k
1.5 k
12 k
A
B
2.8 k
900
B
A
500
250
3.5 k
'LS00
'S00
VCC
Y
GND
50
SN5400, SN54LS00, SN54S00
SN7400, SN74LS00, SN74S00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SDLS025B - DECEMBER 1983 - REVISED OCTOBER 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
CC
(see Note 1)
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage: '00, 'S00
5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
'LS00
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
86
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package
96
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
80
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
76
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS package
95
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. Voltage values are with respect to network ground terminal.
2. The package termal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN5400
SN7400
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.75
5
5.25
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
IOH
High-level output current
-0.4
-0.4
mA
IOL
Low-level output current
16
16
mA
TA
Operating free-air temperature
-55
125
0
70
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN5400
SN7400
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = MIN,
II = -12 mA
-1.5
-1.5
V
VOH
VCC = MIN,
VIL = 0.8 V,
IOH = -0.4 mA
2.4
3.4
2.4
3.4
V
VOL
VCC = MIN,
VIH = 2 V,
IOL = 16 mA
0.2
0.4
0.2
0.4
V
II
VCC = MAX,
VI = 5.5 V
1
1
mA
IIH
VCC = MAX,
VI = 2.4 V
40
40
A
IIL
VCC = MAX,
VI = 0.4 V
-1.6
-1.6
mA
IOS
VCC = MAX
-20
-55
-18
-55
mA
ICCH
VCC = MAX,
VI = 0 V
4
8
4
8
mA
ICCL
VCC = MAX,
VI = 4.5 V
12
22
12
22
mA
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V, TA = 25
C.
Not more than one output should be shorted at a time.
SN5400, SN54LS00, SN54S00
SN7400, SN74LS00, SN74S00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SDLS025B - DECEMBER 1983 - REVISED OCTOBER 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics, V
CC
= 5 V, T
A
= 25
C (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
SN5400
SN7400
UNIT
PARAMETER
(INPUT)
(OUTPUT)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(INPUT)
(OUTPUT)
MIN
TYP
MAX
tPLH
A or B
Y
RL = 400
,
CL = 15 pF
11
22
ns
tPHL
A or B
Y
RL = 400
,
CL = 15 pF
7
15
ns
recommended operating conditions (see Note 4)
SN54LS00
SN74LS00
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.75
5
5.25
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.7
0.8
V
IOH
High-level output current
-0.4
-0.4
mA
IOL
Low-level output current
4
8
mA
TA
Operating free-air temperature
-55
125
0
70
C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LS00
SN74LS00
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = MIN,
II = -18 mA
-1.5
-1.5
V
VOH
VCC = MIN,
VIL = MAX,
IOH = -0.4 mA
2.5
3.4
2.7
3.4
V
VOL
VCC = MIN,
VIH = 2 V
IOL = 4 mA
0.25
0.4
0.25
0.4
V
VOL
VCC = MIN,
VIH = 2 V
IOL = 8mA
0.35
0.5
V
II
VCC = MAX,
VI = 7 V
0.1
0.1
mA
IIH
VCC = MAX,
VI = 2.7V
20
20
A
IIL
VCC = MAX,
VI = 0.4 V
-0.4
-0.4
mA
IOS
VCC = MAX
-20
-100
-20
-100
mA
ICCH
VCC = MAX,
VI = 0 V
0.8
1.6
0.8
1.6
mA
ICCL
VCC = MAX,
VI = 4.5 V
2.4
4.4
2.4
4.4
mA
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V, TA = 25
C.
Not more than one output should be shorted at a time.
switching characteristics, V
CC
= 5 V, T
A
= 25
C (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
SN54LS00
SN74LS00
UNIT
PARAMETER
(INPUT)
(OUTPUT)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(INPUT)
(OUTPUT)
MIN
TYP
MAX
tPLH
A or B
Y
RL = 2 k
,
CL = 15 pF
9
15
ns
tPHL
A or B
Y
RL = 2 k
,
CL = 15 pF
10
15
ns
SN5400, SN54LS00, SN54S00
SN7400, SN74LS00, SN74S00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SDLS025B - DECEMBER 1983 - REVISED OCTOBER 2003
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 5)
SN54S00
SN74S00
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.75
5
5.25
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
IOH
High-level output current
-1
-1
mA
IOL
Low-level output current
20
20
mA
TA
Operating free-air temperature
-55
125
0
70
C
NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54S00
SN74S00
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = MIN,
II = -18 mA
-1.2
-1.2
V
VOH
VCC = MIN,
VIL = 0.8 V,
IOH = -1 mA
2.5
3.4
2.7
3.4
V
VOL
VCC = MIN,
VIH = 2 V,
IOL = 20 mA
0.5
0.5
V
II
VCC = MAX,
VI = 5.5 V
1
1
mA
IIH
VCC = MAX,
VI = 2.7 V
50
50
A
IIL
VCC = MAX,
VI = 0.5V
-2
-2
mA
IOS
VCC = MAX
-40
-100
-40
-100
mA
ICCH
VCC = MAX,
VI = 0 V
10
16
10
16
mA
ICCL
VCC = MAX,
VI = 4.5 V
20
36
20
36
mA
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V, TA = 25
C.
Not more than one output should be shorted at a time.
switching characteristics, V
CC
= 5 V, T
A
= 25
C (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
SN54S00
SN74S00
UNIT
PARAMETER
(INPUT)
(OUTPUT)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(INPUT)
(OUTPUT)
MIN
TYP
MAX
tPLH
A or B
Y
RL = 280
,
CL = 15 pF
3
4.5
ns
tPHL
A or B
Y
RL = 280
,
CL = 15 pF
3
5
ns
tPLH
A or B
Y
RL = 280
,
CL = 50 pF
4.5
ns
tPHL
A or B
Y
RL = 280
,
CL = 50 pF
5
ns
SN5400, SN54LS00, SN54S00
SN7400, SN74LS00, SN74S00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SDLS025B - DECEMBER 1983 - REVISED OCTOBER 2003
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54/74 DEVICES
tPHL
tPLH
tPLH
tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
1 k
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO
50
; tr and tf
7 ns for Series
54/74 devices and tr and tf
2.5 ns for Series 54S/74S devices.
F. The outputs are measured one at a time with one input transition per measurement.
S1
S2
tPHZ
tPLZ
tPZL
tPZH
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
Waveform 1
(see Notes C
and D)
Waveform 2
(see Notes C
and D)
1.5 V
VOH - 0.5 V
VOL + 0.5 V
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
tw
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
VOH
VOL
Figure 1. Load Circuits and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
JM38510/00104BCA
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
JM38510/00104BDA
ACTIVE
CFP
W
14
1
None
Call TI
Level-NC-NC-NC
JM38510/07001BCA
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
JM38510/07001BDA
ACTIVE
CFP
W
14
1
None
Call TI
Level-NC-NC-NC
JM38510/30001B2A
ACTIVE
LCCC
FK
20
1
None
Call TI
Level-NC-NC-NC
JM38510/30001BCA
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
JM38510/30001BDA
ACTIVE
CFP
W
14
1
None
Call TI
Level-NC-NC-NC
JM38510/30001SCA
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
JM38510/30001SDA
ACTIVE
CFP
W
14
1
None
Call TI
Level-NC-NC-NC
SN5400J
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
SN54LS00J
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
SN54S00J
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
SN7400D
ACTIVE
SOIC
D
14
50
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN7400DR
ACTIVE
SOIC
D
14
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN7400N
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN7400N3
OBSOLETE
PDIP
N
14
None
Call TI
Call TI
SN7400NSR
ACTIVE
SO
NS
14
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74LS00D
ACTIVE
SOIC
D
14
50
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74LS00DBLE
OBSOLETE
SSOP
DB
14
None
Call TI
Call TI
SN74LS00DBR
ACTIVE
SSOP
DB
14
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74LS00DR
ACTIVE
SOIC
D
14
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74LS00J
OBSOLETE
CDIP
J
14
None
Call TI
Call TI
SN74LS00N
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74LS00NSR
ACTIVE
SO
NS
14
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74LS00PSR
ACTIVE
SO
PS
8
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74S00D
ACTIVE
SOIC
D
14
50
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74S00DR
ACTIVE
SOIC
D
14
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74S00N
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74S00N3
OBSOLETE
PDIP
N
14
None
Call TI
Call TI
SN74S00NSR
ACTIVE
SO
NS
14
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74S00PSR
ACTIVE
SO
PS
8
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SNJ5400J
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
Addendum-Page 1
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
SNJ5400W
ACTIVE
CFP
W
14
1
None
Call TI
Level-NC-NC-NC
SNJ5400WA
OBSOLETE
CFP
WA
14
None
Call TI
Level-NC-NC-NC
SNJ54LS00FK
ACTIVE
LCCC
FK
20
1
None
Call TI
Level-NC-NC-NC
SNJ54LS00J
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
SNJ54LS00W
ACTIVE
CFP
W
14
1
None
Call TI
Level-NC-NC-NC
SNJ54S00FK
ACTIVE
LCCC
FK
20
1
None
Call TI
Level-NC-NC-NC
SNJ54S00J
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
SNJ54S00W
ACTIVE
CFP
W
14
1
None
Call TI
Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check
http://www.ti.com/productcontent
for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
Addendum-Page 2
MECHANICAL DATA
MLCC006B OCTOBER 1996
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
4040140 / D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MIN
MAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)
(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
13
14
15
16
18
17
11
10
8
9
7
5
4
3
2
0.020 (0,51)
0.010 (0,25)
6
1
28
26
27
19
21
B SQ
A SQ
22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,90
7,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
20
16
6,50
6,50
14
0,05 MIN
5,90
5,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65
M
0,15
0
8
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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Use of such information may require a license from a third party under the patents or other intellectual property
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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright
2005, Texas Instruments Incorporated
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