SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A OCTOBER 1976 REVISED JUNE 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
3-State Outputs Interface Directly With
System Bus
D
Gated Output-Control LInes for Enabling or
Disabling the Outputs
D
Fully Independent Clock Virtually
Eliminates Restrictions for Operating in
One of Two Modes:
Parallel Load
Do Nothing (Hold)
D
For Application as Bus Buffer Registers
D
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Flat
(W) Packages, Ceramic Chip Carriers (FK),
and Standard Plastic (N) and Ceramic (J)
DIPs
TYPE
TYPICAL
PROPAGATION
DELAY TIME
MAXIMUM
CLOCK
FREQUENCY
'173
23 ns
35 MHz
'LS173A
18 ns
50 MHz
description
The '173 and 'LS173A 4-bit registers include
D-type flip-flops featuring totem-pole 3-state
outputs capable of driving highly capacitive
or relatively low-impedance loads. The
high-impedance third state and increased
high-logic-level drive provide these flip-flops with
the capability of being connected directly to and
driving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of
the SN74173 or SN74LS173A outputs can be connected to a common bus and still drive two Series 54/74 or
54LS/74LS TTL normalized loads, respectively. Similarly, up to 49 of the SN54173 or SN54LS173A outputs can
be connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load,
respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic
levels, the output control circuitry is designed so that the average output disable times are shorter than the
average output enable times.
Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both
data-enable (G1, G2) inputs are low, data at the D inputs are loaded into their respective flip-flops on the next
positive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided. When both
are low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus
lines. The outputs are disabled independently from the level of the clock by a high logic level at either
output-control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed
operation is given in the function table.
The SN54173 and SN54LS173A are characterized for operation over the full military temperature range of
55
C to 125
C. The SN74173 and SN74LS173A are characterized for operation from 0
C to 70
C.
Copyright
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
M
N
1Q
2Q
3Q
4Q
CLK
GND
V
CC
CLR
1D
2D
3D
4D
G2
G1
SN54173, SN54LS173A . . . J OR W PACKAGE
SN74173 . . . N PACKAGE
SN74LS173A . . . D or N PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
1D
2D
NC
3D
4D
1Q
2Q
NC
3Q
4Q
SN54LS173A . . . FK PACKAGE
(TOP VIEW)
N
M
NC
CLR
GND
NC
CC
V
NC No internal connection
G2
G1
CLK
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A OCTOBER 1976 REVISED JUNE 1999
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OUTPUT
CLR
CLK
DATA ENABLE
DATA
OUTPUT
Q
CLR
CLK
G1
G2
D
Q
H
X
X
X
X
L
L
L
X
X
X
Q0
L
H
X
X
Q0
L
X
H
X
Q0
L
L
L
L
L
L
L
L
H
H
When either M or N (or both) is (are) high, the output is
disabled to the high-impedance state; however, sequential
operation of the flip-flops is not affected.
logic symbol
G2
G1
G2
G1
1Q
3
R
15
CLR
13
2D
2Q
4
12
3D
3Q
5
11
4D
4Q
6
1
M
10
7
CLK
&
This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
&
EN
C1
2
N
9
1D
14
1D
1Q
3
R
15
CLR
13
2D
2Q
4
12
3D
3Q
5
11
4D
4Q
6
1
M
10
7
CLK
&
&
EN
C1
2
N
9
1D
14
1D
'173
'LS173A
SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A OCTOBER 1976 REVISED JUNE 1999
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
M
N
1D
CLR
CLK
2D
3D
4D
Output
Control
Data
Enable
G1
G2
1
2
14
9
10
13
7
12
11
15
3
4
5
6
1Q
2Q
3Q
4Q
Pin numbers shown are for D, J, N, and W packages.
SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A OCTOBER 1976 REVISED JUNE 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
schematics of inputs and outputs
Equivalent of Each Input
Equivalent of Each Input
Typical of All Outputs
VCC
Input
4 k
NOM
VCC
Input
20 k
NOM
VCC
Output
90
NOM
VCC
Output
100
NOM
'173
'LS173A
Typical of All Outputs
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
CC
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage: '173
0.5 V to 5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
'LS173A
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Off-state output voltage
0.5 V to 5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
113
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
78
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. Voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A OCTOBER 1976 REVISED JUNE 1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54173
SN74173
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.75
5
5.25
V
IOH
High-level output current
2
5.2
mA
IOL
Low-level output current
16
16
mA
TA
Operating free-air temperature
55
125
0
70
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54173
SN74173
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VIK
Input clamp voltage
VCC = MIN,
II = 12 mA
1.5
1.5
V
VOH
High-level output voltage
VCC = MIN,
VIL = 0.8 V,
VIH = 2 V,
IOH = MAX
2.4
2.4
V
VOL
Low-level output voltage
VCC = MIN,
VIL = 0.8 V,
VIH = 2 V,
IOL = 16 mA
0.4
0.4
V
IO( ff)
Off-state (high-impedance state)
VCC = MAX,
VO = 2.4 V
150
40
A
IO(off)
( g
)
output current
CC
,
VIH = 2 V
VO = 0.4 V
150
40
A
II
Input current
at maximum input voltage
VCC = MAX,
VI = 5.5 V
1
1
mA
IIH
High-level input current
VCC = MAX,
VI = 2.4 V
40
40
A
IIL
Low-level input current
VCC = MAX,
VI = 0.4 V
1.6
1.6
mA
IOS
Short-circuit output current
VCC = MAX
30
70
30
70
mA
ICC
Supply current
VCC = MAX,
See Note 4
50
72
50
72
mA
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V, TA = 25
C.
Not more than one output should be shorted at a time.
NOTE 4: ICC is measured with all outputs open; CLR grounded, following momentary connection to 4.5 V, N, G1, G2, and all data inputs grounded;
and CLK and M at 4.5 V.
timing requirements over recommended operating conditions (unless otherwise noted)
SN54173
SN74173
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Input clock frequency
25
25
MHz
tw
Pulse duration
CLK or CLR
20
20
ns
Data enable (G1, G2)
17
17
tsu
Setup time
Data
10
10
ns
CLR (inactive state)
10
10
th
Hold time
Data enable (G1, G2)
2
2
ns
th
Hold time
Data
10
10
ns
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