SN74AHCT74-EP
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCLS495 JUNE 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Controlled Baseline
One Assembly/Test Site, One Fabrication
Site
D
Extended Temperature Performance of
55
C to 125
C
D
Enhanced Diminishing Manufacturing
Sources (DMS) Support
D
Enhanced Product-Change Notification
D
Qualification Pedigree
D
Inputs Are TTL-Voltage Compatible
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
description/ordering information
The SN74AHCT74 is a dual positive-edge-triggered D-type flip-flop.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
55
C to 125
C
SOIC D
Tape and reel
SN74AHCT74MDREP
AHCT74MEP
55
C to 125
C
TSSOP PW
Tape and reel
SN74AHCT74MPWREP
AHT74EP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
D OR PW PACKAGE
(TOP VIEW)
SN74AHCT74-EP
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCLS495 JUNE 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
X
Q0
Q0
This configuration is unstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
logic symbol
S
4
3
1CLK
1D
2
1D
R
1
1Q
5
6
C1
10
11
2CLK
12
2D
13
2Q
9
8
1PRE
2PRE
1CLR
2CLR
1Q
2Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram, each flip-flop (positive logic)
TG
C
C
TG
C
TG
C
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
C
SN74AHCT74-EP
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCLS495 JUNE 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
86
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
113
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
8
mA
IOL
Low-level output current
8
mA
t/
v
Input transition rise or fall rate
20
ns/V
TA
Operating free-air temperature
55
125
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
VOH
IOH = 50
m
A
4 5 V
4.4
4.5
4.4
V
VOH
IOH = 8 mA
4.5 V
3.94
3.8
V
VOL
IOL = 50
m
A
4 5 V
0.1
0.1
V
VOL
IOL = 8 mA
4.5 V
0.36
0.44
V
II
VI = 5.5 V or GND
0 V to 5.5 V
0.1
1
m
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
2
20
m
A
ICC
One input at 3.4 V,
Other inputs at VCC or GND
5.5 V
1.35
1.5
mA
Ci
VI = VCC or GND
5 V
2
10
pF
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
SN74AHCT74-EP
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCLS495 JUNE 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
TA = 25
C
MIN
MAX
UNIT
PARAMETER
MIN
MAX
MIN
MAX
UNIT
t
Pulse duration
PRE or CLR low
5
5
ns
tw
Pulse duration
CLK
5
5
ns
t
Setup time before CLK
Data
5
5
ns
tsu
Setup time before CLK
PRE or CLR inactive
3.5
3.5
ns
th
Hold time, data after CLK
0
0
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CAPACITANCE
MIN
TYP
MAX
MIN
MAX
UNIT
f
CL = 15 pF
100
160
80
MHz
fmax
CL = 50 pF
80
140
65
MHz
tPLH
PRE
CLR
Q
Q
CL = 15 pF
7.6
10.4
1
12
ns
tPHL
PRE or CLR
Q or Q
CL = 15 pF
7.6
10.4
1
12
ns
tPLH
CLK
Q
Q
CL = 15 pF
5.8
7.8
1
9
ns
tPHL
CLK
Q or Q
CL = 15 pF
5.8
7.8
1
9
ns
tPLH
PRE
CLR
Q
Q
CL = 50 pF
8.1
11.4
1
13
ns
tPHL
PRE or CLR
Q or Q
CL = 50 pF
8.1
11.4
1
13
ns
tPLH
CLK
Q or Q
CL = 50 pF
6.3
8.8
1
10
ns
tPHL
CLK
Q or Q
CL = 50 pF
6.3
8.8
1
10
ns
noise characteristics, V
CC
= 5 V, C
L
= 50 pF, T
A
= 25
C (see Note 4)
PARAMETER
MIN
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
4
V
VIH(D)
High-level dynamic input voltage
2
V
VIL(D)
Low-level dynamic input voltage
0.8
V
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
No load,
f = 1 MHz
32
pF
SN74AHCT74-EP
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCLS495 JUNE 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
3 V
3 V
0 V
0 V
th
tsu
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
3 V
0 V
50% VCC
Input
(see Note B)
Out-of-Phase
Output
In-Phase
Output
Timing Input
(see Note B)
VOLTAGE WAVEFORMS
DELAY TIMES
3 V
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
50% VCC
50% VCC
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
LOAD CIRCUIT
Test
Point
CL
(see Note A)
From Output
Under Test
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
, tr
+
3 ns, tf
+
3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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