SN74CB3T16211
24 BIT FET BUS SWITCH
2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
SCDS147B - OCTOBER 2003 - REVISED JANUARY 2005
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
Output Voltage Translation Tracks V
CC
D
Supports Mixed-Mode Signal Operation On
All Data I/O Ports
- 5-V Input Down to 3.3-V Output Level
Shift, With 3.3-V V
CC
- 5-V/3.3-V Input Down to 2.5-V Output
Level Shift, With 2.5-V V
CC
D
5-V-Tolerant I/Os, With Device Powered Up
or Powered Down
D
Bidirectional Data Flow, With Near-Zero
Propagation Delay
D
Low ON-State Resistance (r
on
)
Characteristics (r
on
= 5
Typical)
D
Low Input/Output Capacitance Minimizes
Loading (C
io(OFF)
= 5 pF Typical)
D
Data and Control Inputs Provide
Undershoot Clamp Diodes
D
Low Power Consumption
(I
CC
= 70
A Max)
D
V
CC
Operating Range From 2.3 V to 3.6 V
D
Data I/Os Support 0- to 5-V Signaling
Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V,
5 V)
D
Control Inputs Can be Driven by TTL or
5-V/3.3-V CMOS Outputs
D
I
off
Supports Partial-Power-Down Mode
Operation
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II)
- 1000-V Charged-Device Model (C101)
D
Supports Digital Applications: Level
Translation, PCI Interface, Bus Isolation
D
Ideal for Low-Power Portable Equipment
description/ordering information
The SN74CB3T16211 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r
on
),
allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O
ports by providing voltage translation that tracks V
CC
. The SN74CB3T16211 supports systems using 5-V TTL,
3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1).
Widebus is a trademark of Texas Instruments.
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
1A1
1A2
1A3
1A4
1A5
1A6
GND
1A7
1A8
1A9
1A10
1A11
1A12
2A1
2A2
V
CC
2A3
GND
2A4
2A5
2A6
2A7
2A8
2A9
2A10
2A11
2A12
1OE
2OE
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
1B9
1B10
1B11
1B12
2B1
2B2
2B3
GND
2B4
2B5
2B6
2B7
2B8
2B9
2B10
2B11
2B12
NC - No internal connection
Copyright
2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74CB3T16211
24 BIT FET BUS SWITCH
2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
SCDS147B - OCTOBER 2003 - REVISED JANUARY 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
VCC
VCC
5.5 V
0 V
NOTE A: If the input high-voltage (VIH) level is greater than or equal to VCC - 1 V and less than or equal to 5.5 V, the output high-voltage (VOH)
level is equal to approximately the VCC voltage level.
Input Voltages
Output Voltages
0 V
VCC - 1 V
VCC - 1 V
VCC
IN
OUT
CB3T
Figure 1. Typical DC Voltage-Translation Characteristics
The I/O port of this device has a pullup current source that maintains the output voltage at V
CC
when the device
is ON and the input is greater than or equal to V
CC
- 1. Because of the pullup current source, the output voltage
level may be less than V
CC
when the operating frequency is low and the I/O port is connected to a pulldown
resistor. In order to maintain the output voltage at V
CC
, a pullup resistor must be connected to V
CC
, instead of
a pulldown resistor to ground.
The SN74CB3T16211 is organized as two 12-bit bus switches with separate output-enable (1OE, 2OE) inputs.
It can be used as two 12-bit bus switches or as one 24-bit bus switch. When OE is low, the associated 12-bit
bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When
OE is high, the associated 12-bit bus switch is OFF, and a high-impedance state exists between the A and B
ports.
This device is fully specified for partial-power-down applications using I
off
. The I
off
feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SSOP - DL
Tube
SN74CB3T16211DL
CB3T16211
SSOP - DL
Tape and reel
SN74CB3T16211DLR
CB3T16211
TSSOP - DGG
Tube
SN74CB3T16211DGG
CB3T16211
-40
C to 85
C
TSSOP - DGG
Tape and reel
SN74CB3T16211DGGR
CB3T16211
-40 C to 85 C
TVSOP - DGV
Tape and reel
SN74CB3T16211DGVR
KR211
VFBGA - ZQL
(PB-Free)
Tape and reel
SN74CB3T16211ZQLR
KR211
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
SN74CB3T16211
24 BIT FET BUS SWITCH
2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
SCDS147B - OCTOBER 2003 - REVISED JANUARY 2005
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
terminal assignments
1
2
3
4
5
6
A
1A2
1A1
NC
1OE
2OE
1B1
B
1A5
1A4
1A3
1B2
1B3
1B4
C
1A7
GND
1A6
1B5
GND
1B6
D
1A10
1A8
1A9
1B8
1B7
1B9
E
1A12
1A11
1B10
1B11
F
2A1
2A2
2B1
1B12
G
VCC
GND
2A3
2B3
GND
2B2
H
2A4
2A5
2A6
2B6
2B5
2B4
J
2A7
2A8
2A9
2B9
2B8
2B7
K
2A10
2A11
2A12
2B12
2B11
2B10
NC - No internal connection
FUNCTION TABLE
(each 12-bit bus switch)
INPUT
INPUT/OUTPUT
FUNCTION
INPUT
OE
INPUT/OUTPUT
A
FUNCTION
L
B
A port = B port
H
Z
Disconnect
logic diagram (positive logic)
1A1
SW
1B1
1A12
1OE
SW
1B12
2A1
SW
2B1
2A12
2OE
SW
2B12
2
14
56
15
28
55
54
42
41
29
ZQL PACKAGE
(TOP VIEW)
A
B
C
D
E
F
G
H
J
K
1
2
3
4
5
6
SN74CB3T16211
24 BIT FET BUS SWITCH
2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
SCDS147B - OCTOBER 2003 - REVISED JANUARY 2005
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
simplified schematic, each FET switch (SW)
A
EN
B
Control
Circuit
VG
Gate voltage (VG) is equal to approximately VCC + VT when the switch is ON and VI
>
VCC + VT.
Internal enable signal applied to the switch
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
(see Note 1)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control input voltage range, V
IN
(see Notes 1 and 2)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch I/O voltage range, V
I/O
(see Notes 1, 2, and 3)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control input clamp current, I
IK
(V
IN
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O port clamp current, I
I/OK
(V
I/O
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ON-state switch current, I
I/O
(see Note 4)
128 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND terminals
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 5): DGG package
64
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package
48
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package
56
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ZQL package
42
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. All voltages are with respect to ground, unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. VI and VO are used to denote specific conditions for VI/O.
4. II and IO are used to denote specific conditions for II/O.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 6)
MIN
MAX
UNIT
VCC
Supply voltage
2.3
3.6
V
VIH
High-level control input voltage
VCC = 2.3 V to 2.7 V
1.7
5.5
V
VIH
High-level control input voltage
VCC = 2.7 V to 3.6 V
2
5.5
V
VIL
Low-level control input voltage
VCC = 2.3 V to 2.7 V
0
0.7
V
VIL
Low-level control input voltage
VCC = 2.7 V to 3.6 V
0
0.8
V
VI/O
Data input/output voltage
0
5.5
V
TA
Operating free-air temperature
-40
85
C
NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74CB3T16211
24 BIT FET BUS SWITCH
2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
SCDS147B - OCTOBER 2003 - REVISED JANUARY 2005
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIK
VCC = 3 V,
II = -18 mA
-1.2
V
VOH
See Figures 3 and 4
IIN
Control
inputs
VCC = 3.6 V,
VIN = 3.6 V to 5.5 V or GND
10
A
VCC = 3.6 V,
VI = VCC - 0.7 V to 5.5 V
20
II
VCC = 3.6 V,
Switch ON,
V
= V
or GND
VI = 0.7 V to VCC - 0.7 V
-40
A
II
Switch ON,
VIN = VCC or GND
VI = 0 to 0.7 V
5
A
IOZ
VCC = 3.6 V,
VO = 0 to 5.5 V,
VI = 0,
Switch OFF,
VIN = VCC or GND
10
A
Ioff
VCC = 0,
VO = 0 to 5.5 V,
VI = 0
10
A
ICC
VCC = 3.6 V,
II/O = 0,
VI = VCC or GND
70
A
ICC
II/O = 0,
Switch ON or OFF,
VIN = VCC or GND
VI = 5.5 V
70
A
ICC
Control
inputs
VCC = 3 V to 3.6 V,
One input at VCC - 0.6 V,
Other inputs at VCC or GND
300
A
Cin
Control
inputs
VCC = 3.3 V,
VIN = VCC or GND
4
pF
Cio(OFF)
VCC = 3.3 V,
VI/O = 5.5 V, 3.3 V, or GND,
Switch OFF,
VIN = VCC or GND
5
pF
Cio(ON)
VCC = 3.3 V,
Switch ON,
VI/O = 5.5 V or 3.3 V
5
pF
Cio(ON)
CC
Switch ON,
VIN = VCC or GND
VI/O = GND
13
pF
VCC = 2.3 V,
TYP at VCC = 2.5 V,
IO = 24 mA
5
9.5
ron
CC
TYP at VCC = 2.5 V,
VI = 0
IO = 16 mA
5
9.5
ron
VCC = 3 V,
IO = 64 mA
5
8.5
VCC = 3 V,
VI = 0
IO = 32 mA
5
8.5
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25
C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined by the
lower of the voltages of the two (A or B) terminals.
SN74CB3T16211
24 BIT FET BUS SWITCH
2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
SCDS147B - OCTOBER 2003 - REVISED JANUARY 2005
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.5 V
0.2 V
VCC = 3.3 V
0.3 V
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
UNIT
tpd
A or B
B or A
0.15
0.25
ns
ten
OE
A or B
1
12
1
10
ns
tdis
OE
A or B
1
7.5
1
8.5
ns
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
SN74CB3T16211
24 BIT FET BUS SWITCH
2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
SCDS147B - OCTOBER 2003 - REVISED JANUARY 2005
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOH
VOL
CL
(see Note A)
TEST CIRCUIT
S1
2
VCC
Open
GND
RL
RL
tPLH
tPHL
Output
Waveform 1
S1 at 2
VCC
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOH
VOL
0 V
VOL + V
VOH - V
0 V
Output
Control
(VIN)
VCC
VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
NOTES: B. CL includes probe and jig capacitance.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
E. The outputs are measured one at a time, with one transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state
resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
I. All parameters and waveforms are not applicable to all devices.
50
VG1
VCC
DUT
50
VIN
50
VG2
50
VI
TEST
RL
S1
V
CL
2.5 V
0.2 V
3.3 V
0.3 V
VCC
VI
tPHZ/tPZH
tPLZ/tPZL
tpd(s)
2.5 V
0.2 V
3.3 V
0.3 V
2.5 V
0.2 V
3.3 V
0.3 V
Open
Open
2
VCC
2
VCC
Open
Open
500
500
500
500
500
500
3.6 V or GND
5.5 V or GND
GND
GND
3.6 V
5.5 V
30 pF
50 pF
30 pF
50 pF
30 pF
50 pF
0.15 V
0.3 V
0.15 V
0.3 V
Output
Control
(VIN)
Input Generator
Input Generator
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VO
Figure 2. Test Circuit and Voltage Waveforms
SN74CB3T16211
24 BIT FET BUS SWITCH
2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
SCDS147B - OCTOBER 2003 - REVISED JANUARY 2005
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
0
1
2
3
4
0
1
2
3
4
5
6
V
O
Output V
oltage V
0
VI - Input Voltage - V
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
VI - Input Voltage - V
1
2
3
4
0
1
2
3
4
5
6
VCC = 3 V
IO = 1
A
TA = 25
C
VCC = 2.3 V
IO = 1
A
TA = 25
C
V
O
Output V
o
ltage V
Figure 3. Data Output Voltage vs Data Input Voltage
SN74CB3T16211
24 BIT FET BUS SWITCH
2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
SCDS147B - OCTOBER 2003 - REVISED JANUARY 2005
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
1.5
2
2.5
3
3.5
4
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
1.5
2
2.5
3
3.5
4
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
1.5
2
2.5
3
3.5
4
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
VCC - Supply Voltage - V
VCC = 2.3 V to 3.6 V
VI = 5.5 V
TA = 85
C
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
VCC - Supply Voltage - V
VCC = 2.3 V to 3.6 V
VI = 5.5 V
TA = 25
C
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
VCC - Supply Voltage - V
VCC = 2.3 V to 3.6 V
VI = 5.5 V
TA = -40
C
100
A
8 mA
16 mA
24 mA
100
A
8 mA
16 mA
24 mA
100
A
8 mA
16 mA
24 mA
V
OH
Output V
oltage High V
V
OH
Output V
oltage High V
V
OH
Output V
oltage High V
Figure 4. V
OH
Values
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
74CB3T16211DGGRE4
ACTIVE
TSSOP
DGG
56
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
74CB3T16211DGVRE4
ACTIVE
TVSOP
DGV
56
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74CB3T16211DGG
PREVIEW
TSSOP
DGG
56
35
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74CB3T16211DGGR
ACTIVE
TSSOP
DGG
56
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74CB3T16211DGVR
ACTIVE
TVSOP
DGV
56
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74CB3T16211DL
ACTIVE
SSOP
DL
56
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74CB3T16211DLR
ACTIVE
SSOP
DL
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74CB3T16211ZQLR
ACTIVE
VFBGA
ZQL
56
1000
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Jun-2005
Addendum-Page 1
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