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Электронный компонент: SN74HC595DBR

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SN54HC595, SN74HC595
8 BIT SHIFT REGISTERS
WITH 3 STATE OUTPUT REGISTERS
SCLS041G - DECEMBER 1982 - REVISED FEBRUARY 2004
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
8-Bit Serial-In, Parallel-Out Shift
D
Wide Operating Voltage Range of 2 V to 6 V
D
High-Current 3-State Outputs Can Drive Up
To 15 LSTTL Loads
D
Low Power Consumption, 80-
A Max I
CC
D
Typical t
pd
= 13 ns
D
6-mA Output Drive at 5 V
D
Low Input Current of 1
A Max
D
Shift Register Has Direct Clear
description/ordering information
The 'HC595 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. The storage register has parallel
3-state outputs. Separate clocks are provided for
both the shift and storage register. The shift
register has a direct overriding clear (SRCLR)
input, serial (SER) input, and serial outputs for
cascading. When the output-enable (OE) input is
high, the outputs are in the high-impedance state.
Both the shift register clock (SRCLK) and storage
register clock (RCLK) are positive-edge triggered.
If both clocks are connected together, the shift
register always is one clock pulse ahead of the
storage register.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP - N
Tube of 25
SN74HC595N
SN74HC595N
Tube of 40
SN74HC595D
SOIC - D
Reel of 2500
SN74HC595DR
HC595
-40
C to 85
C
SOIC - D
Reel of 250
SN74HC595DT
HC595
-40
C to 85
C
SOIC - DW
Tube of 40
SN74HC595DW
HC595
SOIC - DW
Reel of 2000
SN74HC595DWR
HC595
SOP - NS
Reel of 2000
SN74HC595NSR
HC595
SSOP - DB
Reel of 2000
SN74HC595DBR
HC595
CDIP - J
Tube of 25
SNJ54HC595J
SNJ54HC595J
-55
C to 125
C
CFP - W
Tube of 150
SNJ54HC595W
SNJ54HC595W
-55 C to 125 C
LCCC - FK
Tube of 55
SNJ54HC595FK
SNJ54HC595FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54HC595 . . . J OR W PACKAGE
SN74HC595 . . . D, DB, DW, N, OR NS PACKAGE
(TOP VIEW)
SN54HC595 . . . FK PACKAGE
(TOP VIEW)
NC - No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
GND
V
CC
Q
A
SER
OE
RCLK
SRCLK
SRCLR
Q
H
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
SER
OE
NC
RCLK
SRCLK
Q
D
Q
E
NC
Q
F
Q
G
Q
NC
SRCLR
H
GND
NC
C
Q
B
V
CC
Q
A
Q
H
Q
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HC595, SN74HC595
8 BIT SHIFT REGISTERS
WITH 3 STATE OUTPUT REGISTERS
SCLS041G - DECEMBER 1982 - REVISED FEBRUARY 2004
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
FUNCTION
SER
SRCLK
SRCLR
RCLK
OE
FUNCTION
X
X
X
X
H
Outputs QA-QH are disabled.
X
X
X
X
L
Outputs QA-QH are enabled.
X
X
L
X
X
Shift register is cleared.
L
H
X
X
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
H
H
X
X
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
X
X
X
X
Shift-register data is stored in the storage register.
SN54HC595, SN74HC595
8 BIT SHIFT REGISTERS
WITH 3 STATE OUTPUT REGISTERS
SCLS041G - DECEMBER 1982 - REVISED FEBRUARY 2004
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
3R
C3
3S
1D
C1
R
3R
C3
3S
2R
C2
R
2S
3R
C3
3S
2R
C2
R
2S
3R
C3
3S
2R
C2
R
2S
3R
C3
3S
2R
C2
R
2S
3R
C3
3S
2R
C2
R
2S
3R
C3
3S
2R
C2
R
2S
3R
C3
3S
2R
C2
R
2S
13
12
10
11
14
15
1
2
3
4
5
6
7
9
QA
QB
QC
QD
QE
QF
QG
QH
QH
OE
SRCLR
RCLK
SRCLK
SER
Pin numbers shown are for the D, DB, DW, J, N, NS, and W packages.
SN54HC595, SN74HC595
8 BIT SHIFT REGISTERS
WITH 3 STATE OUTPUT REGISTERS
SCLS041G - DECEMBER 1982 - REVISED FEBRUARY 2004
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing diagram
SRCLK
SER
RCLK
SRCLR
OE
QA
QB
QC
QD
QE
QF
QG
QH
QH'
implies that the output is in 3-State mode.
NOTE:
SN54HC595, SN74HC595
8 BIT SHIFT REGISTERS
WITH 3 STATE OUTPUT REGISTERS
SCLS041G - DECEMBER 1982 - REVISED FEBRUARY 2004
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
35 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
70 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
73
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package
82
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
57
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
67
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
64
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC595
SN74HC595
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
2
5
6
2
5
6
V
VCC = 2 V
1.5
1.5
VIH
High-level input voltage
VCC = 4.5 V
3.15
3.15
V
VIH
High-level input voltage
VCC = 6 V
4.2
4.2
V
VCC = 2 V
0.5
0.5
VIL
Low-level input voltage
VCC = 4.5 V
1.35
1.35
V
VIL
Low-level input voltage
VCC = 6 V
1.8
1.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 2 V
1000
1000
t/
v
Input transition rise/fall time
VCC = 4.5 V
500
500
ns
t/
v
Input transition rise/fall time
VCC = 6 V
400
400
ns
TA
Operating free-air temperature
-55
125
-40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.