SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D DECEMBER 1982 REVISED JULY 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Wide Operating Voltage Range of 2 V to 6 V
D
Outputs Can Drive Up To 10 LSTTL Loads
D
Low Power Consumption, 40-
A Max I
CC
D
Typical t
pd
= 15 ns
D
4-mA Output Drive at 5 V
D
Low Input Current of 1
A Max
description/ordering information
The 'HC74 devices contain two independent
D-type positive-edge-triggered flip-flops. A low
level at the preset (PRE) or clear (CLR) inputs sets
or resets the outputs, regardless of the levels of
the other inputs. When PRE and CLR are inactive
(high), data at the data (D) input meeting the setup
time requirements are transferred to the outputs
on the positive-going edge of the clock (CLK)
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of CLK.
Following the hold-time interval, data at the
D input can be changed without affecting the
levels at the outputs.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP N
Tube of 25
SN74HC74N
SN74HC74N
Tube of 50
SN74HC74D
SOIC D
Reel of 2500
SN74HC74DR
HC74
Reel of 250
SN74HC74DT
40
C to 85
C
SOP NS
Reel of 2000
SN74HC74NSR
HC74
SSOP DB
Reel of 2000
SN74HC74DBR
HC74
Tube of 90
SN74HC74PW
TSSOP PW
Reel of 2000
SN74HC74PWR
HC74
Reel of 250
SN74HC74PWT
CDIP J
Tube of 25
SNJ54HC74J
SNJ54HC74J
55
C to 125
C
CFP W
Tube of 150
SNJ54HC74W
SNJ54HC74W
LCCC FK
Tube of 55
SNJ54HC74FK
SNJ54HC74FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
SN54HC74 . . . J OR W PACKAGE
SN74HC74 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
NC
2CLK
NC
2PRE
1CLK
NC
1PRE
NC
1Q
1D
1CLR
NC
2Q
2Q
V
2CLR
1Q
GND
NC
SN54HC74 . . . FK PACKAGE
(TOP VIEW)
CC
NC No internal connection
Copyright
2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D DECEMBER 1982 REVISED JULY 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
X
Q0
Q0
This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
logic diagram (positive logic)
PRE
CLK
D
CLR
Q
Q
C
C
C
C
C
C
C
C
C
C
TG
TG
TG
TG
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
86
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package
96
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
80
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
76
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
113
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D DECEMBER 1982 REVISED JULY 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54HC74
SN74HC74
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
2
5
6
2
5
6
V
VCC = 2 V
1.5
1.5
VIH
High-level input voltage
VCC = 4.5 V
3.15
3.15
V
VCC = 6 V
4.2
4.2
VCC = 2 V
0.5
0.5
VIL
Low-level input voltage
VCC = 4.5 V
1.35
1.35
V
VCC = 6 V
1.8
1.8
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 2 V
1000
1000
t/
v
Input transition rise/fall time
VCC = 4.5 V
500
500
ns
VCC = 6 V
400
400
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54HC74
SN74HC74
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
1.9
1.998
1.9
1.9
IOH = 20
A
4.5 V
4.4
4.499
4.4
4.4
VOH
VI = VIH or VIL
6 V
5.9
5.999
5.9
5.9
V
IOH = 4 mA
4.5 V
3.98
4.3
3.7
3.84
IOH = 5.2 mA
6 V
5.48
5.8
5.2
5.34
2 V
0.002
0.1
0.1
0.1
IOL = 20
A
4.5 V
0.001
0.1
0.1
0.1
VOL
VI = VIH or VIL
6 V
0.001
0.1
0.1
0.1
V
IOL = 4 mA
4.5 V
0.17
0.26
0.4
0.33
IOL = 5.2 mA
6 V
0.15
0.26
0.4
0.33
II
VI = VCC or 0
6 V
0.1
100
1000
1000
nA
ICC
VI = VCC or 0,
IO = 0
6 V
4
80
40
A
Ci
2 V to 6 V
3
10
10
10
pF
SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D DECEMBER 1982 REVISED JULY 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25
C
SN54HC74
SN74HC74
UNIT
VCC
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
6
4.2
5
fclock
Clock frequency
4.5 V
31
21
25
MHz
6 V
0
36
0
25
0
29
2 V
100
150
125
PRE or CLR low
4.5 V
20
30
25
t
Pulse duration
6 V
17
25
21
ns
tw
Pulse duration
2 V
80
120
100
ns
CLK high or low
4.5 V
16
24
20
6 V
14
20
17
2 V
100
150
125
Data
4.5 V
20
30
25
t
Setup time before CLK
6 V
17
25
21
ns
tsu
Setup time before CLK
2 V
25
40
30
ns
PRE or CLR inactive
4.5 V
5
8
6
6 V
4
7
5
2 V
0
0
0
th
Hold time, data after CLK
4.5 V
0
0
0
ns
6 V
0
0
0
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25
C
SN54HC74
SN74HC74
UNIT
PARAMETER
(INPUT)
(OUTPUT)
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
6
10
4.2
5
fmax
4.5 V
31
50
21
25
MHz
6 V
36
60
25
29
2 V
70
230
345
290
PRE or CLR
Q or Q
4.5 V
20
46
69
58
t d
6 V
15
39
59
49
ns
tpd
2 V
70
175
250
220
ns
CLK
Q or Q
4.5 V
20
35
50
44
6 V
15
30
42
37
2 V
28
75
110
95
tt
Q or Q
4.5 V
8
15
22
19
ns
6 V
6
13
19
16
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance per flip-flop
No load
35
pF
SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D DECEMBER 1982 REVISED JULY 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
50%
50%
50%
10%
10%
90%
90%
VCC
VCC
0 V
0 V
tr
tf
Reference
Input
Data
Input
50%
High-Level
Pulse
50%
VCC
0 V
50%
50%
VCC
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%
50%
10%
10%
90%
90%
VCC
VOH
VOL
0 V
tr
tf
Input
In-Phase
Output
50%
tPLH
tPHL
50%
50%
10%
10%
90%
90%
VOH
VOL
tr
tf
tPHL
tPLH
Out-of-Phase
Output
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
1 MHz, ZO = 50
, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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