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FEATURES
DCT OR DCU PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1A
1B
2Y
GND
V
CC
1Y
2B
2A
4
3
2
1
5
6
7
8
GND
2Y
1B
1A
2A
2B
1Y
V
CC
YEP OR YZP PACKAGE
(BOTTOM VIEW)
DESCRIPTION/ORDERING INFORMATION
SN74LVC2G132
DUAL 2-INPUT NAND GATE
WITH SCHMITT-TRIGGER INPUTS
SCES547A FEBRUARY 2004 REVISED JUNE 2005
Available in Texas Instruments NanoStarTM
and NanoFreeTM Packages
Supports 5-V V
CC
Operation
Inputs Accept Voltages to 5.5 V
Max t
pd
of 5.3 ns at 3.3 V
Low Power Consumption, 10-
A Max I
CC
24-mA Output Drive at 3.3 V
Typical V
OLP
(Output Ground Bounce) <0.8 V
at V
CC
= 3.3 V, T
A
= 25C
Typical V
OHV
(Output V
OH
Undershoot) >2 V at
V
CC
= 3.3 V, T
A
= 25C
I
off
Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC2G132 contains two inverters and performs the Boolean function Y = A
B or Y = A + B in positive
logic. The device functions as two independent inverters, but because of Schmitt action, it has different input
threshold levels for positive-going (V
T+
) and negative-going (V
T-
) signals.
NanoStarTM and NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
(2)
NanoStarTM WCSP (DSBGA)
SN74LVC2G132YEPR
0.23-mm Large Bump YEP
Reel of 3000
_ _ _D5_
NanoFreeTM WCSP (DSBGA)
0.23-mm Large Bump YZP
SN74LVC2G132YZPR
40C to 85C
(Pb-free)
SSOP DCT
Reel of 3000
SN74LVC2G132DCTR
C3B_ _ _
Reel of 3000
SN74LVC2G132DCUR
VSSOP DCU
C3B_
Reel of 250
SN74LVC2G132DCUT
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2)
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 20042005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
1A
1B
1Y
2A
2B
2Y
7
3
1
2
5
6
Absolute Maximum Ratings
(1)
SN74LVC2G132
DUAL 2-INPUT NAND GATE
WITH SCHMITT-TRIGGER INPUTS
SCES547A FEBRUARY 2004 REVISED JUNE 2005
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
(EACH GATE)
INPUTS
OUTPUT
Y
A
B
L
L
H
L
H
H
H
L
H
H
H
L
LOGIC DIAGRAM (POSITIVE LOGIC)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
CC
Supply voltage range
0.5
6.5
V
V
I
Input voltage range
(2)
0.5
6.5
V
V
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
0.5
6.5
V
V
O
Voltage range applied to any output in the high or low state
(2) (3)
0.5
V
CC
+ 0.5
V
I
IK
Input clamp current
V
I
< 0
50
mA
I
OK
Output clamp current
V
O
< 0
50
mA
I
O
Continuous output current
50
mA
Continuous current through V
CC
or GND
100
mA
DCT package
220
JA
Package thermal impedance
(4)
DCU package
227
C/W
YEP/YZP package
102
T
stg
Storage temperature range
65
150
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3)
The value of V
CC
is provided in the recommended operating conditions table.
(4)
The package thermal impedance is calculated in accordance with JESD 51-7
2
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Recommended Operating Conditions
(1)
SN74LVC2G132
DUAL 2-INPUT NAND GATE
WITH SCHMITT-TRIGGER INPUTS
SCES547A FEBRUARY 2004 REVISED JUNE 2005
MIN
MAX
UNIT
Operating
1.65
5.5
V
CC
Supply voltage
V
Data retention only
1.5
V
I
Input voltage
0
5.5
V
V
O
Output voltage
0
V
CC
V
V
CC
= 1.65 V
4
V
CC
= 2.3 V
8
I
OH
High-level output current
16
mA
V
CC
= 3 V
24
V
CC
= 4.5 V
32
V
CC
= 1.65 V
4
V
CC
= 2.3 V
8
I
OL
Low-level output current
16
mA
V
CC
= 3 V
24
V
CC
= 4.5 V
32
T
A
Operating free-air temperature
40
85
C
(1)
All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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Electrical Characteristics
SN74LVC2G132
DUAL 2-INPUT NAND GATE
WITH SCHMITT-TRIGGER INPUTS
SCES547A FEBRUARY 2004 REVISED JUNE 2005
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP
(1)
MAX
UNIT
1.65 V
0.79
1.16
2.3 V
1.11
1.56
V
T+
Positive-going
3 V
1.5
1.87
V
input threshold voltage
4.5 V
2.16
2.74
5.5 V
2.61
3.33
1.65 V
0.39
0.62
2.3 V
0.58
0.87
V
T
Negative-going
3 V
0.84
1.14
V
input threshold voltage
4.5 V
1.41
1.79
5.5 V
1.87
2.29
1.65 V
0.37
0.62
2.3 V
0.48
0.77
V
T
Hysteresis
3 V
0.56
0.87
V
(V
T+
V
T
)
4.5 V
0.71
1.04
5.5 V
0.71
1.11
I
OH
= 100
A
1.65 V to 5.5 V
V
CC
0.1
I
OH
= 4 mA
1.65 V
1.2
I
OH
= 8 mA
2.3 V
1.9
V
OH
V
I
OH
= 16 mA
2.4
3 V
I
OH
= 24 mA
2.3
I
OH
= 32 mA
4.5 V
3.8
I
OL
= 100
A
1.65 V to 5.5 V
0.1
I
OL
= 4 mA
1.65 V
0.45
I
OL
= 8 mA
2.3 V
0.3
V
OL
V
I
OL
= 16 mA
0.4
3 V
I
OL
= 24 mA
0.55
I
OL
= 32 mA
4.5 V
0.55
I
I
A or B inputs
V
I
= 5.5 V or GND
1.65 V to 5.5 V
1
A
I
off
V
I
or V
O
= 5.5 V
0
10
A
I
CC
V
I
= V
CC
or GND,
I
O
= 0
1.65 V to 5.5 V
10
A
I
CC
One input at V
CC
0.6 V, Other inputs at V
CC
or GND
3 V to 5.5 V
500
A
C
i
V
I
= V
CC
or GND
3.3 V
3.5
pF
(1)
All typical values are at V
CC
= 3.3 V, T
A
= 25C.
4
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Switching Characteristics
Switching Characteristics
Operating Characteristics
SN74LVC2G132
DUAL 2-INPUT NAND GATE
WITH SCHMITT-TRIGGER INPUTS
SCES547A FEBRUARY 2004 REVISED JUNE 2005
over recommended operating free-air temperature range, C
L
= 15 pF (unless otherwise noted) (see
Figure 1
)
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 5 V
FROM
TO
0.15 V
0.2 V
0.3 V
0.5 V
PARAMETER
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
pd
A or B
Y
4
16
2.5
7
2
5.3
1.5
4.4
ns
over recommended operating free-air temperature range, C
L
= 30 pF or 50 pF (unless otherwise noted) (see
Figure 2
)
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 5 V
FROM
TO
0.15 V
0.2 V
0.3 V
0.5 V
PARAMETER
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
pd
A or B
Y
4
16
3
7.5
2
6
2
5
ns
T
A
= 25C
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 5 V
TEST
PARAMETER
UNIT
CONDITIONS
TYP
TYP
TYP
TYP
C
pd
Power dissipation capacitance
f = 10 MHz
17
18
18
20
pF
5
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