1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
B8
B7
B6
B5
B4
B3
B2
B1
OEAB
CLKAB
CLKENAB
GND
V
CC
A8
A7
A6
A5
A4
A3
A2
A1
OEBA
CLKBA
CLKENBA
SN54LVT2952 . . . JT PACKAGE
SN74LVT2952 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
CLKAB
CLKENAB
GND
NC
CLKENBA
CLKBA
OEBA
B6
NC
A7
V
B7
B8
A8
CC
3 2 1 28 27
12 13 14 15 16 17 18
5
6
7
8
9
10
11
25
24
23
22
21
20
19
A6
A5
A4
NC
A3
A2
A1
B5
B4
B3
NC
B2
B1
OEAB
4
26
SN54LVT2952 . . . FK PACKAGE
(TOP VIEW)
NC No internal connection
SN54LVT2952, SN74LVT2952
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS152E MAY 1992 REVISED JULY 1995
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
CC
)
D
Support Unregulated Battery Operation
Down to 2.7 V
D
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
C
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
D
Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
D
Support Live Insertion
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (JT) DIPs
description
These octal bus transceivers and registers are
designed specifically for low-voltage (3.3-V) V
CC
operation, but with the capability to provide a TTL
interface to a 5-V system environment.
The 'LVT2952 consist of two 8-bit back-to-back
registers that store data flowing in both directions
between two bidirectional buses. Data on the A or
B bus is stored in the registers on the low-to-high
transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB or CLKENBA) input
is low. Taking the output-enable (OEAB or OEBA) input low accesses the data on either port.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVT2952 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LVT2952 is characterized for operation over the full military temperature range of 55
C to 125
C.
The SN74LVT2952 is characterized for operation from 40
C to 85
C.
Copyright
1995, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LVT2952, SN74LVT2952
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS152E MAY 1992 REVISED JULY 1995
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OUTPUT
CLKENAB
CLKAB
OEAB
A
B
H
X
L
X
B0
X
H or L
L
X
B0
L
L
L
L
L
L
H
H
X
X
H
X
Z
A-to-B data flow is shown; B-to-A data flow is similar
but uses CLKENBA, CLKBA, and OEBA.
Level of B before the indicated steady-state input
conditions were established
logic symbol
3
1
B1
8
A1
16
A2
17
A3
18
A4
19
EN3
15
1 C5
B2
7
B3
6
B4
5
A5
20
A6
21
A7
22
A8
23
B5
4
B6
3
B7
2
B8
1
G2
11
G1
13
EN4
9
2 C6
4
5D
1
6D
OEBA
CLKENBA
OEAB
CLKENAB
14
CLKBA
10
CLKAB
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, and PW packages.
SN54LVT2952, SN74LVT2952
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS152E MAY 1992 REVISED JULY 1995
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
C1
C1
1D
1D
To Seven Other Channels
B1
A1
8
16
OEBA
CLKBA
CLKENBA
OEAB
CLKAB
CLKENAB
11
10
9
13
14
15
Pin numbers shown are for the DB, DW, JT, and PW packages.
SN54LVT2952, SN74LVT2952
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS152E MAY 1992 REVISED JULY 1995
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state or power-off state, V
O
(see Note 1)
0.5 V to 7 V
. . . .
Current into any output in the low state, I
O
: SN54LVT2952
96 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74LVT2952
128 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
O
(see Note 2): SN54LVT2952
48 mA
. . . . . . . . . . . . . . . . . . . . . . . .
SN74LVT2952
64 mA
. . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at T
A
= 55
C (in still air) (see Note 3): DB package
0.65 W
. . . . . . . . . . . . . . . . . . .
DW package
1.7 W
. . . . . . . . . . . . . . . . . . .
PW package
0.7 W
. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The maximum package power dissipation is calculated using a junction temperature of 150
C and a board trace length of 750 mils.
For more information, refer to the
Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 4)
SN54LVT2952
SN74LVT2952
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
2.7
3.6
2.7
3.6
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
5.5
5.5
V
IOH
High-level output current
24
32
mA
IOL
Low-level output current
48
64
mA
t /
v
Input transition rise or fall rate
Outputs enabled
10
10
ns / V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVT2952, SN74LVT2952
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS152E MAY 1992 REVISED JULY 1995
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LVT2952
SN74LVT2952
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 2.7 V,
II = 18 mA
1.2
1.2
V
VCC = MIN to MAX, IOH = 100
A
VCC 0.2
VCC 0.2
VOH
VCC = 2.7 V,
IOH = 8 mA
2.4
2.4
V
VOH
VCC = 3 V
IOH = 24 mA
2
V
VCC = 3 V
IOH = 32 mA
2
VCC = 2 7 V
IOL = 100
A
0.2
0.2
VCC = 2.7 V
IOL = 24 mA
0.5
0.5
VOL
IOL = 16 mA
0.4
0.4
V
VOL
VCC = 3 V
IOL = 32 mA
0.5
0.5
V
VCC = 3 V
IOL = 48 mA
0.55
IOL = 64 mA
0.55
VCC = 3.6 V,
VI = VCC or GND
Control inputs
1
1
VCC = 0 or MAX,
VI = 5.5 V
Control inputs
10
10
II
VI = 5.5 V
20
20
A
VCC = 3.6 V
VI = VCC
A or B ports
5
5
VI = 0
10
10
Ioff
VCC = 0,
VI or VO = 0 to 4.5 V
100
A
II(h ld)
VCC = 3 V
VI = 0.8 V
A or B ports
75
75
A
II(hold)
VCC = 3 V
VI = 2 V
A or B ports
75
75
A
IOZH
VCC = 3.6 V,
VO = 3 V
1
1
A
IOZL
VCC = 3.6 V,
VO = 0.5 V
1
1
A
V
3 6 V
I
0
Outputs high
0.13
0.19
0.13
0.19
ICC
VCC = 3.6 V,
IO = 0,
VI = VCC or GND
Outputs low
8.8
12
8.8
12
mA
VI = VCC or GND
Outputs disabled
0.13
0.19
0.13
0.19
ICC
VCC = 3 V to 3.6 V,
One input at VCC 0.6 V,
Other inputs at VCC or GND
0.2
0.2
mA
Ci
VI = 3 V or 0
4.5
4.5
pF
Cio
VO = 3 V or 0
11.5
11.5
pF
All typical values are at VCC = 3.3 V, TA = 25
C.
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
Unused terminals at VCC or GND
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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