SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A OCTOBER 1976 REVISED FEBRUARY 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
3-State Outputs Drive Bus Lines Directly
D
PNP Inputs Reduce dc Loading on Bus
Lines
D
Hysteresis at Bus Inputs Improves Noise
Margins
D
Typical Propagation Delay Times Port to
Port, 8 ns
TYPE
IOL
(SINK
CURRENT)
IOH
(SOURCE
CURRENT)
SN54LS245
12 mA
12 mA
SN74LS245
24 mA
15 mA
description
These octal bus transceivers are designed for
asynchronous two-way communication between
data buses. The control-function implementation
minimizes external timing requirements.
The devices allow data transmission from the
A bus to the B bus or from the B bus to the A bus,
depending on the logic level at the
direction-control (DIR) input. The output-enable
(OE) input can disable the device so that the
buses are effectively isolated.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP N
Tube
SN74LS245N
SN74LS245N
SOIC DW
Tube
SN74LS245DW
LS245
0
C to 70
C
SOIC DW
Tape and reel
SN74LS245DWR
LS245
SOP NS
Tape and reel
SN74LS245NSR
74LS245
SSOP DB
Tape and reel
SN74LS245DBR
LS245
CDIP J
Tube
SN54LS245J
SN54LS245J
55
C to 125
C
CDIP J
Tube
SNJ54LS245J
SNJ54LS245J
55
C to 125
C
CFP W
Tube
SNJ54LS245W
SNJ54LS245W
LCCC FK
Tube
SN54LS245FK
SN54LS245FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
B1
B2
B3
B4
B5
A3
A4
A5
A6
A7
A2
A1
DIR
B7
B6
OE
A8
GND
B8
V
CC
SN54LS245 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
SN54LS245 . . . J OR W PACKAGE
SN74LS245 . . . DB, DW, N, OR NS PACKAGE
(TOP VIEW)
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A OCTOBER 1976 REVISED FEBRUARY 2002
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OPERATION
OE
DIR
OPERATION
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC
Input
9 k
NOM
TYPICAL OF ALL OUTPUTS
Output
VCC
50
NOM
logic diagram (positive logic)
DIR
OE
A1
B1
1
2
18
19
To Seven Other Channels
SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A OCTOBER 1976 REVISED FEBRUARY 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
CC
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
(see Note 1)
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
q
JA
(see Note 2): DB package
70
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
69
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
60
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. All voltage values are with respect to GND.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
SN54LS245
SN74LS245
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.75
5
5.25
V
IOH
High-level output current
12
15
mA
IOL
Low-level output current
12
24
mA
TA
Operating free-air temperature
55
125
0
70
C
SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A OCTOBER 1976 REVISED FEBRUARY 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LS245
SN74LS245
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.7
0.8
V
VIK
Input clamp voltage
VCC = MIN,
II = 18 mA
1.5
1.5
V
Hysteresis (VT+ VT)
A or B
VCC = MIN
0.2
0.4
0.2
0.4
V
VOH
High level output voltage
VCC = MIN,
VIH 2 V
IOH = 3 mA
2.4
3.4
2.4
3.4
V
VOH
High-level output voltage
VIH = 2 V,
VIL = VIL(max)
IOH = MAX
2
2
V
VOL
Low level output voltage
VCC = MIN,
VIH 2 V
IOL = 12 mA
0.4
0.4
V
VOL
Low-level output voltage
VIH = 2 V,
VIL = VIL(max)
IOL = 24 mA
0.5
V
IOZH
Off-state output current,
high-level voltage applied
VCC = MAX,
OE at 2 V
VO = 2.7 V
20
20
A
IOZL
Off-state output current,
low-level voltage applied
VCC = MAX,
OE at 2 V
VO = 0.4 V
200
200
A
II
Input current at
maximum input
A or B
VCC = MAX
VI = 5.5 V
0.1
0.1
mA
II
maximum input
voltage
DIR or OE
VCC = MAX
VI = 7 V
0.1
0.1
mA
IIH
High-level input current
VCC = MAX,
VIH = 2.7 V
20
20
A
IIL
Low-level input current
VCC = MAX,
VIL = 0.4 V
0.2
0.2
mA
IOS
Short-circuit output current
VCC = MAX
40
225
40
225
mA
Total, outputs high
48
70
48
70
ICC
Supply current
Total, outputs low
VCC = MAX
Outputs open
62
90
62
90
mA
Outputs at high Z
64
95
64
95
For conditions shown as MIN or MAX, use the appropriate values specified under recommended operating conditions.
All typical values are at VCC = 5 V, TA = 25
C.
Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
switching characteristics, V
CC
= 5 V, T
A
= 25
C (see Figure 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time, low- to high-level output
C
45 pF
R
667
W
8
12
ns
tPHL
Propagation delay time high to low level output
CL = 45 pF,
RL = 667
W
8
12
ns
tPHL
Propagation delay time, high- to low-level output
8
12
tPZL
Output enable time to low level
CL = 45 pF
RL = 667
W
27
40
ns
tPZH
Output enable time to high level
CL = 45 pF,
RL = 667
W
25
40
ns
tPLZ
Output disable time from low level
CL = 5 pF
RL = 667
W
15
25
ns
tPHZ
Output disable time from high level
CL = 5 pF,
RL = 667
W
15
28
ns
SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A OCTOBER 1976 REVISED FEBRUARY 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/ 74LS DEVICES
tPHL
tPLH
tPLH
tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
5 k
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO
50
, tr
1.5 ns, tf
2.6 ns.
G. The outputs are measured one at a time with one input transition per measurement.
S1
S2
tPHZ
tPLZ
tPZL
tPZH
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
Waveform 1
(see Notes C
and D)
Waveform 2
(see Notes C
and D)
1.5 V
VOH 0.5 V
VOL + 0.5 V
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
tw
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
VOL
VOH
Figure 1. Load Circuits and Voltage Waveforms
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