Document Outline
- IMPORTANT NOTICE
- Contents
- List of Illustrations
- List of Tables
- Introduction
- Features
- Functional Block Diagram
- Terminal Assignments
- Ordering Information
- Terminal Functions
- Architecture Overview
- Clock and Serial Data Interface
- Normal-Speed, Double-Speed, and Quad-Speed Selection
- Clock Master/Slave Mode (M_S)
- Clock Master Mode
- Clock Slave Mode
- PLL Filter
- DCLK
- Serial Data Interface
- I2S Timing
- Left-Justified Timing
- Right-Justified Timing
- DSP Mode Timing
- Reset, Power Down, and Status
- Signal Processing
- Volume Control
- Mute
- Auto Mute
- Individual Channel Mute
- De-Emphasis Filter
- Pulse Width Modulator (PWM)
- Clipping Indicator
- Error Recovery
- Individual Channel Error Recovery
- PWM DC-Offset Correction
- Interchannel Delay
- ABD Delay
- PWM/H-Bridge and Discrete H-Bridge Driver Interface
- I2C Serial Control Interface
- Single Byte Write
- Multiple Byte Write
- Single Byte Read
- Multiple Byte Read
- Serial Control Interface Register Definitions
- General Status Register (x00)
- Error Status Register (x01)
- System Control Register 0 (x02)
- System Control Register 1 (x03)
- Error Recovery Register (x04)
- Automute Delay Register (x05)
- DC-Offset Control Registers (x06x0B)
- Interchannel Delay Registers (x0Cx11)
- ABD Delay Register (x12)
- Individual Channel Mute Register (x19)
- System Procedures for Initialization, Changing Data Rates, and Switching\
\
Between Master and Slave Modes
- System Initialization
- Data Sample Rate
- Changing Between Master and Slave Modes
- Specifications
- Absolute Maximum Ratings Over Operating Temperature Ranges (Unless
Ot\
\
herwise Noted)
- Recommended Operating Conditions (Fs = 48 kHz)
- Electrical Characteristics Over Recommended Operating Conditions (Unles\
\
s Otherwise Noted)
- Static Digital Specifications Over Recommended Operating Conditions (Un\
\
less Otherwise Noted)
- Digital Interpolation Filter and PWM Modulator Over Recommended Operatin\
\
g Conditions (Unless Otherwise Noted) Fs = 48 kHz
- TAS5036B/TAS5182 System Performance Measured at the Speaker Terminals Ov\
\
er Recommended Operating Conditions (Unless Otherwise Noted) Fs = \
48 k\
Hz
- Switching Characteristics
- Command Sequence Timing
- Serial Audio Port
- Serial Audio Ports Slave Mode Over Recommended Operating Conditions (Un\
\
less Otherwise Noted)
- Serial Audio Ports Master Mode, Load Conditions 50 pF Over Recommended O\
\
perating Conditions (Unless Otherwise Noted)
- DSP Serial Interface Mode Over Recommended Operating Conditions (Unless\
\
Otherwise Noted)
- Serial Control PortI
- Serial Control PortI2C Operation
- Timing Characteristics for I 2 C Interface Signals Over Recommended Oper\
\
ating
Conditions (Unless Otherwise Noted)
- Application Information
- Serial Audio Interface Clock Master and Slave Interface Configuration
- Slave Configuration
- Master Configuration
- Mechanical Data
- PFC (S-PQFP-G80) PLASTIC QUAD FLATPACK
- Appendix AVolume Table
TAS5036B
Six Channel Digital Audio PWM Processor
February 2003
DAV Digital Audio/Speaker
Data Manual
SLES073
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding thirdparty products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
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Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright
2003, Texas Instruments Incorporated
Contents
iii
February 2003
SLES073
Contents
Section
Page
1
Introduction
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
Features
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Functional Block Diagram
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Terminal Assignments
3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Ordering Information
4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5
Terminal Functions
4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Architecture Overview
6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Clock and Serial Data Interface
6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1
Normal-Speed, Double-Speed, and Quad-Speed Selection
6
. . . . . . . . . . . . . . . . . . .
2.1.2
Clock Master/Slave Mode (M_S)
7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3
Clock Master Mode
7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4
Clock Slave Mode
8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.5
PLL Filter
10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.6
DCLK
10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.7
Serial Data Interface
10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Reset, Power Down, and Status
15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1
Reset--RESET
15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2
Power Down--PDN
16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3
General Status Registers
16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Signal Processing
18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1
Volume Control
18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2
Mute
19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3
Auto Mute
19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.4
Individual Channel Mute
19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.5
De-Emphasis Filter
19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Pulse Width Modulator (PWM)
20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1
Clipping Indicator
20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.2
Error Recovery
20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.3
Individual Channel Error Recovery
21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.4
PWM DC-Offset Correction
21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.5
Interchannel Delay
21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.6
ABD Delay
21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.7
PWM/H-Bridge and Discrete H-Bridge Driver Interface
22
. . . . . . . . . . . . . . . . . . . . . . .
2.5
I
2
C Serial Control Interface
22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1
Single Byte Write
23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.2
Multiple Byte Write
23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.3
Single Byte Read
24
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.4
Multiple Byte Read
24
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Serial Control Interface Register Definitions
25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
General Status Register (x00)
26
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Error Status Register (x01)
26
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
System Control Register 0 (x02)
26
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
System Control Register 1 (x03)
27
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5
Error Recovery Register (x04)
27
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
Automute Delay Register (x05)
28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7
DC-Offset Control Registers (x06x0B)
28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Illustrations
iv
February 2003
SLES073
3.8
Interchannel Delay Registers (x0Cx11)
28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9
ABD Delay Register (x12)
28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10
Individual Channel Mute Register (x19)
29
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 System Procedures for Initialization, Changing Data Rates, and Switching Between Master
and Slave Modes 30
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
System Initialization
30
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
Data Sample Rate
31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
Changing Between Master and Slave Modes
34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Specifications
36
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
Absolute Maximum Ratings Over Operating Temperature Ranges
36
. . . . . . . . . . . . . . . . . . . . . . .
5.2
Recommended Operating Conditions (Fs = 48 kHz)
36
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
Electrical Characteristics Over Recommended Operating Conditions
36
. . . . . . . . . . . . . . . . . . . .
5.3.1
Static Digital Specifications Over Recommended Operating Conditions
36
. . . . . . . . .
5.3.2 Digital Interpolation Filter and PWM Modulator Over Recommended Operating
Conditions Fs = 48 kHz 36
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3 TAS5036B/TAS5182 System Performance Measured at the Speaker Terminals
Over Recommended Operating Conditions 37
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4
Switching Characteristics
37
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1
Command Sequence Timing
37
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.2
Serial Audio Port
41
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.3
Serial Control Port--I
2
C Operation
44
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Application Information
45
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
Serial Audio Interface Clock Master and Slave Interface Configuration
46
. . . . . . . . . . . . . . . . . . .
6.1.1
Slave Configuration
46
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.2
Master Configuration
46
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Mechanical Data
47
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix A--Volume Table
49
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Illustrations
Figure
Title
Page
21 Crystal Circuit
8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22 External PLL Loop Filter
10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23 I2S 64-Fs Format
11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24 I2S 48-Fs Format
12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25 Left-Justified 64-Fs Format
12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26 Left-Justified 48-Fs Format
13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27 Right-Justified 64-Fs Format
13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28 Right-Justified 48-Fs Format
14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29 DSP Format
14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
210 Attenuation Curve
18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
211 De-Emphasis Filter Characteristics
20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
212 PWM Outputs and H-Bridge Driven in BTL Configuration
22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
213 Typical I
2
C Sequence
23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
214 Single Byte Write Transfer
23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
215 Multiple Byte Write Transfer
24
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
216 Single Byte Read
24
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables
v
February 2003
SLES073
217 Multiple Byte Read
24
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41 RESET During System Initialization
30
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42 Extending the I
2
C Write Interval Following a Low-to-High Transition of the RESET Terminal
31
. . . . . . .
43 Changing the Data Sample Rate Using the DBSPD Terminal
32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44 Changing the Data Sample Rate Using the I
2
C
32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45 Changing the Data Sample Rate With An Unstable MCLK_IN Using the DBSPD Terminal
33
. . . . . . . .
46 Changing the Data Sample Rate With An Unstable MCLK_IN Using the I
2
C
34
. . . . . . . . . . . . . . . . . . . .
47 Changing Between Master and Slave Clock Mode
35
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51 RESET Timing
37
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52 Power-Down and Power-Up Timing--RESET Preceding PDN
38
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53 Power-Down and Power-Up Timing--RESET Following PDN
39
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54 Error Recovery Timing
40
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55 Mute Timing
40
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56 Right-Justified, IIS, Left-Justified Serial Protocol Timing
41
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57 Right, Left, and IIS Serial Mode Timing Requirement
42
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58 Serial Audio Ports Master Mode Timing
42
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59 DSP Serial Port Timing
42
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
510 DSP Serial Port Expanded Timing
43
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
511 DSP Absolute Timing
43
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
512 SCL and SDA Timing
44
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
513 Start and Stop Conditions Timing
44
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61 Typical TAS5036B Application
45
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62 TAS5036B Serial Audio Port--Slave Mode Connection Diagram
46
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63 TAS5036B Serial Audio Port--Master Mode Connection Diagram
46
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables
Table
Title
Page
21 Normal-Speed, Double-Speed, and Quad-Speed Operation
7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22 Master and Slave Clock Modes
9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23 LRCLK, MCLK_IN, and External PLL Rates
9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24 DCLK
10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25 Supported Word Lengths
11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26 Device Outputs During Reset
15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27 Values Set During Reset
15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28 Device Outputs During Power Down
16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29 Volume Register
19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
210 De-Emphasis Filter Characteristics
19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
211 Device Outputs During Error Recovery
21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31 I
2
C Register Map
25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32 General Status Register (Read Only)
26
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33 Error Status Register
26
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34 System Control Register 0
26
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35 System Control Register 1
27
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36 Error Recovery Register
27
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables
vi
February 2003
SLES073
37 Automute Delay Register
28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38 DC-Offset Control Registers
28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39 Six Interchannel Delay Registers
28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
310 ABD Delay Register
28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
311 Individual Channel Mute Register
29
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction
1
SLES073--February 2003
TAS5036B
1
Introduction
The TAS5036B is an innovative, cost-effective, high-performance 24-bit six-channel digital pulse width
modulator (PWM) based on Equibit
technology. Combined with a TI digital amplifier power stage, these
devices use noise-shaping and sophisticated error correction algorithms to achieve high power efficiency and
high-performance digital audio reproduction. The TAS5036B is designed to drive up to six digital power
devices to provide six channels of digital audio amplification. The digital power devices can be six conventional
monolithic power stages (such as the TAS5110) or six discrete differential power stages using gate drivers
and MOSFETs.
The TAS5036B has six independent volume controls and mute. The device operates in AD and BD modes.
This all-digital audio system contains only two analog components in the signal chain--an LC low-pass filter
at each speaker terminal and can provide up to 96-dB SNR at the speaker terminals. The TAS5036B has a
wide variety of serial input options including right justified (16, 20, or 24 bit), I2S (16, 20, or 24 bit) left justified,
or DSP (16 bit) data formats. The device is fully compatible with AES standard sampling rates of 44.1 kHz,
48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz including de-emphasis for 44.1-kHz and 48-kHz sample
rates. The TAS5036B plus the TAS51xx power stage device combination was designed for home theater
applications such as DVD minicomponent systems, home theater in a box (HTIB), DVD receiver, A/V receiver,
or TV sets.
1.1
Features
True Digital Audio Amplifier
High Quality Audio
100-dB SNR
<0.005% THD+N
Six-Channel Volume Control
Patented Soft Volume
Patented Soft Mute
16-, 20-, or 24-Bit Input Data
Sampling Rates: 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz
Supports Master and Slave Modes
3.3-V Power Supply Operation
Economical 80-Pin TQFP Package
De-Emphasis: 32 kHz, 44.1 kHz, and 48 kHz
Clock Oscillator Circuit for Master Modes
Low Jitter Internal PLL
Soft Volume and Mute Update
Equibit is a trademark of Texas Instruments.
Introduction
2
SLES073--February 2003
TAS5036B
1.2
Functional Block Diagram
PWM Ch.
Output Control
A
VDD_PLL
A
VSS_PLL
VREGA_CAP
VREGB_CAP
VREGC_CAP
DVDD_RCL
DVSS_RCL
DVDD_PWM
DVSS_PWM
Power Supply
PLL_FLT_OUT
PLL_FLT_RET
SCLK
LRCLK
MCLKOUT
SDIN1
SDIN2
SDIN3
MCLK_IN
XTAL_OUT
XTAL_IN
DBSPD
SDA
SCL
CSO
PWM_AP_1
VALID_1
PWM_AP_2
VALID_2
PWM AP_3
VALID_3
PWM_AP_4
VALID_4
PWM_AP_5
VALID_5
PWM_AP_6
VALID_6
PWM AM_3
PWM_AM_1
PWM_AM_2
PWM_AM_4
PWM_AM_5
PWM_AM_6
Clock,
PLL
and
Serial
Data
I/F
PDN
RESET
MUTE
CLIP
ERR_RCVY
Serial
Control
I/F
Reset,
Pwr Dwn
and
Status
Auto Mute
De-emphasis
Soft Volume
Error Recovery
Soft Mute
Clip Detect
Signal
Processing
PWM
Section
PWM Ch.
PWM Ch.
PWM Ch.
PWM Ch.
PWM Ch.
M_S
DM_SEL1
DM_SEL2
Introduction
3
SLES073--February 2003
TAS5036B
1.3
Terminal Assignments
22 23
VREGP_CAP
DVDD_RCL
DVSS_RCL
DVDD_PWM
DVSS_PWM
PWM_AP_4
PWM_AM_4
VALID_4
PWM_BM_4
PWM_BP_4
PWM_AP_5
PWM_AM_5
VALID_5
PWM_BM_5
PWM_BP_5
PWM_AP_6
PWM_AM_6
VALID_6
PWM_BM_6
PWM_BP_6
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NC
NC
MCLK_IN
AVDD_PLL
PLL_FLT_OUT
PLL_FLT_RET
AVSS_PLL
NC
VREGA_CAP
DVSS1
NC
RESET
ERR_RCVRY
MUTE
PDN
SDA
SCL
CS0
NC
NC
25 26 27 28
PFC PACKAGE
(TOP VIEW)
79 78 77 76 75
80
74
72 71 70
73
29 30 31 32 33
69 68
21
67 66 65 64
34 35 36 37 38 39 40
63 62 61
NC No internal connection
A
VDD_OSC
XTL_IN
XTL_OUT
A
VSS_OSC
DVSS
PWM_AP1
PWM_AM_1
V
ALID_1
PWM_BM_1
PWM_BP_1
PWM_AP_2
PWM_AM_2
V
ALID_2
PWM_BM_2
PWM_BP_2
PWM_AP_3
PWM_AM_3
V
ALID_3
PWM_BM_3
PWM_BP_3
NC
NC
NC
DBSPD
CLIP
SDIN1
SDIN2
SDIN3
MCLK_OUT
SCLK
LRCLK
DVDD
DVSS
VREGC_CAP
DEM_SEL2
DEM_SEL1
M_S
DVSS1
DVSS1
NC
Introduction
4
SLES073--February 2003
TAS5036B
1.4
Ordering Information
Texas Instruments
T
AS
Audio Solutions
5036B
PFC
Device Number
Package Type
AVAILABLE OPTIONS
PACKAGE
TA
PLASTIC 80-PIN TQFP
(PFC)
0
C to 70
C
TAS5036BPFC
1.5
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AVDD_OSC
80
P
Analog power supply for internal oscillator cells
AVDD_PLL
4
P
Analog power supply for PLL
AVSS_OSC
77
AO
Analog ground for internal oscillator cells
AVSS_PLL
7
P
Analog ground for PLL
CLIP
25
DO
Digital clipping indicator, active low
CS0
18
DI
I2C serial control chip address select input, active high
DBSPD
24
DI
Sample rate is double speed (88.2 kHz or 96 kHz), active high
DM_SEL1
36
DI
De-emphasis select bit 2, 10 = 48 kHz, 11= undefined (none)
DM_SEL2
35
DI
De-emphasis select bit 1 (0 = none, 01 = 32 kHz, 10 = 44.1 kHz
DVDD
32
P
Digital power supply
DVDD_PWM
57
P
Digital power supply for PWM
DVDD_RCL
59
P
Digital power supply for reclocker
DVSS
33, 76
P
Digital ground for digital core and most of I/O buffers
DVSS1
10, 38, 39
DIO
Digital ground for digital core and most of I/O buffers
DVSS_PWM
56
P
Digital ground for PWM
DVSS_RCL
58
P
Digital ground for reclocker
ERR_RCVRY
13
DI
Error recovery input, active low
LRCLK
31
DIO
Serial audio data left / right clock (sampling rate clock) (input when M_S = 0; output when M_S = 1)
M_S
37
DI
Master/slave mode input signal (master = 1, slave = 0)
MCLK_IN
3
DI
MCLK input, slave mode (or master / double-speed mode)
MCLK_OUT
29
DO
MCLK output buffered system clock output if M_S = 1; otherwise set to 0
MUTE
14
DI
Mute input signal, active low (muted signal = 0, normal mode = 1)
N/C
1, 2, 8, 11,
1923, 40
Not connected
PDN
15
DI
Power down, active low
PLL_FLT_OUT
5
AO
PLL external filter
PLL_FLT_RET
6
AO
PLL external filter (internally connected to AVSS_PLL)
PWM_AM_1
74
DO
PWM 1 output (differential -); {positive H-bridge side}
Introduction
5
SLES073--February 2003
TAS5036B
TERMINAL
DESCRIPTION
I/O
NAME
DESCRIPTION
I/O
NO.
PWM_AM_2
69
DO
PWM 2 output (differential -); {positive H-bridge side}
PWM_AM_3
64
DO
PWM 3 output (differential -); {positive H-bridge side}
PWM_AM_4
54
DO
PWM 4 output (differential -); {positive H-bridge side}
PWM_AM_5
49
DO
PWM 5 output (differential -); {positive H-bridge side}
PWM_AM_6
44
DO
PWM 6 output (differential -); {positive H-bridge side}
PWM_AP_1
75
DO
PWM 1 output (differential +); {positive H-bridge side}
PWM_AP_2
70
DO
PWM 2 output (differential +); {positive H-bridge side}
PWM_AP_3
65
DO
PWM 3 output (differential +); {positive H-bridge side}
PWM_AP_4
55
DO
PWM 4 output (differential +); {positive H-bridge side}
PWM_AP_5
50
DO
PWM 5 output (differential +); {positive H-bridge side}
PWM_AP_6
45
DO
PWM 6 output (differential +); {positive H-bridge side}
PWM_BM_1
72
DO
PWM 1 output (differential -); {negative H-bridge side}
PWM_BM_2
67
DO
PWM 2 output (differential -); {negative H-bridge side}
PWM_BM_3
62
DO
PWM 3 output (differential -); {negative H-bridge side}
PWM_BM_4
52
DO
PWM 4 output (differential -); {negative H-bridge side}
PWM_BM_5
47
DO
PWM 5 output (differential -); {negative H-bridge side}
PWM_BM_6
42
DO
PWM 6 output (differential -); {negative H-bridge side}
PWM_BP_1
71
DO
PWM 1 output (differential +); {negative H-bridge side}
PWM_BP_2
66
DO
PWM 2 output (differential +); {negative H-bridge side}
PWM_BP_3
61
DO
PWM 3 output (differential +); {negative H-bridge side}
PWM_BP_4
51
DO
PWM 4 output (differential +); {negative H-bridge side}
PWM_BP_5
46
DO
PWM 5 output (differential +); {negative H-bridge side}
PWM_BP_6
41
DO
PWM 6 output (differential +); {negative H-bridge side}
RESET
12
DI
System reset input, active low
SCL
17
DI
I2C serial control clock input
SCLK
30
DIO
Serial audio data clock (shift clock)
SDA
16
DIO
I2C serial control data input/ output
SDIN1
26
DI
Serial audio data 1 input
SDIN2
27
DI
Serial audio data 2 input
SDIN3
28
DI
Serial audio data 3 input
VALID_1
73
DO
Output indicating validity of PWM outputs, channel 1, active high
VALID_2
68
DO
Output indicating validity of PWM outputs, channel 2, active high
VALID_3
63
DO
Output indicating validity of PWM outputs, channel 3, active high
VALID_4
53
DO
Output indicating validity of PWM outputs, channel 4, active high
VALID_5
48
DO
Output indicating validity of PWM outputs, channel 5, active high
VALID_6
43
DO
Output indicating validity of PWM outputs, channel 6, active high
VREGA_CAP
9
P
Voltage regulator capacitor
VREGB_CAP
60
P
Voltage regulator capacitor
VREGC_CAP
34
P
Voltage regulator capacitor
XTL_IN
79
AI
Crystal or TTL level clock input
XTL_OUT
78
AO
Crystal output (not for external usage)
Architecture Overview
6
SLES073--February 2003
TAS5036B
2
Architecture Overview
The TAS5036B is composed of six functional elements:
Clock, PLL, and serial data interface (IIS)
Reset/power-down circuitry
Serial control interface (IIC)
Signal processing unit
Pulse width modulator (PWM)
Power supply
2.1
Clock and Serial Data Interface
The TAS5036B clock and serial data interface contain an input serial data slave and the clock master/ slave
interface. The serial data slave interface receives information from a digital source such as a DSP, S/PDIF
receiver, analog-to-digital converter (ADC), digital audio processor (DAP), or other serial bus master. The
serial data interface has three serial data inputs that can accept up to six channels of data at data sample rates
of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. The serial data interfaces support
left justified and right justified for 16-, 20-, and 24-bits. In addition, the serial data interface supports the DSP
protocol for 16 bits and the I2S protocol for 24 bits.
The TAS5036B can function as a receiver or a generator for the MCLK_IN (master clock), SCLK (shift clock),
and LRCLK (left/right clock) signals that control the flow of data on the three serial data interfaces. The
TAS5036B is a clock master when it generates these clocks and is a clock slave when it receives these clocks.
The TAS5036B is a synchronous design that relies upon the master clock to provide a reference clock for all
of the device operations and communication via the I
2
C. When operating as a slave, this reference clock is
MCLK_IN. When operating as a master, the reference clock is either a TTL clock input to XTAL_IN or a crystal
attached across XTAL_IN and XTAL_OUT.
The clock and serial data interface has two control parameters: data sample rate and clock master or slave.
2.1.1 Normal-Speed, Double-Speed, and Quad-Speed Selection
The data sample rate is selected through a terminal (DBSPD) or the serial control register 0 (X02). The data
sample rate control sets the frequencies of the SCLK and LRCLK in clock slave mode and the output
frequencies of SCLK and LRCLK in clock master mode. There are three data rates: normal speed, double
speed, and quad speed.
Normal-speed mode supports data rates of 32 kHz, 44.1 kHz, and 48 kHz. Normal speed is supported in the
master and slave modes. Double-speed mode is used to support sampling rates of 88.2 kHz and 96 kHz.
Double speed is supported in master and slave modes. Quad-speed mode is used to support sampling rates
of 176.4 kHz and 192 kHz.
The PWM is placed in normal speed by setting the DBSPD terminal low or by setting the normal mode bits
in the system control register 0 (x02) through the serial control interface. The PWM is placed in double speed
mode by setting the DBSPD terminal high or by setting the double speed bits in the system control register.
Quad-speed mode is auto detected supported in slave mode and invoked using the I
2
C serial control interface
in master mode. In slave mode, if the TAS5036B is not in double speed mode, quad-speed mode is
automatically detected when MCLK_IN is 128Fs. In master mode, the PWM is placed in quad-speed mode
by setting the quad-speed bit in the system control register through the serial control interface.
If the master clock is well behaved during the frequency transition (the high or low clock periods are not less
than 20 ns) then a simple speed selection is simply performed by setting the DBSPD terminal or the serial
control register.
When the sample rate is changed, the TAS5036B temporarily suspends processing, places the PWM outputs
in a hard mute (PWM P outputs low; PWM M outputs high and all VALID signals low), resets all internal
processes, and suspends all I
2
C operations. The TAS5036B then performs a partial re-initialization and
noiselessly restarts the PWM output. The TAS5036B preserves all control register settings throughout this
sequence. If desired, the sample rate change can be performed while mute is active to provide a completely
silent transition. The timing of this control sequence is shown in Section 4.
Architecture Overview
7
SLES073--February 2003
TAS5036B
If the master clock input can encounter high clock or low clock period of less than 20 ns while the data rates
are changing, then RESET should be applied during this time There are two recommended control procedures
for this case, depending upon whether the DBSPD terminal or the serial control interface is used. These
control sequences are shown in Section 4.
Table 21. Normal-Speed, Double-Speed, and Quad-Speed Operation
QUAD-SPEED CONTROL
REGISTER BIT
DBSPD TERMINAL OR
CONTROL REGISTER BIT
MODE
SPEED SELECTION
0
0
Master or slave
Normal speed
0
1
Master or slave
Double speed
1
0
Master or slave
Quad speed
0
0
Slave
Quad speed if MCLK_IN = 128Fs
1
1
Master or slave
Error
2.1.2 Clock Master/Slave Mode (M_S)
Clock master and slave mode can be invoked using the M_S (master slave) terminal.
This terminal specifies the default mode that is set immediately following a device RESET. The serial data
interface setting permits the clock generation mode to be changed during normal operation.
The transition to master mode occurs:
Following a RESET when M_S terminal has a logic high applied
The transition to slave mode occurs:
Following a RESET when M_S terminal has a logic low applied
2.1.3 Clock Master Mode
When M_S = 1 following a RESET, the TAS5036B provides the master clock, SCLK, and LRCLK to the rest
of the system. In the master mode, the TAS5036B outputs the audio system clocks MCLK_OUT, SCLK, and
LRCLK.
The TAS5036B device generates these clocks plus its internal clocks from the internal phase-locked loop
(PLL). The reference clock for the PLL can be provided by either an external clock source (attached to
XTAL_IN) or a crystal (connected across terminals XTAL_IN and XTAL_OUT). The external source attached
to MCLK_IN is 256 times (128 in quad mode) the data sample rate (Fs). The SCLK frequency is 64 times the
data sample rate and the SCLK frequency of 48 times the data sample rate is not supported in the master
mode. The LRCLK frequency is the data sample rate.
Architecture Overview
8
SLES073--February 2003
TAS5036B
2.1.3.1
Crystal Type and Circuit
In clock master mode the TAS5036B can derive the MCLKOUT, SCLK, and LRCLK from a crystal. In this case,
the TAS5036B uses a parallel-mode fundamental-mode crystal. This crystal is connected to the TAS5036B
as shown in Figure 21.
XO
TAS5036B
OSC
MACRO
rd
C1
XI
C2
AVSS
rd = Drive level control resistor crystal vendor specified
CL = Crystal load capacitance (capacitance of circuitry between the two terminals of the crystal)
CL = (C1 x C2 )/(C1 + C2 ) + CS (where CS = board stray capacitance ~ 3 pF)
Example: Vendor recommended CL = 18 pF, CS = 3 pF
C1 = C2 = 2 x (183) = 30 pF
Figure 21. Crystal Circuit
2.1.4 Clock Slave Mode
In the slave mode (M_S = 0), the master clock, LRCLK, and SCLK are inputs to the TAS5036B. The master
clock is supplied through the MCLK_IN terminal.
As in the master mode, the TAS5036B device develops its internal timing from the internal phase-locked loop
(PLL). The reference clock for the PLL is provided by the input to the MCLK_IN terminal. This input is at a
frequency of 256 times (128 in quad mode) the input data rate. The SCLK frequency is 48 or 64 times the data
sample rate. The LRCLK frequency is the data sample rate. The TAS5036B does not require any specific
phase relationship between SRCLK and MCLK_IN, but there must be synchronization. The TAS5036B
monitors the relationship between MCLK, SCLK, and LRCLK. The TAS5036B detects if any of the three clocks
are absent, if the LRCLK rate changes more than 10 MCLK cycles since the last device reset or clock error,
or if the MCLK frequency is changing substantially with respect to the PLL frequency.
When a clock error is detected, the TAS5036B performs a clock error management sequence.
The clock error management sequence temporarily suspends processing, places the PWM outputs in a hard
mute (PWM_P outputs are low; PWM_M outputs are high, and all VALID signals are low), resets all internal
processes, sets the volumes to mute, and suspends all I
2
C operations.
When the error condition is corrected, the TAS5036B exits the clock error sequence by performing a partial
re-initialization, noiselessly restarting the PWM output, and ramping the volume up to the level specified in
the volume control registers. This sequence is performed over a 60 ms. interval. The TAS5036B preserves
all control register settings that were set prior to the clock interruption.
If a clock error occurs while the ERR_RCVRY terminal is asserted (low), the TAS5036B performs the error
management sequence up to the unmute sequence. In this case, the volume remains at full attenuation with
the PWM output at a 50% duty cycle. The volume can be restored from this latched mute state by triggering
a mute/unmute sequence by asserting and releasing MUTE either by using the terminal, the system control
register X01 D4, or the individual channel mute register D5D0.
Architecture Overview
9
SLES073--February 2003
TAS5036B
Alternatively, the TAS5036B can be prevented from entering the latched mute state following a clock error
when the ERR_RCVRY terminal or the error recovery I
2
C command (register X03 bit D2) is active by writing
x7F to the individual error recovery register (x04) and a x84 to x1F (a feature enable register).
Table 22. Master and Slave Clock Modes
DESCRIPTION
M_S
DBSPD
XTL_IN
(MHz)
MCLK_IN
(MHz)
SCLK
(MHz)
LRCLK
(kHz)
MCLK_OUT
(MHz)#
Internal PLL, master, normal speed
1
0
8.192
-
2.048
32
8.192
Internal PLL, master, normal speed
1
0
11.2896
-
2.8224
44.1
11.2896
Internal PLL, master, normal speed
1
0
12.288
-
3.072
48
12.288
Internal PLL, master, double speed
1
1
-
22.5792
5.6448
88.2
22.5792
Internal PLL, master, double speed
1
1
-
24.576
6.144
96
24.576
Internal PLL, master, quad speed
1
0
-
22.5792
11.2896
176.4
22.5792
Internal PLL, master, quad speed
1
0
-
24.576
12.288
192
24.576
Internal PLL, slave, normal speed
0
0
-
8.192
2.0484
32
Digital GND
Internal PLL, slave, normal speed
0
0
-
11.2896
2.8224
44.1
Digital GND
Internal PLL, slave, normal speed
0
0
-
12.288
3.072
48
Digital GND
Internal PLL, slave, double speed
0
1
-
22.5792
5.6448
88.2
Digital GND
Internal PLL, slave, double speed
0
1
-
24.576
6.144
96
Digital GND
Internal PLL, slave, quad speed ||
0
0
-
22.5792
11.2896
176
Digital GND
Internal PLL, slave, quad speed ||
0
0
-
24.576
12.288
192
Digital GND
External PLL, master, normal speed
1
0
-
-
2.048
32
8.192
External PLL, master, normal speed
1
0
-
-
2.8224
44.1
11.2896
External PLL, master, normal speed
1
0
-
-
3.072
48
12.288
External PLL, master, double speed
1
1
-
-
5.6448
88.2
22.5792
External PLL, master, double speed
1
1
-
-
6.144
96
24.576
External PLL, master, quad speed
1
0
-
-
11.2896
176.4
22.5792
External PLL, master, quad speed
1
0
-
-
12.288
192
24.576
External PLL, slave, normal speed
0
0
-
8.192
2.0484
32
Digital GND
External PLL, slave, normal speed
0
0
-
11.2896
2.8224
44.1
Digital GND
External PLL, slave, normal speed
0
0
-
12.288
3.072
48
Digital GND
External PLL, slave, double speed
0
1
-
22.5792
5.6448
88.2
Digital GND
External PLL, slave, double speed
0
1
-
24.576
6.144
96
Digital GND
External PLL, slave, quad speed ||
0
0
-
22.5792
11.2896
176
Digital GND
External PLL, slave, quad speed ||
0
0
-
24.576
12.288
192
Digital GND
A crystal oscillator is connected to XTL_IN.
MCLK_IN tied low when input to XTL_IN is provided; XTL_IN tied low when MCLK_IN_IN is provided.
External MCLK_IN connected to MCLK_IN_IN input
SCLK and LRCLK are outputs when M_S=1, and inputs when M_S=0.
# MCLK_OUT is driven low when M_S=0.
|| Quad-speed mode is detected automatically.
k
SCLK can be 48 or 64 times Fs
Table 23. LRCLK, MCLK_IN, and External PLL Rates
NORMAL SPEED (kHz)
DOUBLE SPEED (kHz)
QUAD SPEED (kHz)
LRCLK
1FS
32
44.1
48
1FS
64
88.2
96
1FS
176.4
192
MCLK_IN
256FS
8,192
11,289.6
12,288
256FS
16,384
22,579.2
24,576
128FS
22,579.2
24,576
EXT. PLL
2048FS
65,536
90,316.8
98,304
1024FS
65,536
90,316.8
98,304
512FS
90,316.8
98,304
Architecture Overview
10
SLES073--February 2003
TAS5036B
2.1.5 PLL Filter
A low jitter PLL produces the internal timing of the TAS5036B (when in master mode), the master clock, SCLK,
and LRCLK. Connections for the PLL external loop filter are provided through PLL_FLT_OUT and
PLL_FLT_RET as shown in Figure 22.
PLL_FLT_OUT
TAS5036B
PLL_FLT_RET
220
47 nF
4.7 nF
Figure 22. External PLL Loop Filter
2.1.6 DCLK
DCLK is the internal high frequency clock that is produced by the PLL circuitry from MCLK. The TAS5036B
uses the DCLK to control all internal operations. DCLK is 8 times the speed of MCLK in normal speed mode,
4 times MCLK in double speed, and 2 times MCLK in quad speed. With respect to the I
2
C addressable
registers, DCLK clock cycles are used to specify interchannel delay and to detect when the MCLK frequency
is drifting. Table 24 DCLK shows the relationship between Sample Rate, MCLK, and DCLK.
Table 24. DCLK
FS
(kHz)
MCLK
(MHz)
DCLK
(MHz)
DCK Period
(ns)
32
8.1920
65.5360
15.3
44.1
11.2896
90.3168
11.1
48
12.2880
98.3040
10.2
88
22.5280
90.1120
11.1
96
24.5760
98.3040
10.2
192
49.1520
98.3040
10.2
2.1.7 Serial Data Interface
The TAS5036B operates as a slave only/receive only serial data interface in all modes. The TAS5036B has
three PCM serial data interfaces to accept six channels of digital data though the SDIN1, SDIN2, SDIN3 inputs.
The serial audio data is in MSB first; 2s complement format.
The serial data interfaces of the TAS5036B can be configured in right justified, I
2
S, left-justified, or DSP modes.
This interface supports 32-kHz, 44.1-kHz, 48-kHz, 88-kHz, 96-kHz, 176.4-kHz, and 192-kHz data sample
rates. The serial data interface format is specified using the data interface control register. The supported word
lengths are shown in Table 25.
During normal operating conditions if the serial data interface settings change state, an error recovery
sequence is initiated.
Architecture Overview
11
SLES073--February 2003
TAS5036B
Table 25. Supported Word Lengths
DATA MODES
WORD
LENGTHS
MOD2
MOD1
MOD0
Right justified, MSB first
16
0
0
0
Right justified, MSB first
20
0
0
1
Right justified, MSB first
24
0
1
0
I2S
16
0
1
1
I2S
20
1
0
0
I2S
24
1
0
1
Left justified, MSB first
24
1
1
0
DSP frame
16
1
1
1
2.1.7.1
I
2
S Timing
I
2
S timing uses an LRCLK to define when the data being transmitted is for the left channel or the right channel.
The LRCLK is low for the left channel and high for the right channel. A bit clock running at 48 or 64 times Fs
is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state
to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of the bit
clock. The TAS5036B masks unused trailing data bit positions. Master mode only supports a 64 times Fs bit
clock.
23
22
SCLK
32 Clks
LRCLK (Note Reversed Phase)
Left Channel
24-Bit Mode
9
8
5
4
1
0
19
18
20-Bit Mode
5
4
1
0
16-Bit Mode
1
0
15
14
MSB
LSB
23
22
SCLK
32 Clks
Right Channel
9
8
5
4
1
0
19
18
5
4
1
0
1
0
15
14
MSB
LSB
2-Channel I2S (Philips Format) Stereo Input
Figure 23. I
2
S 64-Fs Format
Architecture Overview
12
SLES073--February 2003
TAS5036B
2-Channel I2S Stereo Input/Output (24-Bit Transfer Word Size)
23
22
SCLK
24 Clks
LRCLK
Left Channel
24-Bit Mode
20
19
8
7
2
1
19
18
20-Bit Mode
16
15
1
0
16-Bit Mode
1
0
15
14
MSB
LSB
4
3
5
21
4
5
17
13
12
11
23
22
SCLK
24 Clks
Right Channel
20
19
8
7
2
1
19
18
16
15
1
0
1
0
15
14
MSB
LSB
4
3
5
21
4
5
17
13
12
11
0
Figure 24. I
2
S 48-Fs Format
2.1.7.2
Left-Justified Timing
Left-justified (LJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and
the right channel. The LRCLK is high for the left channel and low for the right channel. A bit clock running at
48 or 64 times Fs is used to clock in the data. The first bit of data appears on the data lines at the same time
the LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5036B
masks unused trailing data bit positions. Master mode only supports a 64 times Fs bit clock.
23
22
SCLK
32 Clks
LRCLK
Left Channel
24-Bit Mode
9
8
5
4
1
0
MSB
LSB
2-Channel Left-Justified Stereo Input
23
22
32 Clks
LRCLK
Right Channel
9
8
5
4
1
0
MSB
LSB
NOTE: All data presented in 2s complement form with MSB first.
Figure 25. Left-Justified 64-Fs Format
Architecture Overview
13
SLES073--February 2003
TAS5036B
22
21
SCLK
24 Clks
LRCLK
Left Channel
19
9
8
1
0
MSB
LSB
2-Channel Left-Justified Stereo Input/Output (24-Bit Transfer Word Size)
3
2
4
20
23
22
21
24 Clks
Right Channel
19
9
8
1
0
MSB
LSB
3
2
4
20
23
5
5
24-Bit Mode
Figure 26. Left-Justified 48-Fs Format
2.1.7.3
Right-Justified Timing
Right-justified (RJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and
the right channel. The LRCLK is high for the left channel and low for the right channel. A bit clock running at
48 or 64 times Fs is used to clock in the data. The first bit of data appears on the data 8-bit clock periods (for
24-bit data) after LRCLK toggles. In RJ mode, the last bit clock before LRCLK transitions always clocks the
LSB of data. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5036B masks
unused leading data bit positions. Master mode only supports a 64 times Fs bit clock.
23
22
SCLK
32 Clks
LRCLK
Left Channel
24-Bit Mode
19
18
15
14
1
0
19
18
20-Bit Mode
15
14
1
0
16-Bit Mode
1
0
15
14
MSB
LSB
2-Channel Right-Justified (Sony Format) Stereo Input
NOTE: All data presented in 2s complement form with MSB first.
23
22
32 Clks
Right Channel
19
18
15
14
1
0
19
18
15
14
1
0
1
0
15
14
MSB
LSB
Figure 27. Right-Justified 64-Fs Format
Architecture Overview
14
SLES073--February 2003
TAS5036B
22
21
SCLK
24 Clks
LRCLK
Left Channel
19
1
0
19
1
0
MSB
LSB
2-Channel Right-Justified Stereo Input/Output (24-Bit Transfer Word Size)
20
23
NOTE: All data presented in 2s complement form with MSB first.
1
0
8
9
15
14
18
18
8
9
8
9
15
14
15
14
22
21
24 Clks
Right Channel
19
1
0
19
1
0
MSB
LSB
20
23
1
0
8
9
15
14
18
18
8
9
8
9
15
14
15
14
24-Bit Mode
20-Bit Mode
16-Bit Mode
Figure 28. Right-Justified 48-Fs Format
2.1.7.4
DSP Mode Timing
DSP mode timing uses an LRCLK to define when data is to be transmitted for both channels. A bit clock running
at 64
Fs is used to clock in the data. The first bit of the left channel data appears on the data lines following
the LRCLK transition. The data is written MSB first and is valid on the rising edge of the bit clock. The
TAS5036B masks unused trailing data bit positions.
SCLK
LRCLK
64 SCLKS
LSB
MSB
16 Bits
Left
Channel
16 Bits
Right
Channel
32 Bits Unused
SDIN
LSB
MSB
Figure 29. DSP Format
Architecture Overview
15
SLES073--February 2003
TAS5036B
2.2
Reset, Power Down, and Status
The reset, power down, and status circuitry provides the necessary controls to bring the TAS5036B to the initial
inactive condition, achieve low power standby, and report system status.
2.2.1 Reset--RESET
The TAS5036B is placed in the reset mode by setting the RESET terminal low.
RESET is an asynchronous control signal that restores the TAS5036B to its default conditions, sets the valid
16 outputs low, and places the PWM in the hard mute state. Volume is immediately set to full attenuation
(there is no ramp down).
As long as the RESET terminal is held low, the device is in the reset state. During reset, all I
2
C and serial data
bus operations are ignored. Table 26 shows the device output signals while RESET is active.
Upon the release of RESET, if POWER_DWN is high, the system performs a 4-ms to 5-ms device initialization
and then ramps the volume up to 0 db using a soft volume update sequence. If MCLK_IN is not active when
RESET is released high, then a 4-ms to 5-ms initialization sequence is produced once MCLK_IN becomes
active.
During device initialization all controls are reset to their initial states. Table 27 shows the control settings that
are changed during initialization.
RESET should be applied during power-up initialization or while changing the master slave clock states.
Table 26. Device Outputs During Reset
SIGNAL
MODE
SIGNAL STATE
Valid 1Valid 6
All
Low
PWM P-outputs
All
Low
PWM M-outputs
All
Low
MCLKOUT
All
Low
SCLK
Master
Low
SCLK
Slave
Signal input
LRCLK
Master
Low
LRCLK
Slave
Signal input
SDA
All
Signal input
CLIP
All
High
Because the RESET is an asynchronous control signal, small clicks and pops can be produced during the
application (the leading edge) of this control. However, when RESET is released, the transition from the hard
mute state back to normal operation is performed synchronously using a quiet sequence.
If a completely quiet reset sequence is desired, MUTE should be applied before applying RESET.
Table 27. Values Set During Reset
CONTROL
SETTING
Volume
0 dB
MCLK_IN frequency
256
Master/slave mode
M_S terminal state
Automute
Enabled
De-emphasis
None
DC offset
0
Interchannel delay
Each channel is set to default value
Architecture Overview
16
SLES073--February 2003
TAS5036B
2.2.2 Power Down--PDN
The TAS5036B can be placed into the power-down mode by holding the PDN terminal low. When power-down
mode is entered, both the PLL and the oscillator are shut down. Volume is immediately set to full attenuation
(there is no ramp down). The valid 16 outputs are immediately asserted low and the PWM outputs are placed
in the hard mute state. PDN initiates device power down without clock inputs. As long as the PDN terminal
is held low--the device is in the power-down (hard mute) state.
During power down, all I
2
C and serial data bus operations are ignored. Table 28 shows the device output
signals while PDN is active.
Table 28. Device Outputs During Power Down
SIGNAL
MODE
SIGNAL STATE
Valid 1Valid 6
All
Low
PWM P-outputs
All
Low
PWM M-outputs
All
Low
MCLKOUT
All
Low
SCLK
Master
Low
SCLK
Slave
Signal input
LRCLK
Master
Low
LRCLK
Slave
Signal input
SDA
All
Signal input
CLIP
All
High
To place the device in total power-down mode, both RESET and power-down modes must be enabled. Prior
to bringing PDN high, RESET must be brought low for a minimum of 50 ns.
Because PDN is an asynchronous control signal, small clicks and pops can be produced during the application
(the leading edge) of this control. However, when PDN is released, the transition from the hard mute state back
to normal operation is performed synchronously using a quiet sequence.
If a completely quiet reset sequence is desired, MUTE should be applied before applying PDN.
2.2.3 General Status Register
The general status register is a read only register. This register provides an indication when a volume update
is in progress or one of the channels is inactive. The device id can be read using this register.
Volume update is in progress--Whenever a volume change is in progress due to a volume update
command or mute, this status bit is high.
Device identification code--The device identification code 1 0 0 1 1 is displayed.
No internal errors (all valid signals are high)--When there are no internal errors in the TAS5036B and all
outputs are valid, this status bit is high.
One or more valid signals are inactive--If low, one or more channels of the TAS5036B are not outputting
data. The valid signals for those channels are inactive.
This can be produced by one of three causes:
One or more of the clock signals are in error
ERROR recover is active (low)
The automute has silenced one or more channels that are receiving 0 inputs
MUTE has been set
Volume control has been set to full attenuation
If this signal is high, the TAS5036B is outputting data on all channels.
Architecture Overview
17
SLES073--February 2003
TAS5036B
2.2.4 Error Status Register
The error status register indicates historical information on control signal changes and clock errors. This
register latches these indications when they occur. The indications are cleared by writing a 00(Hex) to the
register.
This register is intended as a diagnostic tool to be used only when the system is not operating correctly. This
is because the error status bits are set when the data rate, serial data interface format, or master/slave mode
is changed. As a result, this register indicates an error condition even though the system is operating normally.
This register should only be used while diagnosing transient error conditions.
Any clock error or control signal terminal change which occurs since the last time the error status register was
cleared is displayed. In using this register, the first step is to initialize the device and verify that all of the clock
signals are active. Then this register should be cleared by writing a 00(Hex). At this point, the register indicates
any errors or control signal changes.
This register indicates an error condition by a high for the following conditions:
FS ERROR
A control terminal change has occurred (M_S, DBLSPD)
LRCLK error
MCLK_IN count error
DCLK phase error with respect to MCLK_IN
MCLK_IN phase error with respect to DCLK
PWM timing error
If all bits of the register are low, no errors have occurred and no control terminals changed.
There is no one-to-one correspondence of clock error indication to a system error condition. A particular
system error can be indicated by one or more error indications in this register. The system error conditions
and the reported errors are as follows:
There is no correct number of MCLKs per LRCLK:
FS error has occurred or
LRCLK error or
MCLK_IN count error
LRCLK is absent:
LRCLK error
MCLK is the wrong frequency, changing frequency, or absent:
DCLK phase error with respect to MCLK
MCLK phase error with respect to DCLK
PWM timing error
SCLK is the wrong frequency or absent
SCLK error
Architecture Overview
18
SLES073--February 2003
TAS5036B
2.3
Signal Processing
This section contains the signal processing functions that are contained in the TAS5036B. The signal
processing is performed using a high-speed 24-bit signal processing architecture. The TAS5036B performs
the following signal processing features:
Individual channel soft volume with a range of 24 dB to 114 dB plus mute
Soft mute
Automute
50-
s/15-
s de-emphasis filter supported in the sampling rates 32 kHz, 44.1 kHz, and 48 kHz
2.3.1 Volume Control
The gain of each output can be adjusted by a soft digital volume control for each channel. Volume adjustments
are performed using a soft gain update s-curve, which is approximated using a second order filter fit. The curve
fit is performed over a transition interval between 41 ms and 65 ms.
The volume of each channel can be adjusted from mute to 24 dB to 114 dB in 0.5 dB steps. Because of the
numerical representation that is used to control the volume, at very low volume levels the step size increases
for gains of that are less than 96 dB. The default volume setting following power up or reset is 0 dB for all
channels. The step size increases linearly up to approximately 90 dB, see Figure 210.
Attenuation (Gain) dB
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
110
100
90
80
70
60
50
40
30
20
10
0
10
20
Step Size
dB
STEP SIZE
vs
ATTENUATION (GAIN)
Figure 210. Attenuation Curve
The volume control format for each channel is expressed in 8 bits. The volume for each channel is set by writing
8 bits via the serial control interface. The MSB bit is written first as in the bit position 0 (LSB position).
The volume for each channel can be set using a single or multiple address write operation to the volume control
register via the serial control interface. Changing the volume of all six channels requires that 6 registers be
updated.
To coordinate the volume adjustment of multiple channels simultaneously, the TAS5036B performs a delayed
volume update upon receiving a volume change command. Following the completion of the register volume
write operations, the TAS5036B waits for 5 ms for another volume command to be given. If no volume
command is issued in that period of time, the TAS5036B starts adjusting the volume of the channels that
received volume settings.
Architecture Overview
19
SLES073--February 2003
TAS5036B
While a volume update is being performed, the system status register indicates that the update is in progress.
During the update, all subsequent volume control setting requests that are sent to the TAS5036B are received
and stored as a single next value for a subsequent update. If more than one volume setting request is sent,
only the last is retained.
Table 29. Volume Register
VOLUME REGISTER
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
Vol
Bit 7
Vol
Bit 6
Vol
Bit 5
Vol
Bit 4
Vol
Bit 3
Vol
Bit 2
Vol
Bit 1
Vol
Bit 0
2.3.2 Mute
The application of mute ramps the volume from any setting to noiseless hard mute state. There are two
methods in which the TAS5036B can be placed into mute. The TAS5036B is placed in the noiseless mute when
the MUTE terminal is asserted low for a minimum of 3 MCLK_IN cycles. Alternatively, the mute mode can be
initiated by setting the mute bit in the system control register through the serial control interface. The
TAS5036B is held in mute state as long as the terminal is low or I
2
C mute setting is active. This command uses
quiet entry and exit sequences to and from the hard mute state.
If an error recovery (described in the PWM section) occurs after a mute request has been received, the device
returns from error recovery with the channel volume set as specified by the mute command.
2.3.3 Auto Mute
Automute is an automatic sequence that can be enabled or disabled via the serial control interface. The default
for this control is enabled. When enabled, the PWM automutes an individual channel when a channel receives
from 5 ms to 50 ms of consecutive zeros. This time interval can be selectable using the automute delay
register. The default interval is 5 ms at 48 kHz. This duration is independent of the sample rate. The automute
state is exited when two consecutive samples of nonzero data are received. The TAS5036B exit from
automute is performed quickly and preserves all music information.
This mode uses the valid low to provide a low-noise floor while maintaining a short start-up time. Noise free
entry and exit is achieved by using the PWM quiet start and stop sequences.
2.3.4 Individual Channel Mute
Individual channel mute is invoked through the serial interface. Individual channel mute permits each channel
of the TAS5036B to be individually muted and unmuted. The operation that is performed is identical to the mute
operation; however, it is performed on a per channel basis. A TAS5036B channel is held in the mute state as
long as the serial interface mute setting for that channel is set.
2.3.5 De-Emphasis Filter
For audio sources that have been pre-emphasized, a precision 50-
s/15-
s de-emphasis filter is provided to
support the sampling rates of 32 kHz, 44.1 kHz, and 48 kHz. See Figure 211 for a graph showing the
de-emphasis filtering characteristics. De-emphasis is set using two bits in the system control register.
Table 210. De-Emphasis Filter Characteristics
DEM_SEL2 (MSB)
DEM_SEL1
DESCRIPTION
0
0
De-emphasis disabled
0
1
De-emphasis enabled for Fs = 48 kHz
1
0
De-emphasis enabled for Fs = 44 kHz
1
1
De-emphasis enabled for Fs = 32 kHz
Following the change of state of the de-emphasis bits, the PWM outputs go into the soft mute state. After 128
LRCLK periods for initialization, the PWM outputs are driven to the normal (unmuted) mode.
Architecture Overview
20
SLES073--February 2003
TAS5036B
0
10
Response
dB
3.18 (50
s)
10.6 (15
s)
f Frequency kHz
De-Emphasis
Figure 211. De-Emphasis Filter Characteristics
2.4
Pulse Width Modulator (PWM)
The TAS5036B contains six channels of high performance digital Equibit PWM modulators that are designed
to drive switching output stages (back ends) in both single-ended (SE) and H-bridge (bridge tied load)
configuration. The TAS5036B device uses noise shaping and sophisticated error correction algorithms to
achieve high power efficiency and high-performance digital audio reproduction.
The PWM provides six pseudo-differential outputs to drive six monolithic power stages (such as TAS5110)
or six discrete differential power stages using gate drivers (such as the TAS5182) and MOSFETs in
single-ended or bridged configurations. The TAS5036B also provides a high performance differential output
that can be used to drive an external analog headphone amplifier.
2.4.1 Clipping Indicator
The clipping output is designed to indicate clipping. When any of the six PWM outputs exceeds the maximum
allowable amplitude, the clipping indicator is asserted. The clipping indicator is cleared every 10 ms.
2.4.2 Error Recovery
Error recovery is used to provide error management and to permit the PWM output to be reset while preserving
all intervolume, interchannel delay, dc offsets, and the other internal settings. Error recovery is initiated by
bringing the ERR_RCVRY terminal low for a minimum 5 MCLK_IN cycles or by setting the error recovery bit
in control register 1. Error recovery is a level sensitive signal.
The device also performs an error recovery automatically:
When the speed configuration is changed to normal, double, or quad speed
Following a change in the serial data bus interface configuration
When ERR_RCVRY is brought low, all valid signals go low, and the PWM-P and PWM-M outputs go low. If
there are any pending speed configurations, these changes are then performed. When ERR_RCVRY is
brought high, a delay of 4 ms to 5 ms is performed before the system starts the output re-initialization
sequence. After the initialization time, the TAS5036B begins normal operation. During error recovery, all
controls and device settings that were not updated are maintained in their current configurations.
To permit error recovery to be used to provide TAS5100 error management and recovery, the delay between
the start of (falling edge) error recovery and the falling edge of valid 1 though valid 6 is selectable. This delay
can be selected to be either 6
s or 47
s.
During error recovery all serial data bus operations are ignored. At the conclusion of the sequence, the error
recovery register bit is returned to normal operation state. Table 211 shows the device output signal states
while during error recovery.
Architecture Overview
21
SLES073--February 2003
TAS5036B
Table 211. Device Outputs During Error Recovery
SIGNAL
MODE
SIGNAL STATE
Valid 1Valid 6
All
Low
PWM P-outputs
All
Low
PWM M-outputs
All
Low
MCLKOUT
All
Low
SCLK
Master
Low
SCLK
Slave
Signal input
LRCLK
Master
Low
LRCLK
Slave
Signal input
SDA
All
Signal input
CLIP
All
High
The transitions are done using a quiet entrance and exit sequence to prevent pops and clicks.
2.4.3 Individual Channel Error Recovery
Individual channel error recovery is used to provide error management and to permit the PWM output to be
turned off. Error recovery is initiated by setting one or more of the six error recovery bits in the error recovery
register to low.
While the error recover bits are brought low, the valid signals go to the low state. When the error recovery bits
are brought high, a delay of 4 ms to 5 ms occurs before the channels are returned to normal operation.
The delay between the falling edge of the error recover bit and the falling edge of valid 1 though valid 6 is
selectable. This delay can be selected to be either 6
s or 47
s.
The TAS5036B controls the relative timing of the pseudo-differential drive control signals plus the valid signal
to minimize the production of system noise during error recovery operations. The transitions to valid low and
valid high are done using an almost quiet entrance and exit sequence to prevent pops and clicks.
2.4.4 PWM DC-Offset Correction
An 8-bit value can be programmed to each of the six PWM offset correction registers to correct for any offset
present in the output stages. The offset correction is divided into 256 intervals with a total offset correction of
1.56% of full scale. The default value is zero correction represented by 00 (hex). These values can be
changed at any time through the serial control interface.
2.4.5 Interchannel Delay
An 8-bit value can be programmed to each of the six PWM interchannel delay registers to add a delay per
channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock, DCLK
(or alternatively the external PLL clock frequency). Each subsequent channel has a default value that is N
DCLKs larger than the preceding channel. The default values are 0 for the first channel and 76 for each
successive channel.
These values can be updated upon power up through the serial control interface. This delay is generated in
the PWM block with the appropriate control signals generated in the CTL block.
These values can be changed at any time through the serial control interface.
2.4.6 ABD Delay
A 5-bit value is used to delay the A PWM signals with respect to B PWM signals. The value is the same for
all channels. It can be programmed from 0 to 31 DCLK clock cycles. The default values is 17 DCLK clock cycles
(01011). These values can be changed at any time through the serial control interface.
NOTE:
The performance of a TDAA system is optimized by setting the PWM timing based upon the
type of back-end device that is used and the layout. These values are set during initialization
using the I
2
C serial interface.
Architecture Overview
22
SLES073--February 2003
TAS5036B
2.4.7 PWM/H-Bridge and Discrete H-Bridge Driver Interface
The TAS5036B provides six PWM outputs, which are designed to drive switching output stages (back-ends)
in both single-ended (SE) and H-bridge (bridge tied load) configuration. The back-ends may be monolithic
power stages (such as the TAS5110) or six discrete differential power stages using gate drivers (such as the
the TAS55182) and MOSFETs in single-ended or bridged configurations.
The TAS5110 device is optimized for bridge tied load (BTL) configurations. These devices require a pure
differential PWM signal with a third signal (VALID) to control the MUTE state. In the MUTE state, the TAS5110
OUTA and OUTB are both low.
One Channel
of TAS5036B
PWM_AP
PWM_AM
VALID
TAS5110
OUTA
OUTB
AP
AM
RESET
BP
BM
Speaker
Figure 212. PWM Outputs and H-Bridge Driven in BTL Configuration
2.5
I
2
C Serial Control Interface
MCLK must be active for the TAS5036B to support I
2
C bus transactions. The TAS5036B has a bidirectional
serial control interface that is compatible with the I
2
C (Inter IC) bus protocol and supports both 100 KBPS and
400 KBPS data transfer rates for single and multiple byte write and read operations. This is a slave only device
that does not support a multi-master bus environment or wait state insertion. The control interface is used to
program the registers of the device and to read device status.
The TAS5036B supports the standard-mode I
2
C bus operation (100 kHz maximum) and the fast I
2
C bus
operation (400 kHz maximum). The TAS5036B performs all I
2
C operations without I
2
C wait cycles.
The I
2
C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits
in a system. Data is transferred on the bus serially one bit at a time. The address and data are transferred in
byte (8 bit) format with the most significant bit (MSB) transferred first. In addition, each byte transferred on the
bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with
the master device driving a start condition on the bus and ends with the master device driving a stop condition
on the bus. The bus uses transitions on the data terminal (SDA) while the clock is high to indicate start and
stop conditions. A high-to-low transition on SDA indicates a start, and a low-to-high transition indicates a stop.
Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in
Figure 213. The master generates the 7-bit slave address and the read/write (R/W) bit to open
communication with another device and then waits for an acknowledge condition. The TAS5036B holds SDA
low during acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits
the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte).
All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. I
2
C An
external pullup resistor must be used for the SDA and SCL signals to set the high level for the bus.
Architecture Overview
23
SLES073--February 2003
TAS5036B
7 Bit Slave Address
R/W
8 Bit Register Address (N)
A
A
8 Bit Register Data For
Address (N)
A
8 Bit Register Data For
Address (N)
A
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Start
Stop
SDA
SCL
Figure 213. Typical I
2
C Sequence
There are no limits on the number of bytes that can be transmitted between start and stop conditions. When
the last word transfers, the master generates a stop condition to release the bus. A generic data transfer
sequence is also shown in Figure 213.
The 7-bit address for the TAS5036B is 001101X, where X is a programmable address bit. Using the CS0
terminal on the device, the LSB address bit is programmable to permit two devices to be used in a system.
These two addresses are licensed I
2
C addresses and do not conflict with other licensed I
2
C audio devices.
To communicate with the TAS5036B, the I
2
C master uses 0011010 if CS0=0 and 0011011 if CS0=1. In addition
to the 7-bit device address, an 8-bit register address is used to direct communication to the proper register
location within the device interface.
Read and write operations to the TAS5036B can be done using single byte or multiple byte data transfers.
2.5.1 Single Byte Write
As shown in Figure 214, a single byte data write transfer begins with the master device transmitting a start
condition followed by the I
2
C device address and the read/write bit. The read/write bit determines the direction
of the data transfer. For a write data transfer, the read/write bit is 0. After receiving the correct I
2
C device
address and the read/write bit, the TAS5036B device responds with an acknowledge bit. Next, the master
transmits the address byte or bytes corresponding to the TAS5036B internal memory address being
accessed. After receiving the address byte, the TAS5036B again responds with an acknowledge bit. Next, the
master device transmits the data byte to be written to the memory address being accessed. After receiving
the data byte, the TAS5036B again responds with an acknowledge bit. Finally, the master device transmits
a stop condition to complete the single byte data write transfer.
A6
A5
A4
A3
A2
A1
A0
R/W ACK A7
A6
A5
A4
A3
A2
A1
A0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Start Condition
Stop
Condition
Acknowledge
Acknowledge
Acknowledge
I2C Device Address and
Read/Write Bit
Register Address
Data Byte
Figure 214. Single Byte Write Transfer
2.5.2 Multiple Byte Write
A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes
are transmitted by the master device to TAS5036B as shown in Figure 215. After receiving each data byte,
the TAS5036B responds with an acknowledge bit.
Architecture Overview
24
SLES073--February 2003
TAS5036B
D7
D6
D1
D0 ACK
Stop
Condition
Acknowledge
I2C Device Address and
Read/Write Bit
Register Address
Last Data Byte
A6
A5
A1
A0
R/W ACK A7
A5
A1
A0
ACK D7
D6
D1
D0 ACK
Start Condition
Acknowledge
Acknowledge
Acknowledge
First Data Byte
A4
A3
A6
Other
Data Bytes
Figure 215. Multiple Byte Write Transfer
2.5.3 Single Byte Read
As shown in Figure 216, a single byte data read transfer begins with the master device transmitting a start
condition followed by the I
2
C device address and the read/write bit. For the data read transfer, a write followed
by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory
address to be read. As a result, the read/write bit is 0. After receiving the TAS5036B address and the read/write
bit, the TAS5036B responds with an acknowledge bit. Also, after sending the internal memory address byte
or bytes, the master device transmits another start condition followed by the TAS5036B address and the
read/write bit again. This time the read/write bit is a 1 indicating a read transfer. After receiving the TAS5036B
and the read/write bit, the TAS5036B again responds with an acknowledge bit. Next, the TAS5036B transmits
the data byte from the memory address being read. After receiving the data byte, the master device transmits
a not acknowledge followed by a stop condition to complete the single byte data read transfer.
A6
A5
A0 R/W ACK A7
A6
A5
A4
A0 ACK
A6
A5
A0
ACK
Start
Condition
Stop
Condition
Acknowledge
Acknowledge
Acknowledge
I2C Device Address and
Read/Write Bit
Register Address
Data Byte
D7
D6
D1
D0 ACK
I2C Device Address and
Read/Write Bit
Repeat Start Condition
Not
Acknowledge
R/W
A1
A1
Figure 216. Single Byte Read
2.5.4 Multiple Byte Read
A multiple byte data read transfer is identical to a single byte data read transfer except that multiple data bytes
are transmitted by the TAS5036B to the master device as shown in Figure 217. Except for the last data byte,
the master device responds with an acknowledge bit after receiving each data byte.
A6
A0
ACK
Acknowledge
I2C Device Address and
Read/Write Bit
R/W
A6
A0 R/W ACK
A4
A0
ACK
D7
D0 ACK
Start
Condition
Stop
Condition
Acknowledge
Acknowledge
Acknowledge
Last Data Byte
D7
D6
D1
D0
ACK
First Data Byte
Repeat Start
Condition
Not
Acknowledge
I2C Device Address and
Read/Write Bit
Register Address
Other
Data Bytes
A7
A6
A5
Figure 217. Multiple Byte Read
Serial Control Interface Register Definitions
25
SLES073--February 2003
TAS5036B
3
Serial Control Interface Register Definitions
Table 31 shows the register map for the TAS5036B. Default values in this section are in bold.
Table 31. I
2
C Register Map
ADDR HEX
DESCRIPTION
00
General status register
01
Error status register
02
System control register 0
03
System control register 1
04
Error recovery register
05
Automute delay
06
DC-offset control register channel 1
07
DC-offset control register channel 2
08
DC-offset control register channel 3
09
DC-offset control register channel 4
0A
DC-offset control register channel 5
0B
DC-offset control register channel 6
0C
Interchannel delay register channel 1
0D
Interchannel delay register channel 2
0E
Interchannel delay register channel 3
0F
Interchannel delay register channel 4
10
Interchannel delay register channel 5
11
Interchannel delay register channel 6
12
ABD delay register
13
Volume control register channel 1
14
Volume control register channel 2
15
Volume control register channel 3
16
Volume control register channel 4
17
Volume control register channel 5
18
Volume control register channel 6
19
Individual channel mute
The volume table is contained in Appendix A.
Default values are shown in bold in the following tables.
Serial Control Interface Register Definitions
26
SLES073--February 2003
TAS5036B
3.1
General Status Register (x00)
Table 32. General Status Register (Read Only)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
-
-
-
-
-
-
-
No volume update is in progress.
1
-
-
-
-
-
-
-
Volume update is in progress.
-
0
-
-
-
-
-
-
Always 0
-
-
1
0
0
1
1
-
Device identification code
-
-
-
-
-
-
-
0
Any valid signal is inactive (see status register (X03)) (see Note 1).
-
-
-
-
-
-
-
1
No internal errors (all valid signals are high)
NOTE 1: This bit is reset automatically when one or more channels are active.
3.2
Error Status Register (x01)
Table 33. Error Status Register
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
1
-
-
-
-
-
-
-
FS error has occurred
-
1
-
-
-
-
-
-
Control pin change has occurred
-
-
-
1
-
-
-
-
LRCLK error
-
-
-
-
1
-
-
-
MCLK_IN count error
-
-
-
-
-
1
-
-
DCLK phase error with respect to MCLK_IN
-
-
-
-
-
-
1
-
MCLK_IN phase error with respect to DCLK
-
-
-
-
-
-
-
1
PWM timing error
0
0
0
0
0
0
0
0
No errors--no control pins changed
NOTE 2: Write 00 hex to clear error indications in Error Status Register.
3.3
System Control Register 0 (x02)
Table 34. System Control Register 0
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
-
-
-
-
-
-
Normal mode (in slave mode--quad speed detected if MCLK_IN = 128 Fs)
0
1
-
-
-
-
-
-
Double speed
1
0
-
-
-
-
-
-
Quad speed
1
1
-
-
-
-
-
-
Illegal
-
-
0
-
-
-
-
-
Use de-emphasis pin controls
-
-
1
-
-
-
-
-
Use de-emphasis I2C controls
-
-
-
0
0
-
-
-
No de-emphasis
-
-
-
0
1
-
-
-
De-emphasis for Fs = 32 kHz
-
-
-
1
0
-
-
-
De-emphasis for Fs = 44.1 kHz
-
-
-
1
1
-
-
-
De-emphasis for Fs = 48 kHz
-
-
-
-
-
0
0
0
16 bit, MSB first; right justified
-
-
-
-
-
0
0
1
20 bit, MSB first; right justified
-
-
-
-
-
0
1
0
24 bit, MSB first; right justified
-
-
-
-
-
0
1
1
16-bit IIS
-
-
-
-
-
1
0
0
20-bit IIS
-
-
-
-
-
1
0
1
24-bit IIS
-
-
-
-
-
1
1
0
16-bit MSB first
-
-
-
-
-
1
1
1
16-bit DSP Frame
Serial Control Interface Register Definitions
27
SLES073--February 2003
TAS5036B
3.4
System Control Register 1 (x03)
Table 35. System Control Register 1
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
-
-
-
-
-
-
-
RESERVED Set to 0 in all cases
-
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
Valid remains high during automute.
-
1
-
-
-
-
-
-
Valid goes low during automute.
-
-
0
-
-
-
-
-
Valid remains high during mute.
-
-
1
-
-
-
-
-
Valid goes low during mute.
-
-
-
0
-
-
-
-
Mute
-
-
-
1
-
-
-
-
Normal mode
-
-
-
-
0
-
-
-
Set error recovery delay at 6
s
-
-
-
-
1
-
-
-
Set error recovery delay at 47
s
-
-
-
-
-
0
-
-
Error recovery (forces error recovery initialization sequence)
-
-
-
-
-
1
-
-
Normal mode
-
-
-
-
-
-
0
-
Automute disabled
-
-
-
-
-
-
1
-
Automute enabled
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
RESERVED Set to 0 in all cases
3.5
Error Recovery Register (x04)
Table 36. Error Recovery Register
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
1
1
Set to 11 under default conditions and when x00 is written into x1F
0
if x84 is written into x1F
Enable volume ramp up after an error recovery sequence is initiated by the
ERR_RCVRY terminal or the I2C error recovery command (register X03 bit D2)
1
if x84 is written into x1F
Disable volume ramp up after an error recovery sequence is initiated by the
ERR_RCVRY terminal or the I2C error recovery command (register X03 bit D2)
0
if x84 is written into x1F
Enable volume ramp up after error recovery sequence is initiated by register bits
D5 D0 of this register
1
if x84 is written into x1F
Enable volume ramp up after error recovery sequence is initiated by register bits
D5 D0 of this register
0
Put channel 6 into error recovery mode
0
Put channel 5 into error recovery mode
0
Put channel 4 into error recovery mode
0
Put channel 3 into error recovery mode
0
Put channel 2 into error recovery mode
0
Put channel 1 into error recovery mode
1
1
1
1
1
1
Normal operation
Serial Control Interface Register Definitions
28
SLES073--February 2003
TAS5036B
3.6
Automute Delay Register (x05)
Table 37. Automute Delay Register
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
0
-
-
-
-
Unused
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
Set automute delay at 5 ms
-
-
-
-
0
0
0
1
Set automute delay at 10 ms
-
-
-
-
0
0
1
0
Set automute delay at 15 ms
-
-
-
-
0
0
1
1
Set automute delay at 20 ms
-
-
-
-
0
1
0
0
Set automute delay at 25 ms
-
-
-
-
0
1
0
1
Set automute delay at 30 ms
-
-
-
-
0
1
1
0
Set automute delay at 35 ms
-
-
-
-
0
1
1
1
Set automute delay at 40 ms
-
-
-
-
1
-
-
0
Set automute delay at 45 ms
-
-
-
-
1
-
-
1
Set automute delay at 50 ms
3.7
DC-Offset Control Registers (x06x0B)
Channels 1, 2, 3, 4, 5, and 6 are mapped into (x06, x07, x08, x09, x0A, and x0B).
Table 38. DC-Offset Control Registers
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
1
0
0
0
0
0
0
0
Maximum correction for positive dc offset (1.56% FS)
0
0
0
0
0
0
0
0
No dc-offset correction
0
1
1
1
1
1
1
1
Maximum correction for negative dc offset (1.56% FS)
3.8
Interchannel Delay Registers (x0Cx11)
Channels 1, 2, 3, 4, 5, and 6 are mapped into (x0C, x0D, x0E, x0F, x10, and x11).
The first channel delay is set at 0. Each subsequent channel has a default value that is 76 DCLKs larger than
the preceding channel.
Table 39. Six Interchannel Delay Registers
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
0
0
0
0
0
Minimum absolute delay, 0 DCLK cycles, default for channel 1
0
1
0
0
1
1
0
0
Default for channel 2
1
0
0
1
1
0
0
0
Default for channel 3
1
1
1
0
0
1
0
0
Default for channel 4
0
0
1
1
0
0
0
0
Default for channel 5
0
1
1
1
1
1
0
0
Default for channel 6
1
1
1
1
1
1
1
1
Maximum absolute delay, 255 DCLK cycles
3.9
ABD Delay Register (x12)
Table 310. ABD Delay Register
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
-
-
-
-
-
Unused
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
Minimum ABD delay, 0 DLCK cycles
-
-
-
1
0
0
0
1
Default ABD delay, 17 DLCK cycles
-
-
-
1
1
1
1
1
Maximum ABD delay, 31 DLCK cycles
Serial Control Interface Register Definitions
29
SLES073--February 2003
TAS5036B
3.10 Individual Channel Mute Register (x19)
Table 311. Individual Channel Mute Register
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
1
1
-
-
-
-
-
-
Unused
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
No channels are muted
-
-
-
-
-
-
-
0
Mute channel 1
-
-
-
-
-
-
0
-
Mute channel 2
-
-
-
-
-
0
-
-
Mute channel 3
-
-
-
-
0
-
-
-
Mute channel 4
-
-
-
0
-
-
-
-
Mute channel 5
-
-
0
-
-
-
-
-
Mute channel 6
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
30
SLES073--February 2003
TAS5036B
4
System Procedures for Initialization, Changing Data Rates, and
Switching Between Master and Slave Modes
4.1
System Initialization
Reset is used during system initialization to hold the TAS5036B inactive while power (VDD), the master clock
(MCLK_IN), the device control, and the data signals become stable. The recommended initialization
sequence is to hold RESET low for 24 MCLK_IN cycles after VDD has reached 3 V and the other control
signals (MUTE, PDN, M_S, ERR_RCVRY, DBSPD, and CS0) are stable.
Figure 41 shows the recommended sequence and timing for the RESET terminal duing system VDD voltage
and MCLK.
MCLK
VDD
3 V
24 MCLK_IN
Cycles
RESET
Figure 41. RESET During System Initialization
Within the first 2 ms following the low-to-high transition of the RESET terminal, the serial data interface format
should be set in the serial data interface control register using the I
2
C serial control interface. If the data rate
setting is other than the setting specificed by the DBSPD terminal, then the data rate should be set using the
DBSPD terminal or I
2
C interface within 2 ms. following the low-to-high transition of the RESET terminal.
The time available to set the I
2
C registers following the low-to-high transition of the RESET terminal can be
extended using the ERR_RCVRY terminal. While ERR_RCVRY is low, the TAS5036B outputs are held
inactive. Once the I
2
C control registers are set, the ERR_RCVRY terminal can be released and the TAS5036B
starts operation. Figure 42 shows how the ERR_RCVRY terminal can be used to extend the interval as long
as necessary to set the I
2
C registers following the low-to-high transition of the RESET terminal.
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
31
SLES073--February 2003
TAS5036B
< 2 ms
MCLK
RESET
ERR_RCVRY
ERR_RCVRY and MUTE can
be set at any time prior to 2 ms
following the low-to-high
transistion of RESET
MUTE
Wait a minimum of 100
s
after the low-to-high
transistion of RESET
> 5 ms
Set serial interface format, data rate,
volume, ... via I2C
Release ERR_RCVRY and
then MUTE when I2C
registers are programmed
Volume ramp
up 120 ms
Figure 42. Extending the I
2
C Write Interval Following a Low-to-High Transition of the RESET Terminal
The operation of the TAS5036B can be tailored as desired to meet specific operating requirements by
adjusting the following:
Volume
Data sample rate
Emphasis/deemphasis settings
Individual channel mute
Automute delay register
DC-offset control registers
If desired, the TAS5036B can be set to perform an unmute sequence following the low-to-high transition of
the ERR_RCVRY terminal or the error recovery I
2
C command (register X03 bit D2). This capability is set by
writing x7F to the individual error recovery register (x04) and an x84 to x1F (a feature enable register).
4.2
Data Sample Rate
If the master clock is well-behaved during the frequency transition (no MCLK_IN high or low clock periods less
than 20 ns) then a simple speed selection is performed by setting the DBSPD terminal or the serial control
register. If it is known at least 60 ms in advance that the sample rate is going to change, mute can be used
to provide a completely silent transition. The timing of this control sequence is shown in Figure 43 and
Figure 44.
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
32
SLES073--February 2003
TAS5036B
MCLK
MUTE
Terminal
DBSPD
Terminal
Change from a 96-kHz data rate
MCLK_IN = 24.576 MHz
Clock transition
Change to a 48-kHz data rate
MCLK_IN = 12.288 MHz
Volume ramp
up 42 65 ms
> 5 ms
< 2 ms
< 2 ms
Volume ramp
down 42 65 ms
Set within 2 ms
of transition
Figure 43. Changing the Data Sample Rate Using the DBSPD Terminal
MCLK
MUTE
Terminal
Change from a 96-kHz data rate
MCLK_IN = 24.576 MHz
Clock transition
Change to a 48-kHz data rate
MCLK_IN = 12.288 MHz
Volume ramp
up 42 65 ms
> 5 ms
< 2 ms
< 2 ms
Volume ramp
down 42 65 ms
Set data rate via I2C
register X02D7 and D6
ERR_RCVRY
Terminal
Hold ERR_RCVRY low
to give additional timeset registers
Figure 44. Changing the Data Sample Rate Using the I
2
C
However, if the master clock input can encounter a high clock or low clock period of less than 20 ns, then
RESET should be applied during this time. There are two recommended control procedures for this case,
depending upon whether the DBSPD terminal or the serial control interface is used. These control sequences
are shown in Figure 45 and Figure 46.
Because this sequence employs the RESET terminal the internal register settings are set to the default values.
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
33
SLES073--February 2003
TAS5036B
Figure 45 shows the procedure to change the data rate using the DBSPD terminal and then restore the
register settings. In this example, the ERR_RCVRY terminal is used to hold off system re-initialization after
RESET is released. This permits the system controller to have as much additional time as necessary to restore
the register settings.
Once the data rate is set, the ERR_RCVRY and MUTE terminal signals are set high and the system
re-initializes.
MCLK
MUTE
Terminal
ERR_RCVRY
Terminal
Change from a 96-kHz data rate
MCLK_IN = 24.576 MHz
Clock unstable during transition.
HIGH and LOW intervals < 20 ns
Change to a 48-kHz data rate
MCLK_IN = 12.288 MHz
Volume Ramp
Up 120 ms
Volume Ramp
Down 60 ms
ERR_RCVRY can be set at
any time within this interval
Wait a minimum of 100
s after the
LOW to HIGH transistion of RESET
Release ERR_RCVRY and
then MUTE when I2C
registers are programmed
> 5 ms
RESET
Terminal
DBSPD
Terminal
< 2 ms
Wait a minimum of
100
s to set DBSPD
Restore register
settings via I2C
Figure 45. Changing the Data Sample Rate With An Unstable MCLK_IN Using the DBSPD Terminal
Because this sequence employs the RESET terminal, the internal register settings are set to the default
values.
Figure 46 shows the procedure to change the data rate using register X02 D7 and D6 and then restore the
other register settings. In this example, the ERR_RCVRY terminal is used to hold off system re-initialization
after RESET is released. This permits the system controller to have as much additional time as necessary to
restore the register settings.
Once the data rate is set, the ERR_RCVRY and MUTE terminal signals are set high and the system
re-initializes.
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
34
SLES073--February 2003
TAS5036B
MCLK
MUTE
Terminal
ERR_RCVRY
Terminal
Change from a 96-kHz data rate
MCLK_IN = 24.576 MHz
Clock unstable during transition.
HIGH and LOW intervals < 20 ns
Change to a 48-kHz data rate
MCLK_IN = 12.288 MHz
Volume Ramp
Up 120 ms
Volume Ramp
Down 60 ms
ERR_RCVRY can be set at
any time within this interval
Wait a minimum of 100
s after the
LOW to HIGH transistion of RESET
Release ERR_RCVRY and
then MUTE when I2C
registers are programmed
> 5 ms
RESET
Terminal
< 2 ms
Set data rate and
restore other
register settings
via I2C
Figure 46. Changing the Data Sample Rate With An Unstable MCLK_IN Using the I
2
C
4.3
Changing Between Master and Slave Modes
The master and slave mode is set while the RESET terminal is active. Because this sequence employs the
RESET terminal the internal register settings are set to the default values.
Figure 47 shows the procedure to switch between master and slave modes and then restore the register
settings. In this example, the ERR_RCVRY terminal is used to hold off system re-initialization after RESET
is released. This permits the system controller to have as much additional time as necessary to restore the
register settings.
Once the data rate is set, the ERR_RCVRY and MUTE terminal signals are set high and the system
re-initializes.
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
35
SLES073--February 2003
TAS5036B
MCLK
MUTE
Terminal
ERR_RCVRY
Terminal
Change from Master Mode
Clock unstable during transition.
Change to Slave Mode
Volume Ramp
Up 120 ms
Volume Ramp
Down 60 ms
ERR_RCVRY can be set at
any time within this interval
Wait a minimum of 100
s after the
LOW to HIGH transistion of RESET
Release ERR_RCVRY and
then MUTE when I2C
registers are programmed
> 5 ms
RESET
Terminal
M_S
Terminal
< 2 ms
Wait a minimum of
100
s to set M_S
Restore register
settings via I2C
Figure 47. Changing Between Master and Slave Clock Mode
Specifications
36
SLES073--February 2003
TAS5036B
5
Specifications
5.1
Absolute Maximum Ratings Over Operating Temperature Ranges (Unless
Otherwise Noted)
Digital supply voltage range: DVDD_CORE, DVDD_PWM, DVDD_RCL
0.3 V to 4.2 V
. . . . . . . . . . . . . . . . . .
Analog supply voltage range: AVDD_PLL, ADD_OSC
0.3 V to 4.2 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range, V
I
0.3 V to DVDDX + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature
0
C to 70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD
2000 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
5.2
Recommended Operating Conditions (Fs = 48 kHz)
MIN
TYP
MAX
UNIT
Supply voltage
Digital
DVDDX, See Note 1
3
3.3
3.6
V
Supply current
Digital
Operating
60
mA
Supply current
Digital
Power down, See Note 2
25
A
Power dissipation
Digital
Operating
200
mW
Power dissipation
Digital
Power down
100
W
Supply voltage
Analog
AVDDX, See Note 3
3
3.3
3.6
V
Supply current
Analog
Operating
10
mA
Supply current
Analog
Power down, See Note 2
25
A
Power dissipation
Analog
Operating
35
mW
Power dissipation
Analog
Power down, See Note 2
100
W
NOTES:
3. DVDD_CORE, DVDD_PWM, DVDD_RCL
4. If the clocks are turned off.
5. AVDD_PLL, AVDD_OSC
5.3
Electrical Characteristics Over Recommended Operating Conditions (Unless
Otherwise Noted)
5.3.1
Static Digital Specifications Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
VIH
High-level input voltage
2
DVDD1
V
VIL
Low-level input voltage
0
0.8
V
VOH
High-level output voltage
IO = 1 mA
2.4
V
VOL
Low-level output voltage
IO = 4 mA
0.4
V
Ilkg
Input leakage current
10
10
A
5.3.2
Digital Interpolation Filter and PWM Modulator Over Recommended Operating
Conditions (Unless Otherwise Noted) Fs = 48 kHz
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pass band
0
20
kHz
Pass band ripple
0.012
dB
Stop band
24.1
kHz
Stop band attenuation
24.1 kHz to 152.3 kHz
50
dB
Group delay
700
s
PWM modulation index (gain)
0.93%
Specifications
37
SLES073--February 2003
TAS5036B
5.3.3
TAS5036B/TAS5182 System Performance Measured at the Speaker Terminals
Over Recommended Operating Conditions (Unless Otherwise Noted)
Fs = 48 kHz
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SNR (EIAJ)
A-weighted
100
dB
Dynamic range
A-weighted, -60 dB, f = 1 kHz, 20 Hz20 kHz
100
dB
THD+N
0 dB, 1 kHz, 20 Hz20 kHz
0.09%
5.4
Switching Characteristics
5.4.1
Command Sequence Timing
5.4.1.1
Reset Timing--RESET
CONTROL SIGNAL PARAMETERS OVER RECOMMENDED OPERATING CONDITIONS (UNLESS OTHERWISE NOTED)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tw(RESET)
Pulses duration, RESET active
50
ns
tp(VALID_LOW)
Propagation delay
1
s
tp(VALID_HIGH) Propagation delay
4
5
ms
td(VOLUME)
Delay time
42
65
ms
tw(RESET)
tp(VALID_HIGH)
RESET
tp(VALID_LOW)
td(VOLUME)
VALID 16
VOLUME 16
Figure 51. RESET Timing
Specifications
38
SLES073--February 2003
TAS5036B
5.4.1.2
Power-Down Timing--PDN
5.4.1.2.1 Long Recovery
CONTROL SIGNAL PARAMETERS OVER RECOMMENDED OPERATING CONDITIONS (UNLESS OTHERWISE NOTED)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tw(PDN)
Pulse duration, PDN active
50
ns
td(R PDNR)
Reset high to PDN rising edge
16 MCLKS
ns
tp(VALID_LOW)
1
s
tp(VALID_HIGH)
85
100
ms
td(VOLUME)
42
65
ms
RESET
tp(VALID_LOW)
VALID 16
VOLUME 16
PDN
Normal
Operation
td(R PDNR)
tw(PDN)
tp(VALID_HIGH)
td(VOLUME)
Normal
Operation
Figure 52. Power-Down and Power-Up Timing--RESET Preceding PDN
Specifications
39
SLES073--February 2003
TAS5036B
5.4.1.2.2 Short Recovery
CONTROL SIGNAL PARAMETERS OVER RECOMMENDED OPERATING CONDITIONS (UNLESS OTHERWISE NOTED)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tw(PDN)
Pulse duration, PDN active
50
ns
td(R PDNR)
PDN high to reset rising edge
16 MCLKS
ns
tp(VALID_LOW)
1
s
tp(VALID_HIGH)
4
5
ms
td(VOLUME)
42
65
ms
RESET
tp(VALID_LOW)
VALID 16
VOLUME 16
PDN
Normal
Operation
tw(PDN)
tp(VALID_HIGH)
td(VOLUME)
Normal
Operation
td(R PDNR)
Figure 53. Power-Down and Power-Up Timing--RESET Following PDN
5.4.1.3
Error Recovery Timing--ERR_RCVRY
CONTROL SIGNAL PARAMETERS OVER RECOMMENDED OPERATING CONDITIONS (UNLESS OTHERWISE NOTED)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tw(ER)
Pulse duration, ERR_RCVRY active
5 MCLKS
ns
tp(VALID_LOW)
Selectable for minimum or maximum
6
47
s
tp(VALID_HIGH)
Selectable for minimum or maximum
4
5
ms
Specifications
40
SLES073--February 2003
TAS5036B
ERR_RCVRY
tp(VALID_LOW)
VALID 16
tw(ER)
tp(VALID_HIGH)
Normal
Operation
Normal
Operation
Figure 54. Error Recovery Timing
5.4.1.4
MUTE Timing--MUTE
CONTROL SIGNAL PARAMETERS OVER RECOMMENDED OPERATING CONDITIONS (UNLESS OTHERWISE NOTED)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tw(MUTE)
Pulse duration, PDN active
3 MCLKS
ns
td(VOL)
42
ms
td(VOL)
VOLUME
MUTE
Normal
Operation
VALID 16
Normal
Operation
td(VOL)
tw(MUTE)
Figure 55. Mute Timing
Specifications
41
SLES073--February 2003
TAS5036B
5.4.2 Serial Audio Port
5.4.2.1
Serial Audio Ports Slave Mode Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
MIN
TYP
MAX
UNIT
f(SCLK)
Frequency, SCLK
12.288
MHz
tsu(SDIN)
SDIN setup time before SCLK rising edge
20
ns
th(SDIN)
SDIN hold time before SCLK rising edge
10
ns
f(LRCLK)
LRCLK frequency
32
48
192
kHz
MCLK_IN duty cycle
50%
SCLK duty cycle
50%
LRCLK duty cycle
50%
tsu(LRCLK)
LRCLK setup time before SCLK rising edge
20
ns
MCLK high and low time
20
ns
5.4.2.2
Serial Audio Ports Master Mode, Load Conditions 50 pF Over Recommended
Operating Conditions (Unless Otherwise Noted)
PARAMETER
MIN
TYP
MAX
UNIT
t(MSD)
MCLK_IN to SCLK
0
5
ns
t(MLRD)
MCLK_IN to LRCLK
0
5
ns
5.4.2.3
DSP Serial Interface Mode Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
MIN
TYP
MAX
UNIT
f(SCLK)
SCLK frequency
12.288
MHz
td(FS)
Delay time, SCLK rising to Fs
ns
tw(FSHIGH)
Pulse duration, sync
1/(64xfs)
ns
tsu(SDIN)
SDIN and LRCLK setup time before SCLK falling edge
20
ns
th(SDIN)
SDIN and LRCLK hold time from SCLK falling edge
10
ns
SCLK duty cycle
50%
th(SDIN)
tsu(SDIN)
SCLK
SDIN
Figure 56. Right-Justified, IIS, Left-Justified Serial Protocol Timing
Specifications
42
SLES073--February 2003
TAS5036B
tsu(LRCLK)
SCLK
LRCLK
NOTE: Serial data is sampled with the rising edge of SCLK (setup time = 20 ns and hold time = 10 ns).
Figure 57. Right, Left, and IIS Serial Mode Timing Requirement
LRCLK
SCLK
MCLK
t(MRLD)
t(MSD)
Figure 58. Serial Audio Ports Master Mode Timing
LRCLK
SCLK
SDIN
tsu(LRCLK)
th(LRCLK)
tw(FSHIGH)
tsu(SDIN)
th(SDIN)
Figure 59. DSP Serial Port Timing
Specifications
43
SLES073--February 2003
TAS5036B
64 SCLKS
SCLK
LRCLK
SDIN
16 Bits Left Channel
16 Bits Right Channel
32 Bits Unused
tw(FSHIGH)
Figure 510. DSP Serial Port Expanded Timing
SCLK
SDIN
tsu(SDIN) = 20 ns
th(SDIN) = 10 ns
Figure 511. DSP Absolute Timing
Specifications
44
SLES073--February 2003
TAS5036B
5.4.3 Serial Control Port--I
2
C Operation
5.4.3.1
Timing Characteristics for I
2
C Interface Signals Over Recommended Operating
Conditions (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
STANDARD
MODE
FAST MODE
UNIT
PARAMETER
TEST CONDITIONS
MIN
MAX
MIN
MAX
UNIT
fSCL
Frequency, SCL
0
100
0
400
kHz
tw(H)
Pulse duration, SCL high
4
0.6
s
tw(L)
Pulse duration, SCL low
4.7
1.3
s
tr
Rise time, SCL and SDA
1000
300
ns
tf
Fall time, SCL and SDA
300
300
ns
tsu1
Setup time, SDA to SCL
250
100
ns
th1
Hold time, SCL to SDA
0
0
ns
t(buf)
Bus free time between stop and start condition
4.7
1.3
s
tsu2
Setup time, SCL to start condition
4.7
0.6
s
th2
Hold time, start condition to SCL
4
0.6
s
tsu3
Setup time, SCL to stop condition
4
0.6
s
CL
Load capacitance for each bus line
400
400
pF
SCLK
SDA
th1
tw(L)
tf
tr
tsu
tw(H)
Figure 512. SCL and SDA Timing
SCLK
SDA
th2
t(buf)
tsu2
tsu3
Start Condition
Stop Condition
Figure 513. Start and Stop Conditions Timing
Application
Information
45
SLES073
--
February
2003
T
AS5036B
6
Application Information
PWM Ch.
Output Control
A
VDD_PLL
A
VSS_PLL
VREGA_CAP
VREGB_CAP
VREGC_CAP
DVDD_RCL
DVSS_RCL
DVDD_PWM
DVSS_PWM
Power Supply
PLL_FLT_1
PLL_FLT_2
SCLK
LRCLK
MCLKOUT
SDIN1
SDIN2
SDIN3
MCLK_IN
XTAL_OUT
XTAL_IN
SDA
SCL
CSO
PWM_AP_1
VALID_1
PWM_AP_2
VALID_2
PWM AP_3
VALID_3
PWM_AP_4
VALID_4
PWM_AP_5
VALID_5
PWM_AP_6
VALID_6
PWM AM_3
PWM_AM_1
PWM_AM_2
PWM_AM_4
PWM_AM_5
PWM_AM_6
Clock,
PLL
and
Serial
Data
I/F
PDN
RESET
MUTE
CLIP
ERR_RCVY
Serial
Control
I/F
Reset,
Pwr Dwn
and
Status
Auto Mute
De-emphasis
Soft Volume
Error Recovery
Soft Mute
Clip Detect
Signal
Processing
PWM
Section
PWM Ch.
PWM Ch.
PWM Ch.
PWM Ch.
PWM Ch.
PWAP
PWBM
PWAM
PWBP
RESET
SHUTDOWN
TAS5110
H-Bridge
M_S
DA610
DSP
CLKOUT
ACLKX
ALKX1
ALKX0
AFSX
ALKX2
MSP430
P1.5/IA1/TDI
P1.0
P1.3
P1.1
P2.0
P1.4/SMCLK/TCK
P1.2
PWAP
PWBM
PWAM
PWBP
RESET
SHUTDOWN
TAS5110
H-Bridge
PWAP
PWBM
PWAM
PWBP
RESET
SHUTDOWN
TAS5110
H-Bridge
PWAP
PWBM
PWAM
PWBP
RESET
SHUTDOWN
TAS5110
H-Bridge
PWAP
PWBM
PWAM
PWBP
RESET
SHUTDOWN
TAS5110
H-Bridge
PWAP
PWBM
PWAM
PWBP
RESET
SHUTDOWN
TAS5110
H-Bridge
DM_SEL1
DM_SEL2
DBSPD
Figure 6
1.
T
ypical T
AS5036B
Application
Application Information
46
SLES073--February 2003
TAS5036B
6.1
Serial Audio Interface Clock Master and Slave Interface Configuration
6.1.1 Slave Configuration
TAS5036
(Slave mode)
SDIN1
SDIN2
SDIN3
XTALI
XTALO
DA610 DSP
(Master Mode)
CLKOUT
AFSX
ACLKR
ALKX0
ALKX1
ALKX2
ACLKX
AFSR
CLKIN
ALKR0
PCM1800
ADC
SYSCLK
LRCK
DOUT
BCK
Left
Analog
Right
Analog
ALKR1
ALKR2
Other Digital
Audio Sources
LRCK
SCLK
MCLKO
12.288
MHz XTAL
OSCI
OSCO
GND
NC
MCLKO
Figure 62. TAS5036B Serial Audio Port--Slave Mode Connection Diagram
6.1.2 Master Configuration
TAS5036
(Master Mode)
SDIN1
SDIN2
SDIN3
XTALI
XTALO
DA610 DSP
CLKOUT
AFSX
ACLKR
ALKX0
ALKX1
ALKX2
ACLKX
AFSR
CLKIN
ALKR0
PCM1800
ADC
SYSCLK
LRCK
DOUT
BCK
Left
Analog
Right
Analog
ALKR1
ALKR2
Other Digital
Audio Sources
LRCK
SCLK
MCLKO
12.288
MHz XTAL
GND
MCLKO
Figure 63. TAS5036B Serial Audio Port--Master Mode Connection Diagram
Mechanical Data
47
SLES073--February 2003
TAS5036B
7
Mechanical Data
PFC (S-PQFP-G80)
PLASTIC QUAD FLATPACK
4073177 / B 11/96
40
21
0,13 NOM
0,25
0,75
0,45
Seating Plane
0,05 MIN
Gage Plane
0,27
41
0,17
20
60
1
61
80
SQ
SQ
12,20
13,80
14,20
11,80
9,50 TYP
1,05
1,20 MAX
0,95
0,08
0,50
M
0,08
0
7
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Appendix A--Volume Table
49
SLES073--February 2003
TAS5036B
Appendix A--Volume Table
VOLUME
SETTING
REGISTER VOLUME
(BIN)
GAIN dB
D7 D0
249
11111001
24
248
11111000
23.5
247
11110111
23
246
11110110
22.5
245
11110101
22
244
11110100
21.5
243
11110011
21
242
11110010
20.5
241
11110001
20
240
11110000
19.5
239
11101111
19
238
11101110
18.5
237
11101101
18
236
11101100
17.5
235
11101011
170
234
11101010
16.5
233
11101001
16
232
11101000
15.5
231
11100111
15
230
11100110
14.5
229
11100101
14
228
11100100
13.5
227
11100011
13
226
11100010
12.5
225
11100001
12
224
11100000
11.5
223
11011111
11
222
11011110
10.5
221
11011101
10
220
11011100
9.5
219
11011011
9
218
11011010
8.5
217
11011001
8
216
11011000
7.5
215
11010111
7
214
11010110
6.5
213
11010101
6
212
11010100
5.5
211
11010011
5
210
11010010
4.5
209
11010001
4
208
11010000
3.5
207
11001111
3
206
11001110
2.5
VOLUME
SETTING
REGISTER VOLUME
(BIN)
GAIN dB
D7 D0
205
11001101
2
204
11001100
1.5
203
11001011
1
202
11001010
0.5
201
11001001
0
200
11001000
0.5
199
11000111
1
198
11000110
1.5
197
11000101
2
196
11000100
2.5
195
11000011
3
194
11000010
3.5
193
11000001
4
192
11000000
4.5
191
10111111
5
190
10111110
5.5
189
10111101
6
188
10111100
6.5
187
10111011
7
186
10111010
7.5
185
10111001
8
184
10111000
8.5
183
10110111
9
182
10110110
9.5
181
10110101
10
180
10110100
10.5
179
10110011
11
178
10110010
11.5
177
10110001
12
176
10110000
12.5
175
10101111
13
174
10101110
13.5
173
10101101
14
172
10101100
14.5
171
10101011
15
170
10101010
15.5
169
10101001
16
168
10101000
16.5
167
10100111
17
166
10100110
17.5
165
10100101
18
164
10100100
18.5
163
10100011
19
162
10100010
19.5
Appendix A--Volume Table
50
SLES073--February 2003
TAS5036B
VOLUME
SETTING
REGISTER VOLUME
(BIN)
GAIN dB
D7 D0
161
10100001
20
160
10100000
20.5
159
10011111
21
158
10011110
21.5
157
10011101
22
156
10011100
22.5
155
10011011
23
154
10011010
23.5
153
10011001
24
152
10011000
24.5
151
10010111
25
150
10010110
25.5
149
10010101
26
148
10010100
26.5
147
10010011
27
146
10010010
27.5
145
10010001
28
144
10010000
28.5
143
10001111
29
142
10001110
29.5
141
10001101
30
140
10001100
30.5
139
10001011
31
138
10001010
31.5
137
10001001
32
136
10001000
32.5
135
10000111
33
134
10000110
33.5
133
10000101
34
132
10000100
34.5
131
10000011
35
130
10000010
35.5
129
10000001
36
128
10000000
36.5
127
01111111
37
126
01111110
37.5
125
01111101
38
124
01111100
38.5
123
01111011
39
122
01111010
39.5
121
01111001
40
120
01111000
40.5
119
01110111
41
118
01110110
41.5
117
01110101
42
VOLUME
SETTING
REGISTER VOLUME
(BIN)
GAIN dB
D7 D0
116
01110100
42.5
115
01110011
43
114
01110010
43.5
113
01110001
44
112
01110000
44.5
111
01101111
45
110
01101110
45.5
109
01101101
46
108
01101100
46.5
107
01101011
47
106
01101010
47.5
105
01101001
48
104
01101000
48.5
103
01100111
49
102
01100110
49.5
101
01100101
50
100
01100100
50.5
99
01100011
51
98
01100010
51.5
97
01100001
52
96
01100000
52.5
95
01011111
53
94
01011110
53.5
93
01011101
54
92
01011100
54.5
91
01011011
55
90
01011010
55.5
89
01011001
56
88
01011000
56.5
87
01010111
57
86
01010110
57.5
85
01010101
58
84
01010100
58.5
83
01010011
59
82
01010010
59.5
81
01010001
60
80
01010000
60.5
79
01001111
61
78
01001110
61.5
77
01001101
62
76
01001100
62.5
75
01001011
63
74
01001010
63.5
73
01001001
64
72
01001000
64.5
Appendix A--Volume Table
51
SLES073--February 2003
TAS5036B
VOLUME
SETTING
REGISTER VOLUME
(BIN)
GAIN dB
D7 D0
71
01000111
65
70
01000110
65.5
69
01000101
66
68
01000100
66.5
67
01000011
67
66
01000010
67.5
65
01000001
68
64
01000000
68.5
63
00111111
69
62
00111110
69.5
61
00111101
70
60
00111100
70.5
59
00111011
71
58
00111010
71.5
57
00111001
72
56
00111000
72.5
55
00110111
73
54
00110110
73.5
53
00110101
74
52
00110100
74.5
51
00110011
75
50
00110010
75.5
49
00110001
76
48
00110000
76.6
47
00101111
77
46
00101110
77.5
45
00101101
78
44
00101100
78.5
43
00101011
79
42
00101010
79.6
41
00101001
80.1
40
00101000
80.6
39
00100111
81.1
38
00100110
81.5
37
00100101
82.1
VOLUME
SETTING
REGISTER VOLUME
(BIN)
GAIN dB
D7 D0
36
00100100
82.6
35
00100011
83
34
00100010
83.5
33
00100001
84
32
00100000
84.6
31
00011111
85.1
30
00011110
85.8
29
00011101
86.1
28
00011100
86.8
27
00011011
87.2
26
00011010
87.5
25
00011001
88.4
24
00011000
88.8
23
00010111
89.3
22
00010110
89.8
21
00010101
90.3
20
00010100
90.9
19
00010011
91.5
18
00010010
92.1
17
00010001
92.8
16
00010000
93.6
15
00001111
94.4
14
00001110
95.3
13
00001101
96.3
12
00001100
97.5
11
00001011
98.8
10
00001010
100.4
9
00001001
102.4
8
00001000
104.9
7
00000111
108.4
6
00000110
114.4
5
00000101
MUTE
4
00000100
MUTE
3
00000011
MUTE
2
00000010
MUTE
1
00000001
MUTE
0
00000000
MUTE
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