Document Outline
- IMPORTANT NOTICE
- Contents
- List of Illustrations
- List of Tables
- Introduction
- Features
- Functional Block Diagram
- Terminal Assignments
- Ordering Information
- Terminal Functions
- Architecture Overview
- Clock and Serial Data Interface
- Normal-Speed, Double-Speed, and Quad-Speed Selection
- Clock Master/Slave Mode (M_S)
- Clock Master Mode
- Clock Slave Mode
- PLL Filter
- DCLK
- Serial Data Interface
- I2S Timing
- Left-Justified Timing
- Right-Justified Timing
- DSP Mode Timing
- Reset, Power Down, and Status
- ResetRESET\
- Power DownPDN\
- Status Registers
- Signal Processing
- Volume Control
- Mute
- Auto Mute
- Individual Channel Mute
- De-Emphasis Filter
- Pulse Width Modulator (PWM)
- Clipping Indicator
- Error Recovery
- Individual Channel Error Recovery
- PWM DC-Offset Correction
- Inter-Channel Delay
- ABD Delay
- PWM/H-Bridge and Discrete H-Bridge Driver Interface
- I2C Serial Control Interface
- Single Byte Write
- Multiple Byte Write
- Single Byte Read
- Multiple Byte Read
- Serial Control Interface Register Definitions
- General Status Register (x00)
- Error Status Register (x01)
- System Control Register 0 (x02)
- System Control Register 1 (x03)
- Error Recovery Register (x04)
- Automute Delay Register (x05)
- DC-Offset Control Registers (x06x0B)
- Interchannel Delay Registers (x0Cx11)
- ABD Delay Register (x12)
- Individual Channel Mute Register (x19)
- System Initialization
- Specifications
- Absolute Maximum Ratings Over Operating Temperature Ranges (Unless
Otherwise Noted)
- Recommended Operating Conditions (Fs = 48 kHz)
- Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted)
- Static Digital Specifications Over Recommended Operating Conditions (Unless Otherwise Noted)
- Digital Interpolation Filter and PWM Modulator Over Recommended Operating Conditions (Unless Otherwise Noted) Fs = 48 kHz
- TAS5036/TAS5100 System Performance Measured at the Speaker Terminals Over Recommended Operating Conditions (Unless Otherwise Noted) Fs = 48 kHz; Input = 1 Vrms Sine Wave at 1 kHz
- Switching Characteristics
- Command Sequence Timing
- Reset TimingRESET\
- Power-Down TimingPDN\
- Long Recovery
- Short Recovery
- Error Recovery TimingERR_RCVRY\
- MUTE TimingMUTE\
- Serial Audio Port
- Serial Audio Ports Slave Mode Over Recommended Operating Conditions (Unless Otherwise Noted)
- Serial Audio Ports Master Mode, Load Conditions 50 pF Over Recommended Operating Conditions (Unless Otherwise Noted)
- DSP Serial Interface Mode Over Recommended Operating Conditions (Unless Otherwise Noted)
- Serial Control PortI2C Operation
- Timing Characteristics for I2C Interface Siganals Over Recommended Operating Conditions (Unless Otherwise Noted)
- Application Information
- Serial Audio Interface Clock Master and Slave Interface Configuration
- Slave Configuration
- Master Configuration
- Appendix AVolume Table
TAS5036
Six Channel Digital Audio PWM Processor
November 2002
DAV Digital Audio/Speaker
Data Manual
SLES044B
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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Copyright
2002, Texas Instruments Incorporated
Contents
3
November 2002
SLES044B
Contents
Section
Page
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1.2
Functional Block Diagram . . . . . . . . . . . . .
2
1.3
Terminal Assignments . . . . . . . . . . . . . . . .
3
1.4
Ordering Information . . . . . . . . . . . . . . . . .
4
1.5
Terminal Functions . . . . . . . . . . . . . . . . . . .
4
2
Architecture Overview . . . . . . . . . . . . . . . . . . . . .
6
2.1
Clock and Serial Data Interface . . . . . . . .
6
2.1.1
Normal-Speed, Double-Speed,
and Quad-Speed Selection . .
6
2.1.2
Clock Master/Slave Mode
(M_S) . . . . . . . . . . . . . . . . . . . .
7
2.1.3
Clock Master Mode . . . . . . . . .
7
2.1.4
Clock Slave Mode . . . . . . . . . .
8
2.1.5
PLL Filter . . . . . . . . . . . . . . . . .
10
2.1.6
DCLK . . . . . . . . . . . . . . . . . . . . .
10
2.1.7
Serial Data Interface . . . . . . . .
10
2.2
Reset, Power Down, and Status . . . . . . .
15
2.2.1
Reset--RESET . . . . . . . . . . . .
15
2.2.2
Power Down--PDN . . . . . . . .
16
2.2.3
Status Registers . . . . . . . . . . .
16
2.3
Signal Processing . . . . . . . . . . . . . . . . . . .
17
2.3.1
Volume Control . . . . . . . . . . . .
17
2.3.2
Mute . . . . . . . . . . . . . . . . . . . . .
18
2.3.3
Auto Mute . . . . . . . . . . . . . . . . .
18
2.3.4
Individual Channel Mute . . . . .
18
2.3.5
De-Emphasis Filter . . . . . . . . .
18
2.4
Pulse Width Modulator (PWM) . . . . . . . . .
19
2.4.1
Clipping Indicator . . . . . . . . . . .
19
2.4.2
Error Recovery . . . . . . . . . . . .
19
2.4.3
Individual Channel Error Re-
covery . . . . . . . . . . . . . . . . . . . .
20
2.4.4
PWM DC-Offset Correction . .
20
2.4.5
Inter-Channel Delay . . . . . . . .
20
2.4.6
ABD Delay . . . . . . . . . . . . . . . .
20
2.4.7
PWM/H-Bridge and Discrete
H-Bridge Driver Interface . . . .
21
2.5
I2C Serial Control Interface . . . . . . . . . . .
21
2.5.1
Single Byte Write . . . . . . . . . . .
22
2.5.2
Multiple Byte Write . . . . . . . . .
22
2.5.3
Single Byte Read . . . . . . . . . . .
23
2.5.4
Multiple Byte Read . . . . . . . . .
23
3
Serial Control Interface Register Definitions .
24
3.1
General Status Register (x00) . . . . . . . . .
25
3.2
Error Status Register (x01) . . . . . . . . . . . .
25
3.3
System Control Register 0 (x02) . . . . . . .
25
3.4
System Control Register 1 (x03) . . . . . . .
26
3.5
Error Recovery Register (x04) . . . . . . . . .
26
3.6
Automute Delay Register (x05) . . . . . . . .
26
3.7
DC-Offset Control Registers (x06x0B) .
27
3.8
Interchannel Delay Registers (x0Cx11)
27
3.9
ABD Delay Register (x12) . . . . . . . . . . . . .
27
3.10
Individual Channel Mute Register (x19) .
27
4
System Initialization . . . . . . . . . . . . . . . . . . . . . . .
28
5
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
List of Illustrations
4
November 2002
SLES044B
5.1
Absolute Maximum Ratings Over Operat-
ing Temperature Ranges . . . . . . . . . . . . . .
29
5.2
Recommended Operating Conditions (Fs
= 48 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
5.3
Electrical Characteristics Over Recom-
mended Operating Conditions . . . . . . . . .
29
5.3.1
Static Digital Specifications
Over Recommended Operat-
ing Conditions . . . . . . . . . . . . .
29
5.3.2
Digital Interpolation Filter and
PWM Modulator Over Recom-
mended Operating Conditions
Fs = 48 kHz . . . . . . . . . . . . . . .
29
5.3.3
TAS5036/TAS5100 System
Performance Measured at the
Speaker Terminals Over
Recommended Operating
Conditions . . . . . . . . . . . . . . . . .
30
5.4
Switching Characteristics . . . . . . . . . . . . .
30
5.4.1
Command Sequence Timing .
30
5.4.2
Serial Audio Port . . . . . . . . . . .
34
5.4.3
Serial Control Port--I2C Op-
eration . . . . . . . . . . . . . . . . . . . .
37
6
Application Information . . . . . . . . . . . . . . . . . . . .
38
6.1
Serial Audio Interface Clock Master and
Slave Interface Configuration . . . . . . . . . .
39
6.1.1
Slave Configuration . . . . . . . . .
39
6.1.2
Master Configuration . . . . . . .
39
Appendix A--Volume Table . . . . . . . . . . . . . . . . . . . .
41
List of Illustrations
Figure
Title
Page
21 Crystal Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
22 External PLL Loop Filter . . . . . . . . . . . . . . . . . . . .
10
23 I2S 64-Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . .
11
24 I2S 48-Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . .
12
25 Left-Justified 64-Fs Format . . . . . . . . . . . . . . . . . .
12
26 Left-Justified 48-Fs Format . . . . . . . . . . . . . . . . . .
13
27 Right-Justified 64-Fs Format . . . . . . . . . . . . . . . . .
13
28 Right-Justified 48-Fs Format . . . . . . . . . . . . . . . . .
14
29 DSP Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
210 Attenuation Curve . . . . . . . . . . . . . . . . . . . . . . . . .
17
211 De-Emphasis Filter Characteristics . . . . . . . . . .
19
212 PWM Outputs and H-Bridge Driven in BTL
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
213 Typical I2C Sequence . . . . . . . . . . . . . . . . . . . . .
22
214 Single Byte Write Transfer . . . . . . . . . . . . . . . . .
22
215 Multiple Byte Write Transfer . . . . . . . . . . . . . . . .
23
216 Single Byte Read . . . . . . . . . . . . . . . . . . . . . . . . .
23
217 Multiple Byte Read . . . . . . . . . . . . . . . . . . . . . . . .
23
41 RESET During System Initialization . . . . . . . . . . .
28
51 RESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
52 Power-Down and Power-Up Timing--RESET
Preceding PDN . . . . . . . . . . . . . . . . . . . . . . . . .
31
53 Power-Down and Power-Up Timing--RESET
Following PDN . . . . . . . . . . . . . . . . . . . . . . . . . .
32
54 Error Recovery Timing . . . . . . . . . . . . . . . . . . . . . .
33
List of Tables
5
November 2002
SLES044B
55 Mute Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
56 Right-Justified, IIS, Left-Justified Serial Protocol
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
57 Right, Left, and IIS Serial Mode Timing
Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
58 Serial Audio Ports Master Mode Timing . . . . . . .
35
59 DSP Serial Port Timing . . . . . . . . . . . . . . . . . . . . .
35
510 DSP Serial Port Expanded Timing . . . . . . . . . . .
36
511 DSP Absolute Timing . . . . . . . . . . . . . . . . . . . . . .
36
512 SCL and SDA Timing . . . . . . . . . . . . . . . . . . . . . .
37
513 Start and Stop Conditions Timing . . . . . . . . . . . .
37
61 Typical TAS5036 Application . . . . . . . . . . . . . . . . .
38
62 TAS5036 Serial Audio Port--Slave Mode
Connection Diagram . . . . . . . . . . . . . . . . . . . . .
39
63 TAS5036 Serial Audio Port--Master Mode
Connection Diagram . . . . . . . . . . . . . . . . . . . . .
39
List of Tables
Table
Title
Page
21 Normal-Speed, Double-Speed, and Quad-Speed
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
22 Master and Slave Clock Modes . . . . . . . . . . . . . .
9
23 LRCLK, MCLK_IN, and External PLL Rates . . .
9
24 DCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
25 Supported Word Lengths . . . . . . . . . . . . . . . . . . . .
11
26 Device Outputs During Reset . . . . . . . . . . . . . . . .
15
27 Values Set During Reset . . . . . . . . . . . . . . . . . . . .
15
28 Device Outputs During Power Down . . . . . . . . . .
16
29 Volume Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
210 De-Emphasis Filter Characteristics . . . . . . . . . .
18
211 Device Outputs During Error Recovery . . . . . . .
20
31 I2C Register Map . . . . . . . . . . . . . . . . . . . . . . . . . .
24
32 General Status Register (Read Only) . . . . . . . . .
25
33 Error Status Register . . . . . . . . . . . . . . . . . . . . . . .
25
34 System Control Register 0 . . . . . . . . . . . . . . . . . .
25
35 System Control Register 1 . . . . . . . . . . . . . . . . . .
26
36 Error Recovery Register . . . . . . . . . . . . . . . . . . . .
26
37 Automute Delay Register . . . . . . . . . . . . . . . . . . . .
26
38 DC-Offset Control Registers . . . . . . . . . . . . . . . . .
27
39 Six Inter-Channel Delay Registers . . . . . . . . . . . .
27
310 ABD Delay Register . . . . . . . . . . . . . . . . . . . . . . .
27
311 Individual Channel Mute Register . . . . . . . . . . . .
27
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