TM
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FEATURES
APPLICATIONS
DESCRIPTION
PVDD - Supply Voltage - V
0
10
20
30
40
50
60
70
80
90
100
110
120
0
4
8
12
16
20
24
28
32
P
O
- Output Power - W
8
4
T
C
= 75
C
THD+N @ 10%
6
G002
TAS5142
SLES126B DECEMBER 2004 REVISED MAY 2005
STEREO DIGITAL AMPLIFIER POWER STAGE
deliver high-quality, high-efficiency audio amplification
with proven EMI compliance. This device requires two
2100 W at 10% THD+N Into 4-
BTL
(1)
power supplies, at 12 V for GVDD and VDD, and at
280 W at 10% THD+N Into 6-
BTL
32 V for PVDD. The TAS5142 does not require
power-up sequencing due to internal power-on reset.
265 W at 10% THD+N Into 8-
BTL
The efficiency of this digital amplifier is greater than
440 W at 10% THD+N Into 3-
SE
90% into 6
, which enables the use of smaller
430 W at 10% THD+N Into 4-
SE
power supplies and heatsinks.
1160 W at 10% THD+N Into 3-
PBTL
The TAS5142 has an innovative protection system
1200 W at 10% THD+N Into 2-
PBTL
(1)
integrated on-chip, safeguarding the device against a
wide range of fault conditions that could damage the
>100 dB SNR (A-Weighted)
system. These safeguards are short-circuit protection,
<0.1% THD+N at 1 W
overcurrent protection, undervoltage protection, and
Two Thermally Enhanced Package Options:
overtemperature protection. The TAS5142 has a new
DKD (36-pin PSOP3)
proprietary current-limiting circuit that reduces the
possibility of device shutdown during high-level music
DDV (44-pin HTSSOP)
transients. A new programmable overcurrent detector
High-Efficiency Power Stage (>90%) With
allows the use of lower-cost inductors in the demodu-
140-m
Output MOSFETs
lation output filter.
Power-On Reset for Protection on Power Up
BTL OUTPUT POWER vs SUPPLY VOLTAGE
Without Any Power-Supply Sequencing
Integrated Self-Protection Circuits Including
Undervoltage, Overtemperature, Overload,
Short Circuit
Error Reporting
EMI Compliant When Used With
Recommended System Design
Intelligent Gate Drive
Mini/Micro Audio System
DVD Receiver
Home Theater
The TAS5142 is a third-generation, high-perform-
ance, integrated stereo digital amplifier power stage
with an improved protection system. The TAS5142 is
(1) It is not recommended to drive 200 W (total
capable of driving a 4-
bridge-tied load (BTL) at up
power) into the DDV package continuously.
to 100 W per channel with low integrated noise at the
For multichannel systems that require two
output, low THD+N performance, and low idle power
channels to be driven at full power with the
DDV package option, it is recommended to
dissipation.
design the system so that the two channels
A low-cost, high-fidelity audio system can be built
are in two separate devices.
using a TI chipset, comprising a modulator (e.g.,
PurePath DigitalTM
TAS5508) and the TAS5142. This system only re-
quires a simple passive LC demodulation filter to
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath Digital, PowerPad are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright 20042005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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GENERAL INFORMATION
Terminal Assignment
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
GVDD_B
OTW
SD
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
AGND
VREG
M3
M2
M1
PWM_C
RESET_CD
PWM_D
VDD
GVDD_C
GVDD_A
BST_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
BST_D
GVDD_D
DKD PACKAGE
(TOP VIEW)
P0018-01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
GVDD_B
OTW
NC
NC
SD
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
AGND
VREG
M3
M2
M1
PWM_C
RESET_CD
PWM_D
NC
NC
VDD
GVDD_C
DDV PACKAGE
(TOP VIEW)
GVDD_A
BST_A
NC
PVDD_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
PVDD_D
NC
BST_D
GVDD_D
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
P0016-02
TAS5142
SLES126B DECEMBER 2004 REVISED MAY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
The TAS5142 is available in two thermally enhanced packages:
36-pin PSOP3 package (DKD)
44-pin HTSSOP PowerPadTM package (DDV)
Both package types contain a heat slug that is located on the top side of the device for convenient thermal
coupling to the heatsink.
2
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MODE Selection Pins for Both Packages
Package Heat Dissipation Ratings
(1)
TAS5142
SLES126B DECEMBER 2004 REVISED MAY 2005
GENERAL INFORMATION (continued)
MODE PINS
PWM INPUT
OUTPUT CONFIGURATION
PROTECTION SCHEME
M3
M2
M1
0
0
0
2N
(1)
AD/BD modulation
2 channels BTL output
BTL mode
(2)
0
0
1
Reserved
0
1
0
1N
(1)
AD modulation
2 channels BTL output
BTL mode
(2)
0
1
1
1N
(1)
AD modulation
1 channel PBTL output
PBTL mode. Only PWM_A input is used.
Protection works similarly to BTL mode
(2)
. Only
difference in SE mode is that OUT_X is Hi-Z
1
0
0
1N
(1)
AD modulation
4 channels SE output
instead of a pulldown through internal pulldown
resistor.
1
0
1
1
1
0
Reserved
1
1
1
(1)
The 1N and 2N naming convention is used to indicate the required number of PWM lines to the power stage per channel in a specific
mode.
(2)
An overload protection (OLP) occurring on A or B causes both channels to shut down. An OLP on C or D works similarly. Global errors
like overtemperature error (OTE), undervoltage protection (UVP), and power-on reset (POR) affect all channels.
PARAMETER
TAS5142DKD
TAS5142DDV
R
JC
(C/W)--2 BTL or 4 SE channels (8 transistors)
1.28
1.28
R
JC
(C/W)--1 BTL or 2 SE channel(s) (4 transistors)
2.56
2.56
R
JC
(C/W)--(1 transistor)
8.6
8.6
Pad area
(2)
80 mm
2
36 mm
2
(1)
JC is junction-to-case, CH is case-to-heatsink.
(2)
R
CH
is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink. The
R
CH
with this condition is 0.8C/W for the DKD package and 1.8C/W for the DDV package.
3
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ABSOLUTE MAXIMUM RATINGS
TAS5142
SLES126B DECEMBER 2004 REVISED MAY 2005
over operating free-air temperature range unless otherwise noted
(1)
TAS5142
VDD to AGND
0.3 V to 13.2 V
GVDD_X to AGND
0.3 V to 13.2 V
PVDD_X to GND_X
(2)
0.3 V to 50 V
OUT_X to GND_X
(2)
0.3 V to 50 V
BST_X to GND_X
(2)
0.3 V to 63.2 V
VREG to AGND
0.3 V to 4.2 V
GND_X to GND
0.3 V to 0.3 V
GND_X to AGND
0.3 V to 0.3 V
GND to AGND
0.3 V to 0.3 V
PWM_X, OC_ADJ, M1, M2, M3 to AGND
0.3 V to 4.2 V
RESET_X, SD, OTW to AGND
0.3 V to 7 V
Maximum continuous sink current (SD, OTW)
9 mA
Maximum operating junction temperature range, T
J
0C to 125C
Storage temperature
40C to 125C
Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds
260C
Minimum pulse duration, low
50 ns
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
ORDERING INFORMATION
T
A
PACKAGE
DESCRIPTION
0C to 70C
TAS5146DKD
36-pin PSOP3
0C to 70C
TAS5142DDV
44-pin HTSSOP
For the most current specification and package information, see the TI Web site at www.ti.com.
4
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Terminal Functions
TAS5142
SLES126B DECEMBER 2004 REVISED MAY 2005
TERMINAL
FUNCTION
(1)
DESCRIPTION
NAME
DKD NO.
DDV NO.
AGND
9
11
P
Analog ground
BST_A
35
43
P
HS bootstrap supply (BST), external capacitor to OUT_A required
BST_B
28
34
P
HS bootstrap supply (BST), external capacitor to OUT_B required
BST_C
27
33
P
HS bootstrap supply (BST), external capacitor to OUT_C required
BST_D
20
24
P
HS bootstrap supply (BST), external capacitor to OUT_D required
GND
8
10
P
Ground
GND_A
32
38
P
Power ground for half-bridge A
GND_B
31
37
P
Power ground for half-bridge B
GND_C
24
30
P
Power ground for half-bridge C
GND_D
23
29
P
Power ground for half-bridge D
GVDD_A
36
44
P
Gate-drive voltage supply requires 0.1-
F capacitor to AGND
GVDD_B
1
1
P
Gate-drive voltage supply requires 0.1-
F capacitor to AGND
GVDD_C
18
22
P
Gate-drive voltage supply requires 0.1-
F capacitor to AGND
GVDD_D
19
23
P
Gate-drive voltage supply requires 0.1-
F capacitor to AGND
M1
13
15
I
Mode selection pin
M2
12
14
I
Mode selection pin
M3
11
13
I
Mode selection pin
NC
3, 4, 19, 20, 25,
No connect. Pins may be grounded.
42
OC_ADJ
7
9
O
Analog overcurrent programming pin requires resistor to ground
OTW
2
2
O
Overtemperature warning signal, open-drain, active-low
OUT_A
33
39
O
Output, half-bridge A
OUT_B
30
36
O
Output, half-bridge B
OUT_C
25
31
O
Output, half-bridge C
OUT_D
22
28
O
Output, half-bridge D
PVDD_A
34
40, 41
P
Power supply input for half-bridge A requires close decoupling of
0.1-
F capacitor to GND_A.
PVDD_B
29
35
P
Power supply input for half-bridge B requires close decoupling of
0.1-
F capacitor to GND_B.
PVDD_C
26
32
P
Power supply input for half-bridge C requires close decoupling of
0.1-
F capacitor to GND_C.
PVDD_D
21
26, 27
P
Power supply input for half-bridge D requires close decoupling of
0.1-
F capacitor to GND_D.
PWM_A
4
6
I
Input signal for half-bridge A
PWM_B
6
8
I
Input signal for half-bridge B
PWM_C
14
16
I
Input signal for half-bridge C
PWM_D
16
18
I
Input signal for half-bridge D
RESET_AB
5
7
I
Reset signal for half-bridge A and half-bridge B, active-low
RESET_CD
15
17
I
Reset signal for half-bridge C and half-bridge D, active-low
SD
3
5
O
Shutdown signal, open-drain, active-low
VDD
17
21
P
Power supply for digital voltage regulator requires 0.1-
F capacitor
to GND.
VREG
10
12
P
Digital regulator supply filter pin requires 0.1-
F capacitor to AGND.
(1)
I = input, O = output, P = power
5
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