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FEATURES
PIN ASSIGNMENTS
APPLICATIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AI
AI
AO
E1
BO
BI
BI
GND
VCC
DI
DI
DO
E2
CO
CI
CI
D PACKAGE
(TOP VIEW)
DESCRIPTION
AI
AO
BO
CO
DO
AI
AI
BI
BI
C1
C1
D1
D1
D1
E2
E1
ENABLE TRUTH TABLE
TB3R1, TB3R2
SLLS587B NOVEMBER 2003 REVISED MAY 2004
QUAD DIFFERENTIAL PECL RECEIVERS
The power-down loading characteristics of the re-
ceiver input circuit are approximately 8 k
relative to
Low-Voltage Functional Replacements for the
the power supplies; hence they do not load the
Agere BRF1A, BRF2A, BRS2A, and BRS2B
transmission line when the circuit is powered down.
Pin-Equivalent to General Trade 26LS32 De-
The package for these differential line receivers is the
vices
16-pin SOIC (D) package.
High-Input Impedance Approximately 8 k
The enable inputs of this device include internal
3.5-ns Maximum Propagation Delay
pullup resistors of approximately 40 k
that are
TB3R1 Provides 50-mV Hysteresis
connected to V
CC
to ensure a logical high level input
if the inputs are open circuited.
TB3R2 With -125-mV Threshold Offset for
Preferred State Output
-0.5-V to 5.2-V Common Mode Range
Single 3.3 V
10% Supply
Slew Rate Limited (0.5 ns min 80% to 20%)
TB3R2 Output Defaults to Logic 1 When In-
puts Left Open or Shorted to V
CC
or GND
ESD Protection HBM > 3 kV, CDM > 2 kV
Operating Temperature Range: -40
C to 85
C
Available SOIC (D) Package
Digital Data or Clock Transmission Over Bal-
anced Lines
FUNCTIONAL BLOCK DIAGRAM
These quad differential receivers accept digital data
over balanced transmission lines. They translate
differential input logic levels to TTL output logic
levels.
The TB3R1 is a pin- and function-compatible replace-
ment for the Agere Systems BRF1A and BRF2A; it
includes 3-kV HBM and 2-kV CDM ESD protection.
The TB3R2 is a pin- and function-compatible replace-
ment for the Agere Systems BRS2A and BRS2B and
incorporates a -125-mV receiver input offset, pre-
ferred state output, 3-kV HBM and 2-kV CDM ESD
E1
E2
CONDITION
protection. The TB3R2 preferred state feature places
0
0
Active
the output in the high state when the inputs are open,
shorted to ground, or shorted to the power supply.
1
0
Active
0
1
Disabled
1
1
Active
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 20032004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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POWER DISSIPATION RATINGS
ABSOLUTE MAXIMUM RATINGS
TB3R1, TB3R2
SLLS587B NOVEMBER 2003 REVISED MAY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER
PART MARKING
Package
LEAD FIISH
STATUS
TB3R1D
TB3R1
SOIC
NiPdAu
Production
TB3R2D
TB3R2
SOIC
NiPdAu
Production
TB3R1LD
TB3R1
SOIC
SnPb
Production
TB3R2LD
TB3R2
SOIC
SnPb
Production
POWER RATING
THERMAL RESISTANCE,
DERATING FAC-
POWER RATING
CIRCUIT BOARD
PACKAGE
T
A
25
C
JUNCTION-TO-AMBIENT
TOR
(1)
T
A
= 85
C
MODEL
WITH NO AIR FLOW
T
A
25
C
Low-K
(1)
763 mW
131.1
C/W
7.6 mW/
C
305 mW
D
High-K
(2)
1190 mW
84.1
C/W
11.9 mW/
C
475 mW
Low-K
(1)
831 mW
120.3
C/W
8.3 mW/
C
332 mW
DW
High-K
(2)
1240 mW
80.8
C/W
12.4 mW/
C
494 mW
(1)
In accordance with the low-K thermal metric definitions of EIA/JESD51-3.
(2)
In accordance with the high-K thermal metric definitions of EIA/JESD51-7.
THERMAL CHARACTERISTICS
PARAMETER
PACKAGE
VALUE
UNIT
D
47.5
C/W
Junction-to-Board
JB
Thermal Resistance
DW
53.7
C/W
D
44.2
C/W
Junction-to-Case
JC
Thermal Resistance
DW
47.1
C/W
over operating free-air temperature range unless otherwise noted
(1)
UNIT
Supply voltage, V
CC
0 V to 6 V
Magnitude of differential bus (input) voltage, |V
AI
- V|, |V
BI
- V|, |V
CI
- V|, |V
DI
- V|
6.5 V
Human Body Model
(2)
All pins
3 kV
ESD
Charged-Device Model
(3)
All pins
2 kV
Continuous power dissipation
See Dissipation Rating Table
Storage temperature, T
stg
-65
C to 150
C
(1)
Stresses beyond those listed under,, absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(3)
Tested in accordance with JEDEC Standard 22, Test Method C101.
2
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RECOMMENDED OPERATING CONDITIONS
DEVICE ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
TB3R1, TB3R2
SLLS587B NOVEMBER 2003 REVISED MAY 2004
MIN
Nom
MAX UNIT
Supply voltage, V
CC
3
3.3
3.6
V
Bus pin input voltage, V
AI
, V, V
BI
, V, V
CI
, V, V
DI
, V
-0.6
(1)
5.3
V
Magnitude of differential input voltage, |V
AI
- V|, |V
BI
- V|, |V
CI
- V|, |V
DI
- V|
0.1
5
V
Operating free-air temperature, T
A
-40
85
C
(1)
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet, unless
otherwise noted.
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Outputs disabled
34
mA
I
CC
Supply current
(1)
Outputs enabled
32
mA
(1)
Current is dc power draw as measured through GND pin and does not include power delivered to load.
over operating free-air temperature range unless otherwise noted
parameter
test conditions
min
typ
max
unit
V
OL
Output low voltage
V
CC
= 3 V,
I
OL
= 8 mA
0.4
V
V
OH
Output high voltage
V
CC
= 3 V,
I
OH
= -400 A
2.4
V
V
IL
Low level enable input voltage
(1)
V
CC
= 3.6 V
0.8
V
V
IH
High level enable input voltage
(1)
V
CC
= 3.6 V
2
V
V
IK
Enable input clamp voltage
V
CC
= 3 V,
I
I
= -5 mA
-1
(2)
V
TB3R1
100
mV
V
TH+
Positive-going differential input threshold voltage
(1)
, (V
xl
- V)
x = A, B, C, or D
TB3R2
(3)
-50
mV
TB3R1
-100
(2)
mV
V
TH-
Negative-going differential input threshold voltage
(1)
, (V
xl
- V)
x = A, B, C, or D
TB3R2
(3)
-200
(2)
mV
V
HYST
Differential input threshold voltage hysteresis, (V
TH+
- V
TH_
)
TB3R1
50
mV
I
OZL
V
O
= 0.4 V
-20
(2)
A
Output off-state current, (High-Z)
V
CC
= 3.6 V
I
OZH
V
O
= 2.4 V
20
A
I
OS
Output short circuit current
(4)
V
CC
= 3.6 V
-100
(2)
mA
I
IL
Enable input low current
V
CC
= 3.6 V,
V
IN
= 0.4 V
-400
(2)
A
Enable input high current
V
IN
= 2.7 V
20
A
I
IH
V
CC
= 3.6 V
Enable input reverse current
V
IN
= 3.6 V
100
A
II
L
Differential input low current
V
CC
= 3.6 V,
V
IN
= -1.2 V
-2
(2)
mA
I
IH
Differential input high current
V
CC
= 3.6 V,
V
IN
= 5.3 V
1
mA
R
O
Output resistance
20
(1)
The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment.
(2)
This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original
Agere data sheet.
(3)
Outputs of unused receivers assume a logic 1 level when the inputs are left open. (It is recomended that all unused positive inputs be
tied to the positive power supply. No external series resistor is required.)
(4)
Test must be performed one lead at a time to prevent damage to the device.
3
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SWITCHING CHARACTERISTICS
TB3R1, TB3R2
SLLS587B NOVEMBER 2003 REVISED MAY 2004
over operating free-air temperature range unless otherwise noted
uni
parameter
test conditions
min
typ
max
t
t
PLH
Propagation delay time, low-to-high-level output
1.8
3.5
C
L
= 0 pF
(1)
, See Figure 2 and Figure 4
ns
t
PHL
Propagation delay time, high-to-low-level output
1.8
3.5
t
PLH
Propagation delay time, low-to-high-level output
2.3
4
C
L
= 15 pF, See Figure 2 and Figure 4
ns
t
PHL
Propagation delay time, high-to-low-level output
2.3
4
t
PHZ
Output disable time, high-level-to-high-impedance output
(2)
4.4
12
ns
C
L
= 5 pF See Figure 3 and Figure 5
t
PLZ
Output disable time, low-level-to-high-impedance output
(2)
3.3
12
ns
C
L
= 10 pF, See Figure 2 and Figure 4
0.7
ns
t
skew1
Pulse width distortion, |t
PHL
- t
PLH
|
C
L
= 150 pF, See Figure 2 and Figure 4
4
ns
C
L
= 10 pF, T
A
= 75
C, See Figure 2 and
0.8
1.4
ns
Figure 4
t
skew1p-p
Part-to-part output waveform skew
(3)
C
L
= 10 pF, T
A
= -40
C to 85
C, See
1.5
ns
Figure 2 and Figure 4
t
skew
Same part output waveform skew
(3)
C
L
= 10 pF, See Figure 2 and Figure 4
0.3
ns
t
PZH
Output enable time, high-impedance-to-high-level output
(4)
6
12
ns
C
L
= 10 pF, See Figure 3 and Figure 4
t
PZL
Output enable time, high-impedance-to-low-level output
(4)
4
12
ns
t
TLH
Rise time (20%-80%)
0.5
2
ns
C
L
= 10 pF, See Figure 2 and Figure 4
t
THL
Fall time (80%-20%)
0.5
2
ns
(1)
The propagation delay values with a 0 pF load are based on design and simulation.
(2)
See Table 1.
(3)
Output waveform skews are when devices operate with the same supply voltage, same temperature, have the same packages and the
same test circuits.
(4)
See Table 1.
4
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TYPICAL CHARACTERISTICS
0
2
4
6
8
0
50
100
150
200
t pd
- Propagation Delay T
ime - ns
C
L
- Load Capacitance - pF
t
PHL
t
PLH
T
A
= 25
5
C
V
CC
= 3.3 V
OUTPUT
3.7 V
2.7 V
3.2 V
VOH
V OL
1.5 V
tTHL
tPHL
tPLH
tTLH
20%
80%
20%
80%
INPUT
INPUT
TB3R1, TB3R2
SLLS587B NOVEMBER 2003 REVISED MAY 2004
TYPICAL PROPAGATION DELAY
vs
LOAD CAPACITANCE
A.
NOTE
:
This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The
total delay is the sum of the delay due to external capacitance and the intrinsic delay of the device. Intrinsic delay is
listed in the table above as the 0 pF load condition. The incremental increase in delay between the 0 pF load
condition and the actual total load capacitance represents the extrinsic, or external delay contributed by the load.
Figure 1. Typical Propagation Delay vs Load Capacitance at 25
C
Figure 2. Receiver Propagation Delay Times
5
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OUTPUT
2.4 V
0.4 V
1.5 V
t
PHZ
tPZH
tPLZ
tPZL
0.2 V
0.2 V
0.2 V
0.2 V
0.4 V
2.4 V
1.5 V
E1
(1)
E1
(2)
V
OH
V
OL
TO OUTPUT
C
L
OF DEVICE
UNDER TEST
C
L
includes test-fixture and probe capacitance.
TO OUTPUT
OF DEVICE
UNDER TEST
C
L
500
W
1.5 V
C
L
includes test-fixture and probe capacitance.
TB3R1, TB3R2
SLLS587B NOVEMBER 2003 REVISED MAY 2004
TYPICAL CHARACTERISTICS (continued)
A.
E2 = 1 while E1 changes states.
B.
E1 = 0 while E2 changes states.
Figure 3. Receiver Enable and Disable Timing
Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the data
transmission driver devices are measured with the following output load circuits.
Figure 4. Receiver Propagation Delay Time and Enable Time (t
PZH
, t
PZL
) Test Circuit
Figure 5. Receiver Disable Time (t
PHZ
, t
PLZ
) Test Circuit
6
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1
2
3
4
5
-50
0
50
100
150
Max
Nom
Min
- Low-to-High Propagation Delay - ns
t PLH
T
A
- Free-Air Temperature -
5
C
V
CC
= 3.3 V
1
2
3
4
5
-50
0
50
100
150
- High to Low Propagation Delay - ns
t
PHL
V
CC
= 3.3 V
Nom
Min
Max
T
A
- Free-Air Temperature -
5
C
15
20
25
30
35
-50
0
50
100
150
T
A
- Free-Air Temperature -
5
C
I CC
- Supply Current - mA
I
CC
max at V
CC
= 3.6 V
I
CC
Typical at V
CC
= 3.3 V
0
0.5
1
1.5
2
2.5
3
3.5
-50
0
50
100
150
V
CC
= 3.3 V
V
OH
min
VOL max
- Output V
oltage - V
V
O
T
A
- Free-Air Temperature -
C
TB3R1, TB3R2
SLLS587B NOVEMBER 2003 REVISED MAY 2004
TYPICAL CHARACTERISTICS (continued)
LOW-TO-HIGH PROPAGATION DELAY
HIGH-TO-LOW PROPAGATION DELAY
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
Figure 6.
Figure 7.
MINIMUM V
OH
AND MAXIMUM V
OL
TYPICAL AND MAXIMUM I
CC
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
Figure 8.
Figure 9.
7
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APPLICATION INFORMATION
Power Dissipation
V
Sn
I
Sn
(1)
(V
Ln
I
Ln
)
(2)
T
J
+
T
A
)
P
D
q
JA
(3)
T
J
+
T
A
)
P
D
q
JA(S)
(4)
q
JA(S)
+
q
JC
)q
CA
q
JB
)q
BA
q
JC
)q
CA
)q
JB
)q
BA
(5)
40
60
80
100
120
140
0
100
200
300
400
500
D, Low-K
DW, Low-K
D, High-K
DW, High-K
Thermal Impedance - C/W
Air Flow - LFM
TB3R1, TB3R2
SLLS587B NOVEMBER 2003 REVISED MAY 2004
Note that
JA
is highly dependent on the PCB on
which the device is mounted, and on the airflow over
The power dissipation rating, often listed as the
the
device
and
PCB.
JEDEC/EIA
has
defined
package dissipation rating, is a function of the ambi-
standardized test conditions for measuring
JA
. Two
ent temperature, T
A
, and the airflow around the
commonly used conditions are the low-K and the
device. This rating correlates with the device's maxi-
high-K
boards,
covered
by
EIA/JESD51-3
and
mum junction temperature, sometimes listed in the
EIA/JESD51-7 respectively. Figure 10 shows the
absolute maximum ratings tables. The maximum
low-K and high-K values of
JA
versus air flow for this
junction temperature accounts for the processes and
device and its package options.
materials used to fabricate and package the device,
in addition to the desired life expectancy.
The standardized
JA
values may not accurately
represent the conditions under which the device is
There are two common approaches to estimating the
used. This can be due to adjacent devices acting as
internal die junction temperature, T
J
. In both of these
heat sources or heat sinks, to nonuniform airflow, or
methods, the device internal power dissipation P
D
to the system PCB having significantly different ther-
needs to be calculated This is done by totaling the
mal characteristics than the standardized test PCBs.
supply power(s) to arrive at the system power
The second method of system thermal analysis is
dissispation:
more accurate. This calculation uses the power
dissipation and ambient temperature, along with two
device and two system-level parameters:
and then subtracting the total power dissipation of the
JC
, the junction-to-case thermal resistance, in
external load(s):
degrees Celsius per watt
JB
, the junction-to-board thermal resistance, in
degrees Celsius per watt
The first T
J
calculation uses the power dissipation
CA
, the case-to-ambient thermal resistance, in
and ambient temperature, along with one parameter:
degrees Celsius per watt
JA
, the junction-to-ambient thermal resistance, in
BA
, the board-to-ambient thermal resistance, in
degrees Celsius per watt.
degrees Celsius per watt.
The product of P
D
and
JA
is the junction temperature
In this analysis, there are two parallel paths, one
rise above the ambient temperature. Therefore:
through the case (package) to the ambient, and
another through the device to the PCB to the ambi-
ent. The system-level junction-to-ambient thermal im-
pedance,
JA(S)
, is the equivalent parallel impedance
of the two parallel paths:
where
The device parameters
JC
and
JB
account for the
internal structure of the device. The system-level
parameters
CA
and
BA
take into account details of
the PCB construction, adjacent electrical and mech-
anical components, and the environmental conditions
including airflow. Finite element (FE), finite difference
(FD), or computational fluid dynamics (CFD) pro-
grams can determine
CA
and
BA
. Details on using
these programs are beyond the scope of this data
sheet, but are available from the software manufac-
turers.
Figure 10. Thermal Impedance vs Air Flow
8
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
TB3R1D
ACTIVE
SOIC
D
16
40
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1YEAR/
Level-1-220C-UNLIM
TB3R1DR
ACTIVE
SOIC
D
16
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1YEAR/
Level-1-220C-UNLIM
TB3R2D
ACTIVE
SOIC
D
16
40
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1YEAR/
Level-1-220C-UNLIM
TB3R2DR
ACTIVE
SOIC
D
16
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1YEAR/
Level-1-220C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check
http://www.ti.com/productcontent
for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2005
Addendum-Page 1
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
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product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright
2005, Texas Instruments Incorporated
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