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FEATURES
DESCRIPTION
APPLICATIONS
PIN ASSIGNMENTS
AI
AO
BO
CO
DO
AI
AI
BI
BI
C1
C1
D1
D1
D1
E2
E1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AI
AI
AO
E1
BO
BI
BI
GND
VCC
DI
DI
DO
E2
CO
CI
CI
D PACKAGE
(TOP VIEW)
ENABLE TRUTH TABLE
TB5R1, TB5R2
SLLS588B NOVEMBER 2003 REVISED MAY 2004
QUAD DIFFERENTIAL PECL RECEIVERS
Functional Replacements for the Agere
These quad differential receivers accept digital data
BRF1A, BRF2A, BRS2A, and BRS2B
over balanced transmission lines. They translate
differential input logic levels to TTL output logic
Pin Equivalent to General Trade 26LS32
levels.
High Input Impedance Approximately 8 k
The TB5R1 is a pin- and function-compatible replace-
4-ns Maximum Propagation Delay
ment for the Agere systems BRF1A and BRF2A; it
TB5R1 Provides 50-mV Hysteresis
includes 3-kV HBM and 2-kV CDM ESD protection.
TB5R2 With -125-mV Threshold Offset for
The TB5R2 is a pin- and function-compatible replace-
Preferred State Output
ment for the Agere systems BRS2A and BRS2B and
-1.1-V to 7.1-V Common Mode Range
incorporates a 125-mV receiver input offset, preferred
state output, 3-kV HBM and 2-kV CDM ESD protec-
Single 5-V
10% Supply
tion. The TB5R2 preferred state feature places the
Slew Rate Limited (1 ns min 80% to 20%)
high state when the inputs are open, shorted to
TB5R2 Output Defaults to Logic 1 When In-
ground, or shorted to the power supply.
puts Left Open or Shorted to V
CC
or GND
The power-down loading characteristics of the re-
ESD Protection HBM > 3 kV, CDM > 2 kV
ceiver input circuit are approximately 8 k
relative to
Operating Temperature Range: -40
C to 85
C
the power supplies; hence they do not load the
transmission line when the circuit is powered down.
Available in Gull-Wing SOIC (JEDEC MS-013,
DW) and SOIC (D) Package
The packaging for these differential line receivers
include a 16-pin gull wing SOIC (DW) and SOIC (D).
The enable inputs of this device include internal
Digital Data or Clock Transmission Over Bal-
pullup resistors of approximately 40 k
that are
anced Lines
connected to V
CC
to ensure a logical high level input
if the inputs are open circuited.
FUNCTIONAL BLOCK DIAGRAM
E1
E2
CONDITION
0
0
Active
1
0
Active
0
1
Disabled
1
1
Active
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 20032004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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POWER DISSIPATION RATINGS
ABSOLUTE MAXIMUM RATINGS
TB5R1, TB5R2
SLLS588B NOVEMBER 2003 REVISED MAY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER
PART MARKING
Package
LEAD FINISH
STATUS
TB5R1DW
TB5R1
Gull-Wing SOIC
NiPdAu
Production
TB5R1D
TB5R1
SOIC
NiPdAu
Production
TB5R2DW
TB5R2
Gull-Wing SOIC
NiPdAu
Production
TB5R2D
TB5R2
SOIC
NiPdAu
Production
TB5R1LDW
TB5R1
Gull-Wing SOIC
SnPb
Production
TB5R1LD
TB5R1
SOIC
SnPb
Production
TB5R2LDW
TB5R2
Gull-Wing SOIC
SnPb
Production
TB5R2LD
TB5R2
SOIC
SnPb
Production
THERMAL RESIST-
CIRCUIT BOARD
POWER RATINGT
A
ANCE,JUNCTION-TO-
DERATINGFACT
POWER RATINGT
A
=
PACKAGE
MODEL
25
C
AMBIENTWITH NO AIR
OR
(1)
T
A
25
C
85
C
FLOW
Low-K
(2)
763 mW
131.1
C/W
7.6 mW/
C
305 mW
D
High-K
(3)
1190 mW
84.1
C/W
11.9 mW/
C
475 mW
Low-K
(2)
831 mW
120.3
C/W
8.3 mW/
C
332 mW
DW
High-K
(3)
1240 mW
80.8
C/W
12.4 mW/
C
494 mW
(1)
This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no air flow.
(2)
In accordance with the low-K thermal metric definitions of EIA/JESD51-3.
(3)
In accordance with the high-K thermal metric definitions of EIA/JESD51-7.
THERMAL CHARACTERISTICS
PARAMETER
PACKAGE
VALUE
UNIT
D
47.5
C/W
Junction-to-Board
JB
Thermal Resistance
DW
53.7
C/W
D
44.2
C/W
Junction-to-Case
JC
Thermal Resistance
DW
47.1
C/W
over operating free-air temperature range unless otherwise noted
(1)
UNIT
Supply voltage, V
CC
0 V to 6 V
Magnitude of differential bus (input) voltage, |V
AI
- V|, |V
BI
- V|, |V
CI
- V|, |V
DI
- V|
8.4 V
Human Body Model
(2)
All pins
3 kV
ESD
Charged-Device Model
(3)
All pins
2 kV
Continuous power dissipation
See Dissipation Rating Table
Storage temperature, T
stg
-65
C to 150
C
(1)
Stresses beyond those listed under,, absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(3)
Tested in accordance with JEDEC Standard 22, Test Method C101.
2
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RECOMMENDED OPERATING CONDITIONS
DEVICE ELECTRICAL CHARACTERISTICS
RECEIVER ELECTRICAL CHARACTERISTICS
TB5R1, TB5R2
SLLS588B NOVEMBER 2003 REVISED MAY 2004
MIN
Nom
MAX UNIT
Supply voltage, V
CC
4.5
5
5.5
V
Bus pin input voltage, V
AI
, V, V
BI
, V, V
CI
, V, V
DI
, V
-1.2
(1)
7.2
V
Magnitude of differential input voltage, |V
AI
- V|, |V
BI
- V|, |V
CI
- V|, |V
DI
- V|
0.1
6
V
Operating free-air temperature, T
A
-40
85
C
(1)
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet, unless
otherwise noted.
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Outputs disabled
40
mA
I
CC
Supply current
(1)
Outputs enabled
38
mA
(1)
Current is dc power draw as measured through GND pin and does not include power delivered to load.
over operating free-air temperature range unless otherwise noted
parameter
test conditions
min typ
max
unit
V
OL
Output low voltage
V
CC
= 4.5 V,
I
OL
= 8 mA
0.4
V
V
OH
Output high voltage
V
CC
= 4.5 V,
I
OH
= -400 A
2.4
V
V
IL
Low level enable input voltage
(1)
V
CC
= 5.5 V
0.8
V
V
IH
High level enable input voltage
(1)
V
CC
= 5.5 V
2
V
V
IK
Enable input clamp voltage
V
CC
= 4.5 V,
I
I
= -5 mA
-1
(2)
V
TB5R1
100
mV
V
TH+
Positive-going differential input threshold voltage
(1)
, (V
xl
- V)
x = A, B, C, or D
TB5R2
(3)
-50
mV
TB5R1
-100
(2)
mV
V
TH-
Negative-going differential input threshold voltage
(1)
, (V
xl
- V)
x = A, B, C, or D
TB5R2
(3)
-200
(2)
mV
V
HYST
Differential input threshold voltage hysteresis, (V
TH+
- V
TH_
)
TB5R1
50
mV
I
OZL
V
O
= 0.4 V
-20
(2)
A
Output off-state current, (High-Z)
V
CC
= 5.5 V
I
OZH
V
O
= 2.4 V
20
A
I
OS
Output short circuit current
(4)
V
CC
= 5.5 V
-100
(2)
mA
I
IL
Enable input low current
V
CC
= 5.5 V,
V
IN
= 0.4 V
-400
(2)
A
Enable input high current
V
IN
= 2.7 V
20
A
I
IH
V
CC
= 5.5 V
Enable input reverse current
V
IN
= 5.5 V
100
A
II
L
Differential input low current
V
CC
= 5.5V,
V
IN
= -1.2 V
-2
(2)
mA
I
IH
Differential input high current
V
CC
= 5.5V,
V
IN
= 7.2 V
1
mA
R
O
Output resistance
20
(1)
The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment.
(2)
This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original
Agere data sheet.
(3)
Outputs of unused receivers assume a logic 1 level when the inputs are left open. (It is recomended that all unused positive inputs be
tied to the positive power supply. No external series resistor is required.)
(4)
Test must be performed one lead at a time to prevent damage to the device.
3
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SWITCHING CHARACTERISTICS
TB5R1, TB5R2
SLLS588B NOVEMBER 2003 REVISED MAY 2004
over operating free-air temperature range unless otherwise noted
parameter
test conditions
min
typ
max
unit
t
PLH
Propagation delay time, low-to-high-level output
2.5
4
C
L
= 0 pF
(1)
, See Figure 2 and Figure 4
ns
t
PHL
Propagation delay time, high-to-low-level output
2.5
4
t
PLH
Propagation delay time, low-to-high-level output
3
5
C
L
= 15 pF, See Figure 2 and Figure 4
ns
t
PHL
Propagation delay time, high-to-low-level output
3
5
Output disable time, high-level-to-high-impedance out-
t
PHZ
4.1
12
ns
put
(2)
C
L
= 5 pF, See Figure 3 and Figure 5
t
PLZ
Output disable time, low-level-to-high-impedance output
(2)
2.8
12
ns
C
L
= 10 pF, See Figure 2 and Figure 4
0.7
ns
t
skew1
Pulse width distortion, |t
PHL
- t
PLH
|
C
L
= 150 pF, See Figure 2 and Figure 4
4
ns
C
L
= 10 pF, T
A
= 75
C, See Figure 2 and
0.8
1.4
ns
Figure 4
t
skew1p-
Part-to-part output waveform skew
(3)
p
C
L
= 10 pF, T
A
= -40
C to 85
C, See
1.5
ns
Figure 2 and Figure 4
t
skew
Same part output waveform skew
(3)
C
L
= 10 pF, See Figure 2 and Figure 4
0.3
ns
Output enable time, high-impedance-to-high-level out-
t
PZH
5
12
ns
put
(4)
C
L
= 10 pF, See Figure 3 and Figure 4
t
PZL
Output enable time, high-impedance-to-low-level output
(4)
4
12
ns
t
TLH
Rise time (20%-80%)
1
3.5
ns
C
L
= 10 pF, See Figure 2 and Figure 4
t
THL
Fall time (80%-20%)
1
3.5
ns
(1)
The propagation delay values with a 0 pF load are based on design and simulation.
(2)
See Table 1.
(3)
Output waveform skews are when devices operate with the same supply voltage at the same temperature and have the same packages
and the same test circuits.
(4)
See Table 1.
4
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TYPICAL CHARACTERISTICS
0
2
4
6
8
10
0
50
100
150
200
t pd
- Propagation Delay T
ime - ns
C
L
- Load Capacitance - pF
t
PLH
t
PHL
OUTPUT
3.7 V
2.7 V
3.2 V
VOH
V OL
1.5 V
tTHL
tPHL
tPLH
tTLH
20%
80%
20%
80%
INPUT
INPUT
TB5R1, TB5R2
SLLS588B NOVEMBER 2003 REVISED MAY 2004
TYPICAL PROPAGATION DELAY
vs
LOAD CAPACITANCE
A.
NOTE
:
This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The
total delay is the sum of the delay due to external capacitance and the intrinsic delay of the device. Intrinsic delay is
listed in the table above as the 0 pF load condition. The incremental increase in delay between the 0 pF load
condition and the actual total load capacitance represents the extrinsic, or external delay contributed by the load.
Figure 1. Typical Propagation Delay
vs
Load Capacitance at 25
C
Figure 2. Receiver Propagation Delay Times
5
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OUTPUT
2.4 V
0.4 V
1.5 V
t
PHZ
tPZH
tPLZ
tPZL
0.2 V
0.2 V
0.2 V
0.2 V
0.4 V
2.4 V
1.5 V
E1
(1)
E1
(2)
V
OH
V
OL
TO OUTPUT
OF DEVICE
UNDER TEST
5 V
5 k
DIODES TYPE
458E, 1N4148,
OR EQUIVALENT
2 k
C
L
C
L
includes test-fixture and probe capacitance.
TO OUTPUT
OF DEVICE
UNDER TEST
C
L
500
W
1.5 V
C
L
includes test-fixture and probe capacitance.
TB5R1, TB5R2
SLLS588B NOVEMBER 2003 REVISED MAY 2004
TYPICAL CHARACTERISTICS (continued)
A.
E2 = 1 while E1 changes states.
B.
E1 = 0 while E2 changes states.
Figure 3. Receiver Enable and Disable Timing
Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the data
transmission driver devices are measured with the following output load circuits.
Figure 4. Receiver Propagation Delay Time and Enable Time (t
PZH
, t
PZL
) Test Circuit
Figure 5. Receiver Disable Time (t
PHZ
, t
PLZ
) Test Circuit
6
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Max
2
3
4
5
6
-50
0
50
100
150
Nom
Min
- Low-to-High Propagation Delay - ns
t PLH
T
A
- Free-Air Temperature -
5
C
V
CC
= 5 V
2
3
4
5
6
-50
0
50
100
150
- High-to-Low Propagation Delay - ns
t
PHL
V
CC
= 5 V
Nom
Min
Max
T
A
- Free-Air Temperature -
5
C
15
20
25
30
35
40
45
-50
0
50
100
150
T
A
- Free-Air Temperature -
5
C
I CC
- Supply Current - mA
I
CC
max at V
CC
= 5.5 V
I
CC
Typical at V
CC
= 5 V
0
0.5
1
1.5
2
2.5
3
3.5
4
-50
0
50
100
150
V
CC
= 4.5 V
V
OH
min
VOL min
- Output V
oltage - V
V
O
T
A
- Free-Air Temperature -
C
TB5R1, TB5R2
SLLS588B NOVEMBER 2003 REVISED MAY 2004
TYPICAL CHARACTERISTICS (continued)
LOW-TO-HIGH PROPAGATION DELAY
HIGH-TO-LOW PROPAGATION DELAY
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
Figure 6.
Figure 7.
MINIMUM V
OH
AND MAXIMUM V
OL
TYPICAL AND MAXIMUM I
CC
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
Figure 8.
Figure 9.
7
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APPLICATION INFORMATION
Power Dissipation
V
Sn
I
Sn
(1)
(V
Ln
I
Ln
)
(2)
T
J
+
T
A
)
P
D
q
JA
(3)
T
J
+
T
A
)
P
D
q
JA(S)
(4)
q
JA(S)
+
q
JC
)q
CA
q
JB
)q
BA
q
JC
)q
CA
)q
JB
)q
BA
(5)
40
60
80
100
120
140
0
100
200
300
400
500
T
h
e
r
m
a
l
I
m
p
e
d
a
n
c
e
-
C
/
W
D, Low-K
DW, Low-K
DW, High-K
D, High-K
TB5R1, TB5R2
SLLS588B NOVEMBER 2003 REVISED MAY 2004
Note that
JA
is highly dependent on the PCB on
which the device is mounted and on the airflow over
The power dissipation rating, often listed as the
the
device
and
PCB.
JEDEC/EIA
has
defined
package dissipation rating, is a function of the ambi-
standardized test conditions for measuring
JA
. Two
ent temperature, T
A
, and the airflow around the
commonly used conditions are the low-K and the
device. This rating correlates with the device's maxi-
high-K
boards,
covered
by
EIA/JESD51-3
and
mum junction temperature, sometimes listed in the
EIA/JESD51-7 respectively. Figure 10 shows the
absolute maximum ratings tables. The maximum
low-K and high-K values of
JA
versus air flow for this
junction temperature accounts for the processes and
device and its package options.
materials used to fabricate and package the device,
in addition to the desired life expectancy.
The standardized
JA
values may not accurately
represent the conditions under which the device is
There are two common approaches to estimating the
used. This can be due to adjacent devices acting as
internal die junction temperature, T
J
. In both of these
heat sources or heat sinks, to nonuniform airflow, or
methods, the device internal power dissipation P
D
to the system PCB having significantly different ther-
needs to be calculated This is done by totaling the
mal characteristics than the standardized test PCBs.
supply power(s) to arrive at the system power
The second method of system thermal analysis is
dissispation:
more accurate. This calculation uses the power
dissipation and ambient temperature, along with two
device and two system-level parameters:
and then subtracting the total power dissipation of the
JC
, the junction-to-case thermal resistance, in
external load(s):
degrees Celsius per watt
JB
, the junction-to-board thermal resistance, in
degrees Celsius per watt
The first T
J
calculation uses the power dissipation
CA
, the case-to-ambient thermal resistance, in
and ambient temperature, along with one parameter:
degrees Celsius per watt
JA
, the junction-to-ambient thermal resistance, in
BA
, the board-to-ambient thermal resistance, in
degrees Celsius per watt.
degrees Celsius per watt.
The product of P
D
and
JA
is the junction temperature
In this analysis, there are two parallel paths, one
rise above the ambient temperature. Therefore:
through the case (package) to the ambient, and
another through the device to the PCB to the ambi-
ent. The system-level junction-to-ambient thermal im-
pedance,
JA(S)
, is the equivalent parallel impedance
of the two parallel paths:
where
The device parameters
JC
and
JB
account for the
internal structure of the device. The system-level
parameters
CA
and
BA
take into account details of
the PCB construction, adjacent electrical and mech-
anical components, and the environmental conditions
including airflow. Finite element (FE), finite difference
(FD), or computational fluid dynamics (CFD) pro-
grams can determine
CA
and
BA
. Details on using
these programs are beyond the scope of this data
sheet, but are available from the software manufac-
Figure 10. Thermal Impedance vs Air Flow
turers.
8
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