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FEATURES
9
10
16
15
14
13
12
11
1
2
3
4
5
6
7
8
GND
V
CC
RO2
RO1
DI1
DI2
ED
ER
RI1
RI1
RI2
RI2
DO1
DO1
DO2
DO2
DW AND D PACKAGE
(TOP VIEW)
DESCRIPTION
DI1
DI2
ED
ER
RO2
RO1
RI1
RI1
RI2
RI2
DO1
DO1
DO2
DO2
ENABLE TRUTH TABLE
TB5T1
SLLS589B NOVEMBER 2003 REVISED MAY 2004
DUAL DIFFERENTIAL PECL DRIVER/RECEIVER
In circuits with termination resistors, the line remains
impedance- matched when the circuit is powered
Functional Replacement for the Agere BTF1A
down. The driver does not load the line when it is
Driver Features
powered down.
Third-State Logic Low Output
All devices are characterized for operation from -40
C
ESD Protection HBM > 3 kV, CDM > 2 kV
to 85
C.
No Line Loading when Vcc = 0
The logic inputs of this device include internal pull-up
Capable of Driving 50-
loads
resistors of approximately 40 k
that are connected
to V
CC
to ensure a logical high level input if the inputs
2.0-ns Maximum Propagation Delay
are open circuited.
0.2-ns Output Skew (typical)
PIN ASSIGNMENTS
Receiver Features
High-Input Impedance Approximately 8 k
4.0-ns Maximum Propagation Delay
50-mV Hysteresis
Slew Rate Limited (1 ns min 80% to 20%)
ESD Protection HBM > 3 kV, CDM > 2 kV
-1.1-V to 7.1-V Input Voltage Range
Common Device Features
Common Enable for Each Driver/Receiver
Pair
FUNCTIONAL BLOCK DIAGRAM
Operating Temperature Range: -40
C to
85
C
Single 5.0 V
10% Supply
Available in Gull-Wing SOIC (JEDEC
MS-013, DW) and SOIC (D) Package
The TB5T1 device is a dual differential driver/receiver
circuit that transmits and receives digital data over
balanced transmission lines. The dual drivers trans-
late input TTL logic levels to differential pseudo-ECL
output levels. The dual receivers convert differen-
tial-input logic levels to TTL output levels. Each driver
or receiver pair has its own common enable control
allowing serial data and a control clock to be
transmitted and received on a single integrated cir-
cuit. The TB5T1 requires the customer to supply
ED
ER
D1
D2
R1
R2
termination resistors on the circuit board.
0
0
Active
Active
Active
Active
The power-down loading characteristics of the re-
1
0
Disabled
Disabled
Active
Active
ceiver input circuit are approximately 8 k
relative to
0
1
Active
Active
Disabled
Disabled
the power supplies; hence, it does not load the
1
1
Disabled
Disabled
Disabled
Disabled
transmission line when the circuit is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 20032004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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POWER DISSIPATION RATINGS
THERMAL CHARACTERISTICS
TB5T1
SLLS589B NOVEMBER 2003 REVISED MAY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER
PART MARKING
PACKAGE
LEAD FINISH
STATUS
TB5T1DW
TB5T1
Gull-Wing SOIC
NiPdAu
Production
TB5T1D
TB5T1
SOIC
NiPdAu
Production
TB5T1LDW
TB5T1L
Gull-Wing SOIC
SnPb
Production
TB5T1LD
TB5T1L
SOIC
SnPb
Production
PACK-
CIRCUIT
POWER RATING
THERMAL RESISTANCE, JUNCTION-
DERATING FACTOR
(1)
POWER RATING
AGE
BOARD MODEL
T
A
25
C
TO-AMBIENT WITH NO AIR FLOW
T
A
25
C
T
A
= 85
C
Low-K
(2)
752 mW
132.8
C/W
7.5 mW/
C
301 mW
D
High-K
(3)
1160 mW
85.8
C/W
11.7 mW/
C
466 mW
Low-K
(2)
814 mW
122.7
C/W
8.2 mW/
C
325 mW
DW
High-K
(3)
1200 mW
83.1
C/W
12 mW/
C
481 mW
(1)
This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no airflow.
(2)
In accordance with the low-K thermal metric definitions of EIA/JESD51-3.
(3)
In accordance with the high-K thermal metric definitions of EIA/JESD51-7.
PARAMETER
PACKAGE
VALUE
UNIT
D
48.4
C/W
Junction-to-board
JB
thermal resistance
DW
55.2
C/W
D
45.1
C/W
Junction-to-case
JC
thermal resistance
DW
48.1
C/W
2
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
TB5T1
SLLS589B NOVEMBER 2003 REVISED MAY 2004
over operating free-air temperature range unless otherwise noted
(1)
UNIT
Supply voltage, V
CC
0 V to 6 V
Magnitude of differential bus (input) voltage, |V
RI1
- V
RI1
|, |V
RI2
- V
RI2
|
8.4 V
Human Body Model
(2)
All pins
3 kV
ESD
Charged-Device Model
(3)
All pins
2 kV
Continuous power dissipation
See Dissipation Rating Table
Storage temperature, T
stg
-65
C to 150
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(3)
Tested in accordance with JEDEC Standard 22, Test Method C101.
MIN
NOM
MAX
UNIT
Supply voltage, V
CC
4.5
5
5.5
V
Bus pin input voltage, V
RI1
, V
RI1
, V
RI2
, or V
RI2
-1.2
(1)
7.2
V
Magnitude of differential input voltage, |V
RI1
- V
RI1
|, |V
RI2
- V
RI2
|
0.1
6
V
Operating free-air temperature, T
A
-40
85
C
(1)
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet, unless
otherwise noted.
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Outputs disabled
40
mA
I
CC
Supply current
Outputs enabled
40
mA
3
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THIRD STATE
DRIVER ELECTRICAL CHARACTERISTICS
TB5T1
SLLS589B NOVEMBER 2003 REVISED MAY 2004
A TB5T1 driver produces pseudo-ECL levels and has a third state mode, which is different from a conventional
TTL device. When a TB5T1 driver is placed in the third state, the base of the output transistors are pulled low,
bringing the outputs below the active-low level of standard PECL devices. (For example: The TB5T1 low output
level is typically 2.7 V, while the third state noninverting output level is typically 1.2 V.) In a bidirectional,
multipoint bus application, the driver of one device, which is in its third state, can be back driven by another
driver on the bus whose voltage in the low state is lower than the 3-stated device. This could be due to
differences between individual driver's power supplies. In this case, the device in the third state controls the line,
thus clamping the line and reducing the signal swing. If the difference between the driver power supplies is small,
this consideration can be ignored. Again using the TB5T1 driver as an example, a typical supply voltage
difference between separate drivers of > 2 V can exist without significantly affecting the amplitude of the signal.
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
OH
Output high voltage
(1)
V
CC
- 1.8
V
CC
- 1.3
V
CC
- 0.8
V
V
OL
Output low voltage
(1)
V
OH
- 1.4
V
OH
- 1.2
V
OH
- 0.7
V
V
OD
Differential output voltage, |V
OH
- V
OL
|
0.7
1.1
1.4
V
V
OH
Output high voltage
(1)
V
CC
- 1.8
V
CC
- 1.3
V
CC
- 0.8
V
V
OL
Output low voltage
(1)
T
A
= 0
C to 85
C
V
OH
- 1.4
V
OH
- 1.1
V
OH
- 0.5
V
V
OD
Differential output voltage, |V
OH
- V
OL
|
0.5
1.1
1.4
V
V
OC(PP)
Peak-to-peak common-mode output voltage
C
L
= 5 pF, See Figure 7
230
600
mV
V
OZH
Third state output high voltage
(1)
DO1, DO2
1.4
1.8
2.2
V
CC
= 4.5 V
V
V
OZD
Third state diferential output voltage
(1)
V
DOn
- V
DOn
-0.47
(2)
-0.6
V
IL
Input low voltage
(3)
V
CC
= 5.5 V
0.8
V
V
IH
Input high voltage
V
CC
= 4.5 V
2
V
V
IK
Input clamp voltage
V
CC
= 4.5 V, I
I
= -5 mA
-1
(2)
V
V
CC
= 5.5 V, V
O
= 0 V
-250
(2)
mA
I
OS
Short-circuit output current
(4)
V
CC
= 5.5 V, V
OD
= 0 V
10
(2)
mA
I
IL
Input low current
V
CC
= 5.5 V, V
I
= 0.4 V
-400
(2)
A
I
IH
Input high current
V
CC
= 5.5 V, V
I
= 2.7 V
20
A
I
IH
Input reverse current
V
CC
= 5.5 V, V
I
= 5.5 V
100
A
C
IN
Input Capacitance
5
pF
(1)
Values are with terminations as per Figure 6.
(2)
This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original
Agere data sheet.
(3)
The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment.
(4)
Test must be performed one lead at a time to prevent damage to the device. No test circuit attached.
4
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RECEIVER ELECTRICAL CHARACTERISTICS
DRIVER SWITCHING CHARACTERISTICS
TB5T1
SLLS589B NOVEMBER 2003 REVISED MAY 2004
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
OL
Output low voltage
V
CC
= 4.5 V, I
OL
= 8.0 mA
0.4
V
V
OH
Output high voltage
V
CC
= 4.5 V, I
OH
= -400 A
2.4
V
V
IL
Enable input low voltage
(1)
V
CC
= 5.5 V
0.8
V
V
IH
Enable input high voltage
(1)
V
CC
= 4.5 V
2
V
V
IK
Enable input clamp voltage
V
CC
= 4.5 V, I
I
= -5 mA
-1
(2)
V
V
TH+
Positive-going differential input threshold voltage
(1)
|V
Rin
- V
Rin
|
n = 1 or 2
100
mV
V
TH-
Negative-going differential input threshold voltage
(1)
|V
Rin
- V
Rin
|
n = 1 or 2
-100
(2)
mV
V
HYST
Differential input threshold voltage hysteresis
(V
TH+
- V
TH-
)
50
mV
I
OZL
Off-state output low current (high Z)
V
CC
= 5.5 V, V
O
= 0.4 V
-20
(2)
A
I
OZH
Off-state output high current (high Z)
V
CC
= 5.5 V, V
O
= 2.4 V
20
A
I
OS
Short circuit output current
(3)
V
CC
= 5.5 V
-100
(2)
mA
I
IL
Enable input low current
V
CC
= 5.5 V, V
IN
= 0.4 V
-400
(2)
A
I
IH
Enable input high current
V
CC
= 5.5 V, V
IN
= 2.7 V
20
A
I
IH
Enable input reverse current
V
CC
= 5.5 V, V
IN
= 5.5 V
100
A
II
L
Differential input low current
V
CC
= 5.5V, V
IN
= -1.2 V
-2
(2)
mA
I
IH
Differential input high current
V
CC
= 5.5V, V
IN
= 7.2 V
1
mA
R
O
Output resistance
20
(1)
The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment.
(2)
This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original
Agere data sheet.
(3)
Test must be performed one lead at a time to prevent damage to the device.
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
P1
Propagation delay time, input high to output
(1)
C
L
= 5 pF, See Figure 2 and Figure 6
1.2
2
ns
t
P2
Propagation delay time, input low to output
(1)
1.2
2
ns
t
P
Capacitive delay
0.01
0.03
ns/pF
t
PHZ
Propagation delay time,
C
L
= 5 pF, See Figure 3 and Figure 6
8
12
ns
high-level-to-high-impedance output
t
PLZ
Propagation delay time,
7
12
ns
low-level-to-high-impedance output
t
PZH
Propagation delay time,
4
12
ns
high-impedance-to-high-level output
t
PZL
Propagation delay time,
5
12
ns
high-impedance-to-low-level output
t
skew1
Output skew, |t
P1
- t
P2
|
C
L
= 5 pF, See Figure 2 andFigure 6
0.15
0.3
ns
t
skew2
Output skew, |t
PHH
- t
PHL
|, |t
PLH
- t
PLL
|
0.15
1.1
ns
t
skew(pp)
Part-to-part skew
(2)
0.1
1
ns
t
skew
Output skew, difference between drivers
0.3
ns
t
TLH
Rise time (20%-80%)
0.7
2
ns
t
THL
Fall time (80%-20%)
0.7
2
ns
(1)
Parameters t
P1
and t
P2
are measured from the 1.5 V point of the input to the crossover point of the outputs (see Figure 2).
(2)
t
skew(pp)
is the magnitude of the difference in propagation delay times between any specified outputs of two devices when both devices
operate with the same supply voltage, at the same temperature, and have identical packages and test circuits.
5
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RECEIVER SWITCHING CHARACTERISTICS
0
2
4
6
8
10
0
50
100
150
200
t pd
- Propagation Delay T
ime - ns
C
L
- Load Capacitance - pF
t
PLH
t
PHL
TB5T1
SLLS589B NOVEMBER 2003 REVISED MAY 2004
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
PLH
Propagation delay time, low-to-high-level output
2.5
4
C
L
= 0 pF
(1)
, See Figure 4 and Figure 8
ns
t
PHL
Propagation delay time, high-to-low-level output
2.5
4
t
PLH
Propagation delay time, low-to-high-level output
3
5.5
C
L
= 15 pF, See Figure 4 and Figure 8
ns
t
PHL
Propagation delay time, high-to-low-level output
3
5.5
Propagation delay time,
t
PHZ
6
12
ns
high-level-to-high-impedance output
C
L
= 5 pF, See Figure 5 and Figure 9
Propagation delay time,
t
PLZ
6
12
ns
low-level-to-high-impedance output
Load capacitance (C
L
) = 10 pF, See
0.7
ns
Figure 4 and Figure 8
t
skew1
Pulse width distortion, |t
PHL
- t
PLH
|
Load capacitance (C
L
) = 150 pF, See
4
ns
Figure 4 and Figure 8
C
L
= 10 pF, T
A
= 75
C, See Figure 4
0.8
1.4
ns
and Figure 8
t
skew1p-p
Part-to-part output waveform skew
(2)
C
L
= 10 pF, T
A
= -40
C to 85
C, See
1.5
ns
Figure 4 and Figure 8
t
skew
Same part output waveform skew
(2)
C
L
= 10 pF, See Figure 4 and Figure 8
0.3
ns
Propagation delay time,
t
PZH
3
12
ns
high-impedance-to-high-level output
C
L
= 10 pF, See Figure 5 and Figure 8
Propagation delay time,
t
PZL
4
12
ns
high-impedance-to-low-level output
t
TLH
Rise time (20%--80%)
1
4
ns
C
L
= 10 pF, See Figure 5 and Figure 8
t
THL
Fall time (80%--20%)
1
4
ns
(1)
The propagation delay values with a 0 pF load are based on design and simulation.
(2)
Output waveform skews are when devices operate with the same supply voltage, same temperature, have the same packages and the
same test circuits.
NOTE: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total
delay is the sum of the delay due to external capacitance and the intrinsic delay of the device. Intrinsic delay is listed
in the table above as the 0 pF load condition. The incremental increase in delay between the 0 pF load condition and
the actual total load capacitance represents the extrinsic, or external delay contributed by the load.
Figure 1. Typical Propagation Delay vs Load Capacitance at 25
C
6
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PARAMETER MEASUREMENT INFORMATION
2.4 V
0.4 V
1.5 V
tTHL
tTLH
80%
20%
80%
20%
VOH
VOL
VOH
VOL
VOH
VOL
(VOH + VOL)/2
VOH
VOL
(VOH + VOL)/2
t
P1
t P2
tPHH
t PHL
t PLL
t PLH
INPUT
OUTPUTS
OUTPUT
OUTPUT
OUTPUT
ED
OUTPUT
OUTPUT
t
PHZ
t
PZH
2.4 V
1.5 V
0.4 V
V
OH
V
OL
+0.2 V
V
OL
V
OL
-0.1 V
OUTPUT -0.47 V
V
OL
V
OL
-0.1 V
t
PLZ
t
PZL
TB5T1
SLLS589B NOVEMBER 2003 REVISED MAY 2004
Figure 2. Driver Propagation Delay TImes
A.
NOTE
:
In the third state, OUTPUT is 0.47 V (minimum) more negative than OUTPUT.
Figure 3. Driver Enable and Disable Delay Times for a High Input
7
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OUTPUT
3.7 V
2.7 V
3.2 V
VOH
VOL
1.5 V
tTHL
tPHL
tPLH
tTLH
20%
80%
20%
80%
INPUT
INPUT
ER
OUTPUT
2.4 V
0.4 V
1.5 V
VOH
VOL
t
PHZ
tPZH
tPLZ
tPZL
0.2 V
0.2 V
0.2 V
0.2 V
100
W
200
W
200
W
C
L
C
L
C
L
includes test-fixture and probe capacitance.
TB5T1
SLLS589B NOVEMBER 2003 REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 4. Receiver Propagation Delay Times
Figure 5. Receiver Enable and Disable Timing
Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the data
transmission driver devices are measured with the following output load circuits.
Figure 6. Driver Test Circuit
8
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OUTPUTS
V
OC(PP)
V
OC
V
OH
V
OL
V
OC
50
W
200
W
200
W
C
L
C
L
C
P
=
2 pF
C
L
includes test-fixture and probe capacitance.
50
W
TO OUTPUT
OF DEVICE
UNDER TEST
5 V
5 k
DIODES TYPE
458E, 1N4148,
OR EQUIVALENT
2 k
C
L
TO OUTPUT
OF DEVICE
UNDER TEST
C
L
500
W
1.5 V
TB5T1
SLLS589B NOVEMBER 2003 REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION (continued)
A.
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
= 1 ns, pulse repetition
rate (PRR) = 0.25 Mbps, pulse width = 500
10 ns. C
P
includes the instrumentation and fixture capacitance within
0,06 m of the D.U.T. The measurement of V
OS(PP)
is made on test equipment with a -3 dB bandwidth of at least 1
GHz.
Figure 7. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Figure 8. Receiver Propagation Delay Time and Enable Time (t
PZH
, t
PZL
) Test Circuit
Figure 9. Receiver Disable Time (t
PHZ
, t
PLZ
) Test Circuit
9
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TYPICAL CHARACTERISTICS
-3
-2.5
-2
-1.5
-1
-0.5
0
-50
0
50
100
150
T
A
- Free-Air Temperature -
5
C
V
OH
OL
V
AND
EXTREMES FOR DRIVERS
V
CC
= 4.5 V to 5.5 V,
Load = 100
W
V
OH
Max
V
OH
Min
V
OL
Max
V
OL
Min
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
-50
-40
-30
-20
-10
0
V
OH
V
OL
V
oltage Characteristics - V
T
A
= 25
5
C
I
O
- Output Current - mA
0.8
1
1.2
1.4
1.6
-50
0
50
100
150
V
OD
-
D
i
f
f
e
r
e
n
t
i
a
l
O
u
t
p
u
t
V
o
l
t
a
g
e
-
V
TA - Free-Air T emperature -
C
V
CC
= 4.5 V to 5.5 V
Load = 100
W
V
DD
Max
V
DD
Nom
V
DD
Min
0
0.5
1
1.5
2
2.5
3
3.5
4
-50
0
50
100
150
V
CC
= 4.5 V
V
OH
Min
VOL Min
- Output V
oltage - V
V
O
T
A
- Free-Air Temperature -
C
TB5T1
SLLS589B NOVEMBER 2003 REVISED MAY 2004
OUTPUT-VOLTAGE
V
OL
AND V
OH
EXTREMES
vs
vs
OUTPUT CURRENT, DRIVER
FREE-AIR TEMPERATURE, DRIVER
Figure 10.
Figure 11.
DIFFERENTIAL OUTPUT VOLTAGE
MINIMUM V
OH
AND V
OL
vs
vs
FREE-AIR TEMPERATURE, DRIVER
FREE-AIR TEMPERATURE, RECEIVER
Figure 12.
Figure 13.
10
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Max
2
3
4
5
6
-50
0
50
100
150
Nom
Min
- Low-to-High Propagation Delay - ns
t PLH
T
A
- Free-Air Temperature -
5
C
V
CC
= 5 V
0
0.8
1
1.2
1.4
1.6
-50
0
50
100
150
Max Delay
Min Delay
V
CC
= 4.5 V to 5.5 V
Load = 100
W
t pd
- Propagation Delay T
ime - ns
T - Temperature For Driver-
5
C
2
3
4
5
6
-50
0
50
100
150
- High-to-Low Propagation Delay - ns
t
PHL
V
CC
= 5 V
Nom
Min
Max
T
A
- Free-Air Temperature -
5
C
TB5T1
SLLS589B NOVEMBER 2003 REVISED MAY 2004
TYPICAL CHARACTERISTICS (continued)
PROPAGATION DELAY TIME t
P1
or t
P2
LOW-TO-HIGH PROPAGATION DELAY
vs
vs
FREE-AIR TEMPERATURE, DRIVER
FREE-AIR TEMPERATURE, RECEIVER
Figure 14.
Figure 15.
HIGH-TO-LOW PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE, RECEIVER
Figure 16.
11
www.ti.com
APPLICATION INFORMATION
Power Dissipation
40
60
80
100
120
140
0
100
200
300
400
500
D, Low-K
DW, Low-K
D, High-K
DW, High-K
Thermal Impedance - C/W
Air Flow - LFM
V
Sn
I
Sn
(V
Ln
I
Ln
)
T
J
+
T
A
)
P
D
q
JA
T
J
+
T
A
)
P
D
q
JA(S)
q
JA(S)
+
q
JC
)q
CA
q
JB
)q
BA
q
JC
)q
CA
)q
JB
)q
BA
TB5T1
SLLS589B NOVEMBER 2003 REVISED MAY 2004
The power dissipation rating, often listed as the
package dissipation rating, is a function of the ambi-
ent temperature, T
A
, and the airflow around the
device. This rating correlates with the device's maxi-
mum junction temperature, sometimes listed in the
absolute maximum ratings tables. The maximum
junction temperature accounts for the processes and
materials used to fabricate and package the device,
in addition to the desired life expectancy.
There are two common approaches to estimating the
internal die junction temperature, T
J
. In both of these
methods, the device internal power dissipation P
D
needs to be calculated This is done by totaling the
supply power(s) to arrive at the system power
dissispation:
Figure 17. Thermal Impedance vs Air Flow
and then subtracting the total power dissipation of the
external load(s):
The standardized
JA
values may not accurately
represent the conditions under which the device is
used. This can be due to adjacent devices acting as
heat sources or heat sinks, to nonuniform airflow, or
The first T
J
calculation uses the power dissipation
to the system PCB having significantly different ther-
and ambient temperature, along with one parameter:
mal characteristics than the standardized test PCBs.
JA
, the junction-to-ambient thermal resistance, in
The second method of system thermal analysis is
degrees Celsius per watt.
more accurate. This calculation uses the power
The product of P
D
and
JA
is the junction temperature
dissipation and ambient temperature, along with two
rise above the ambient temperature. Therefore:
device and two system-level parameters:
JC
, the junction-to-case thermal resistance, in
degrees Celsius per watt
JB
, the junction-to-board thermal resistance, in
Note that
JA
is highly dependent on the PCB on
degrees Celsius per watt
which the device is mounted and on the airflow over
the
device
and
PCB.
JEDEC/EIA
has
defined
CA
, the case-to-ambient thermal resistance, in
standardized test conditions for measuring
JA
. Two
degrees Celsius per watt
commonly used conditions are the low-K and the
BA
, the board-to-ambient thermal resistance, in
high-K
boards,
covered
by
EIA/JESD51-3
and
degrees Celsius per watt.
EIA/JESD51-7 respectively. Figure 17 shows the
In this analysis, there are two parallel paths, one
low-K and high-K values of
JA
versus air flow for this
through the case (package) to the ambient, and
device and its package options.
another through the device to the PCB to the ambi-
ent. The system-level junction-to-ambient thermal im-
pedance,
JA(S)
, is the equivalent parallel impedance
of the two parallel paths:
where
12
www.ti.com
Load Circuits
Recommended Resistor Values:
For 5 V Nom Supplies, R
S
= 200
.
For 3.3 V Nom Supplies, R
S
= 75
.
R
S
R
S
R
T
= 100
Transmission Line
OUTPUT
INPUT
Recommended Resistor Values:
For 5 V Nom Supplies, R
T
= 200
, R
S
= 90
For 3.3 V Nom Supplies, R
T
= 100
, R
S
= 30
R
T
/2
Transmission Line
OUTPUT
INPUT
R
S
R
T
/2
Recommended Resistor Values:
For 5 V and 3.3 V Nom Supplies, R
T
= 100
,
V
T
= V
CC
- 2.55 V
R
T
/2
Transmission Line
OUTPUT
INPUT
V
T
R
T
/2
_
+
TB5T1
SLLS589B NOVEMBER 2003 REVISED MAY 2004
The test load circuits shown in Figure 6 and Figure 7 are based on a recommended pi type of load circuit shown
in Figure 18. The 100-
differential load resistor R
T
at the receiver provide proper termination for the
interconnecting transmission line, assuming it has a 100-
characteristic impedance. The two resistors R
S
to
ground at the driver end of the transmission line link provide dc current paths for the emitter follower output
transistors. The two resistors to ground normally should not be placed at the receiver end, as they shunt the
termination resistor, potentially creating an impedance mismatch with undesirable reflections.
Figure 18. A Recommended pi Load Circuit
Another common load circuit, a Y load, is shown in Figure 19. The receiver-end line termination of R
T
is provided
by the series combination of the two R
T/2
resistors, while the dc current path to ground is provided by the single
resistor R
S
. Recommended values, as a function of the nominal supply voltage range, are indicated in the figure.
Figure 19. A Recommended Y Load Circuit
An additional load circuit, similar to one commonly used with ECL and PECL, is shown in Figure 20.
Figure 20. A Recommended PECL-Style Load Circuit
An important feature of all of these recommended load circuits is that they ensure that both of the emitter follower
output transistors remain active (conducting current) at all times. When deviating from these recommended
values, it is important to make sure that the low-side output transistor does not turn off. Failure to do so
increases the t
skew2
and V
OC(PP)
values, increasing the potential for electromagnetic radiation.
13
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
TB5T1D
ACTIVE
SOIC
D
16
40
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1YEAR/
Level-1-220C-UNLIM
TB5T1DR
ACTIVE
SOIC
D
16
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1YEAR/
Level-1-220C-UNLIM
TB5T1DW
ACTIVE
SOIC
DW
16
40
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1YEAR/
Level-1-220C-UNLIM
TB5T1DWR
ACTIVE
SOIC
DW
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1YEAR/
Level-1-220C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
Addendum-Page 1
IMPORTANT NOTICE
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