TMS370Cx1x
8-BIT MICROCONTROLLER
SPNS012F MAY 1987 REVISED FEBRUARY 1997
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
D
CMOS / EEPROM/ EPROM Technologies on
a Single Device
Mask-ROM Devices for High-Volume
Production
One-Time-Programmable (OTP) EPROM
Devices for Low-Volume Production
Reprogrammable-EPROM Devices for
Prototyping Purposes
D
Internal System Memory Configurations
On-Chip Program Memory Versions
ROM: 2K, 4K, or 8K Bytes
EPROM: 8K Bytes
Data EEPROM: 256 Bytes
Static RAM: 128 or 256 Bytes Usable as
Registers
D
Flexible Operating Features
Low-Power Modes: STANDBY and HALT
Commercial, Industrial, and Automotive
Temperature Ranges
Clock Options
Divide-by-1 (2 MHz 5 MHz SYSCLK)
Phase-Locked Loop (PLL)
Divide-by-4 (0.5 MHz 5 MHz SYSCLK)
Supply Voltage (V
CC
) 5 V
10%
D
16-Bit General Purpose Timer
Software Configurable as
a 16-Bit Event Counter, or
a 16-Bit Pulse Accumulator, or
a 16-Bit Input Capture Functions, or
Two Compare Registers, or a
Self-Contained PWM Function
Software Programmable Input Polarity
8-Bit Prescaler, Providing a 24-Bit
Real-Time Timer
D
On-Chip 24-Bit Watchdog Timer
EPROM / OTP Devices:
EPROM '712A Standard Watchdog
EPROM '712B Hard Watchdog
Mask-ROM Devices: Hard Watchdog,
Simple Counter, or Standard Watchdog
D
Flexible Interrupt Handling
Two S oftware Programmable Interrupt
Levels
Global-and Individual-Interrupt Masking
Programmable Rising- or Falling-Edge
Detect
Individual Interrupt Vectors
D
Serial Peripheral Interface (SPI)
Variable-Length High-Speed Shift
Register
Synchronous Master / Slave Operation
D
TMS370 Series Compatibility
Register-to-Register Architecture
128 or 256 General-Purpose Registers
14 Powerful Addressing Modes
Instructions Upwardly Compatible With
All TMS370 Devices
D
CMOS / TTL Compatible I / O Pins / Packages
All Peripheral Function Pins Software
Configurable for Digital I / O
21 Bidirectional Pins, 1 Input Pin
28-Pin Plastic and Ceramic DIP, or
Leaded Chip Carrier (LCC) Packages
D
Workstation / PC-Based Development
System
C Compiler and C Source Debugger
Real-Time In-Circuit Emulation
Extensive Breakpoint / Trace Capability
Multi-Window User Interface
Microcontroller Programmer
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1997, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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6
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11
1
2
3
4
5
6
7
8
9
10
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12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D6
D7
A7
VCC
XTAL2 / CLKIN
XTAL1
A6
A5
A4
A3
A2
VSS
A1
A0
D3
RESET
D4
SPISOMI
SPICLK
SPISIMO
T1IC / CR
T1PWM
T1EVT
MC
INT3
INT2
INT1
D5
JD AND N PACKAGES
( TOP VIEW )
3 2 1 28 27
12 13
25
24
23
22
21
20
19
SPISOMI
SPICLK
SPISIMO
T1IC / CR
T1PWM
T1EVT
MC
XTAL2 / CLKIN
XTAL1
A6
A5
A4
A3
A2
4
26
14 15 16 1718
SS
A1
A0
D5
INT1
INT2
INT3
V
A7
D7
D6
D3
RESET
D4
FZ AND FN PACKAGES
( TOP VIEW )
CC
V
TMS370Cx1x
8-BIT MICROCONTROLLER
SPNS012F MAY 1987 REVISED FEBRUARY 1997
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Pin Descriptions
28 PINS
DIP and LCC
I / O
DESCRIPTION
NAME
NO.
A0
A1
A2
A3
A4
A5
A6
A7
14
13
11
10
9
8
7
3
I / O
Port A is a general-purpose bidirectional I / O port.
D3
D4
D5
D6
D7
28
26
15
1
2
I / O
Port D is a general-purpose bidirectional I / O port. D3 is also configurable as SYSCLK.
INT1
INT2
INT3
16
17
18
I
I / O
I / O
External interrupt (non-maskable or maskable) / general-purpose input pin
External maskable interrupt input / general-purpose bidirectional pin
External maskable interrupt input / general-purpose bidirectional pin
T1IC / CR
T1PWM
T1EVT
22
21
20
I / O
Timer1 input capture / counter reset input pin / general-purpose bidirectional pin
Timer1 PWM output pin / general-purpose bidirectional pin
Timer1 external event input pin / general-purpose bidirectional pin
SPISOMI
SPISIMO
SPICLK
25
23
24
I / O
SPI slave output pin, master input pin / general-purpose bidirectional pin
SPI slave input pin, master output pin / general-purpose bidirectional pin
SPI bidirectional serial clock pin / general-purpose bidirectional pin
RESET
27
I / O
System reset bidirectional pin; as input pin, RESET initializes the microcontroller; as open-drain output,
RESET indicates that an internal failure was detected by watchdog or oscillator fault circuit.
MC
19
I
Mode control input pin; enables EEPROM write protection override (WPO) mode, also EPROM VPP
XTAL2 / CLKIN
XTAL1
5
6
I
O
Internal oscillator crystal input / External clock source input
Internal oscillator output for crystal
VCC
4
Positive supply voltage
VSS
12
Ground reference
I = input, O = output
TMS370Cx1x
8-BIT MICROCONTROLLER
SPNS012F MAY 1987 REVISED FEBRUARY 1997
3
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
functional block diagram
Interrupts
T1IC/CR
T1EVT
T1PWM
V
System
Control
Clock Options:
Divide-By-4 or
Divide-By-1 (PLL)
RAM
128 or 256 Bytes
CPU
Port A
Port D
Timer 1
Watchdog
INT1
INT2
INT3
XTAL1
XTAL2/
CLKIN
MC
SPISOMI
SPISIMO
SPICLK
Serial
Peripheral
Interface
RESET
SS
VCC
Program Memory
ROM: 2K, 4K, or 8K Bytes
EPROM: 8K Bytes
Data EEPROM
0 or 256 Bytes
5
8
description
The TMS370C010, TMS370C012, TMS370C311, TMS370C310, TMS370C312, TMS370C712, and
SE370C712 devices are members of the TMS370 family of single-chip 8-bit microcontrollers. Unless otherwise
noted, the term TMS370Cx1x refers to these devices. The TMS370 family provides cost-effective real-time
system control through integration of advanced peripheral-function modules and various on-chip memory
configurations.
The TMS370Cx1x family of devices is implemented using high-performance silicon-gate CMOS EPROM and
EEPROM technologies. Low-operating power, wide-operating temperature range, and noise immunity of
CMOS technology coupled with the high performance and extensive on-chip peripheral functions make the
TMS370Cx1x devices attractive for system designs for automotive electronics, industrial motors, computer
peripheral controls, telecommunications, and consumer applications.
All TMS370Cx1x devices contain the following on-chip peripheral modules:
D
Serial peripheral interface (SPI)
D
One 24-bit general-purpose watchdog timer
D
One 16-bit general-purpose timer with an 8-bit prescaler
TMS370Cx1x
8-BIT MICROCONTROLLER
SPNS012F MAY 1987 REVISED FEBRUARY 1997
4
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
description (continued)
Table 1 provides a memory configuration overview of the TMS370Cx1x devices.
Table 1. Memory Configurations
DEVICE
PROGRAM MEMORY
(BYTES)
DATA MEMORY
(BYTES)
28 PIN PACKAGES
ROM
EPROM
RAM
EEPROM
TMS370C010A
4K
--
128
256
FN PLCC
N PDIP
TMS370C012A
8K
--
256
256
FN PLCC
N PDIP
TMS370C311A
2K
--
128
FN PLCC
N PDIP
TMS370C310A
4K
--
128
FN PLCC
N PDIP
TMS370C312A
8K
--
128
FN PLCC
N PDIP
TMS370C712A,
TMS370C712B
--
8K
256
256
FN PLCC
N PDIP
SE370C712A,
SE370C712B
--
8K
256
256
FZ CLCC
JD CDIP
System evaluators and development are for use only in prototype environment and their reliability has not been characterized.
The suffix letter (A or B) appended to the device names shown in the device column of Tables 1 and 2 indicates
the configuration of the device. ROM or EPROM devices have different configurations as indicated in Table 2.
ROM devices with the suffix letter A are configured through a programmable contact during manufacture.
Table 2. Suffix Letter Configuration
DEVICE
WATCHDOG TIMER
CLOCK
LOW-POWER MODE
EPROM A
Standard
Divide-by-4 (Standard oscillator)
Enabled
EPROM B
Hard
Divide-by-1 (PLL)
Enabled
Standard
ROM A
Hard
Divide-by-4 or Divide-by-1 (PLL)
Enabled or disabled
Simple
Refer to the "device numbering conventions" section for device nomenclature and to the "device part numbers" section for ordering.
The 2K bytes, 4K bytes, and 8K bytes of mask-programmable ROM in the associated TMS370Cx1x devices
are replaced in the TMS370C712 with 8K bytes of EPROM. All other available memory and on-chip peripherals
are identical, with the exception of no data EEPROM on the TMS370C311, TMS370C310, and TMS370C312
devices. The OTP (TMS370C712) device and reprogrammable (SE370C712) device are available.
TMS370C712 OTP devices are available in plastic packages. This microcontroller is effective to use for
immediate production updates for other members of the TMS370Cx1x family or for low volume production runs
when the mask charge or cycle time for the low-cost mask ROM devices is not practical.
The SE370C712 has a windowed ceramic package to allow reprogramming of the program EPROM memory
during the development / prototyping phase of design. The SE370C712 devices allow quick updates to
breadboards and prototype systems while iterating initial designs.
TMS370Cx1x
8-BIT MICROCONTROLLER
SPNS012F MAY 1987 REVISED FEBRUARY 1997
5
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
description (continued)
The TMS370Cx1x family provides two low-power modes (STANDBY and HALT) for applications where
low-power consumption is critical. Both modes stop all CPU activity (that is, no instructions are executed). In
the STANDBY mode, the internal oscillator and the general-purpose timer remain active. In the HALT mode,
all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both
low-power modes.
The TMS370Cx1x features advanced register-to-register architecture that allows direct arithmetic and logical
operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to
the contents of register 47 and store the result in register 47). The TMS370Cx1x family is fully
instruction-set-compatible, providing easy transition between members of the TMS370 8-bit microcontroller
family.
The SPI provides a convenient method of serial interaction for high-speed communications between simpler
shift register-type devices, such as display drivers, analog-to-digital (A / D) converters, PLL, input / output (I / O)
expansion, or other microcontrollers in the system.
The TMS370Cx1x family provides the system designer with economical, efficient solution to real-time control
applications. The TMS370 family extended development system (XDS
TM
) and compact development tool
(CDT
TM
) solve the challenge of efficiently developing the software and hardware required to design the
TMS370Cx1x into an ever-increasing number of complex applications. The application source code can be
written in assembly and C language, and the output code can be generated by the linker. The TMS370 family
XDS development tool communicates through a standard RS-232-C interface with an existing personal
computer. This allows the use of the PC's editors and software utilities already familiar to the designer. The
TMS370 family XDS emphasizes ease-of-use through extensive menus and screen windowing so that a system
designer can begin developing software with minimal training. Precise real-time, in-circuit emulation and
extensive symbolic debug and analysis tools ensure efficient software and hardware implementation as well
as reducing the time-to-market cycle.
The TMS370Cx1x family together with the TMS370 family XDS22, CDT370, design kit, starter kit, software
tools, the SE370C712 reprogrammable devices, comprehensive product documentation, and customer
support provide a complete solution to the needs of the system designer.
central processing unit (CPU)
The CPU on the TMS370Cx1x device is the high-performance 8-bit TMS370 CPU module. The 'x1x implements
an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The
complete 'x1x instruction map is shown in Table 17 in the TMS370Cx1x instruction set overview section.
The '370Cx1x CPU architecture provides the following components:
CPU registers:
D
A stack pointer that points to the last entry in the memory stack
D
A status register that monitors the operation of the instructions and contains the global interrupt-enable bits
D
A program counter (PC) that points to the memory location of the next instruction to be executed
XDS and CDT are trademarks of Texas Instruments Incorporated.
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