UC1525A/27A
UC2525A/27A
UC3525A/27A
Regulating Pulse Width Modulators
FEATURES
8 to 35V Operation
5.1V Reference Trimmed to
1%
100Hz to 500kHz Oscillator
Range
Separate Oscillator Sync
Terminal
Adjustable Deadtime Control
Internal Soft-Start
Pulse-by-Pulse Shutdown
Input Undervoltage Lockout
with Hysteresis
Latching PWM to Prevent
Multiple Pulses
Dual Source/Sink Output
Drivers
DESCRIPTION
The UC1525A/1527A series of pulse width modulator integrated circuits are de-
signed to offer improved performance and lowered external parts count when used
in designing all types of switching power supplies. The on-chip +5.1V reference is
trimmed to
1% and the input common-mode range of the error amplifier includes
the reference voltage, eliminating external resistors. A sync input to the oscillator
allows multiple units to be slaved or a single unit to be synchronized to an external
system clock. A single resistor between the C
T
and the discharge terminals pro-
vides a wide range of dead-time adjustment. These devices also feature built-in
soft-start circuitry with only an external timing capacitor required. A shutdown termi-
nal controls both the soft-start circuitry and the output stages, providing instantane-
ous turn off through the PWM latch with pulsed shutdown, as well as soft-start
recycle with longer shutdown commands. These functions are also controlled by
an undervoltage lockout which keeps the outputs off and the soft-start capacitor
discharged for sub-normal input voltages. This lockout circuitry includes approxi-
mately 500mV of hysteresis for jitter-free operation. Another feature of these PWM
circuits is a latch following the comparator. Once a PWM pulse has been termi-
nated for any reason, the outputs will remain off for the duration of the period. The
latch is reset with each clock pulse. The output stages are totem-pole designs ca-
pable of sourcing or sinking in excess of 200mA. The UC1525A output stage fea-
tures NOR logic, giving a LOW output for an OFF state. The UC1527A utilizes OR
logic which results in a HIGH output level when OFF.
BLOCK DIAGRAM
2/96
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, (+V
IN
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +40V
Collector Supply Voltage (V
C
) . . . . . . . . . . . . . . . . . . . . . . +40V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +V
IN
Output Current, Source or Sink . . . . . . . . . . . . . . . . . . . 500mA
Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Oscillator Charging Current . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Power Dissipation at T
A
= +25C (Note 2) . . . . . . . . . . 1000mW
Power Dissipation at T
C
= +25C (Note 2) . . . . . . . . . . 2000mW
Operating Junction Temperature . . . . . . . . . . . -55C to +150C
Storage Temperature Range . . . . . . . . . . . . . . -65C to +150C
Lead Temperature (Soldering, 10 seconds). . . . . . . . . . +300C
Note 1: Values beyond which damage may occur.
Note 2: Consult packaging Section of Databook for thermal
limitations and considerations of package.
UC1525A/27A
UC2525A/27A
UC3525A/27A
RECOMMENDED OPERATING CONDITIONS
(Note 3)
Input Voltage (+V
IN
) . . . . . . . . . . . . . . . . . . . . . . . . +8V to +35V
Collector Supply Voltage (V
C
) . . . . . . . . . . . . . . +4.5V to +35V
Sink/Source Load Current (steady state) . . . . . . . . 0 to 100mA
Sink/Source Load Current (peak) . . . . . . . . . . . . . . 0 to 400mA
Reference Load Current . . . . . . . . . . . . . . . . . . . . . . 0 to 20mA
Oscillator Frequency Range . . . . . . . . . . . . . . 100Hz to 400kHz
Oscillator Timing Resistor. . . . . . . . . . . . . . . . . . . 2k
to 150k
Oscillator Timing Capacitor. . . . . . . . . . . . . . . . .001
F to 0.1
F
Dead Time Resistor Range . . . . . . . . . . . . . . . . . . . . 0 to 500
Operating Ambient Temperature Range
UC1525A, UC1527A . . . . . . . . . . . . . . . . . . -55C to +125C
UC2525A, UC2527A . . . . . . . . . . . . . . . . . . . -25C to +85C
UC3525A, UC3527A . . . . . . . . . . . . . . . . . . . . . 0C to +70C
Note 3: Range over which the device is functional and
parameter limits are guaranteed.
CONNECTION DIAGRAMS
DIL-16 (TOP VIEW)
J or N Package
PLCC-20, LCC-20 (TOP VIEW)
Q, L Package
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
1
Inv. Input
2
N.I. Input
3
SYNC
4
OSC. output
5
N/C
6
C
T
7
R
T
8
Discharge
9
Softstart
10
N/C
11
Compensation 12
Shutdown
13
Output A
14
Ground
15
N/C
16
V
C
17
Output B
18
+V
IN
19
V
REF
20
2
ELECTRICAL CHARACTERISTICS:
PARAMETER
TEST CONDITIONS
UC1525A/UC2525A
UC1527A/UC2527A
UC3525A
UC3527A
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
Reference Section
Output Voltage
T
J
= 25C
5.05
5.10
5.15
5.00
5.10
5.20
V
Line Regulation
V
IN
= 8 to 35V
10
20
10
20
mV
Load Regulation
I
L
= 0 to 20mA
20
50
20
50
mV
Temperature Stability (Note 5)
Over Operating Range
20
50
20
50
Total Output Variation (Note 5)
Line, Load, and Temperature
5.00
5.20
4.95
5.25
V
Shorter Circuit Current
V
REF
= 0, T
J
= 25C
80
100
80
100
mA
Output Noise Voltage (Note 5)
10Hz
10kHz, T
J
=
25C
40
200
40
200
Vrms
Long Term Stability (Note 5)
T
J
= 125C
20
50
20
50
mV
Oscillator Section (Note 6)
Initial Accuracy (Notes 5 & 6)
T
J
= 25C
2
6
2
6
%
Voltage Stability (Notes 5 & 6)
V
IN
= 8 to 35V
0.3
1
1
2
%
Temperature Stability (Note 5)
Over Operating Range
3
6
3
6
%
Minimum Frequency
R
T
= 200k
, C
T
= 0.1
F
120
120
Hz
Maximum Frequency
R
T
= 2k
, C
T
= 470pF
400
400
kHz
Current Mirror
I
RT
= 2mA
1.7
2.0
2.2
1.7
2.0
2.2
mA
Clock Amplitude (Notes 5 & 6)
3.0
3.5
3.0
3.5
V
Clock Width (Notes 5 & 6)
T
J
= 25C
0.3
0.5
1.0
0.3
0.5
1.0
s
Sync Threshold
1.2
2.0
2.8
1.2
2.0
2.8
V
Sync Input Current
Sync Voltage = 3.5V
1.0
2.5
1.0
2.5
mA
Error Amplifier Section (V
CM
= 5.1V)
Input Offset Voltage
0.5
5
2
10
mV
Input Bias Current
1
10
1
10
A
Input Offset Current
1
1
A
DC Open Loop Gain
R
L
10M
60
75
60
75
dB
Gain-Bandwidth Product
(Note 5)
A
V
= 0dB, T
J
= 25C
1
2
1
2
MHz
DC Transconductance
(Notes 5 & 7)
T
J
= 25
C, 30k
R
L
1M
1.1
1.5
1.1
1.5
mS
Output Low Level
0.2
0.5
0.2
0.5
V
Output High Level
3.8
5.6
3.8
5.6
V
Common Mode Rejection
V
CM
= 1.5 to 5.2V
60
75
60
75
dB
Supply Voltage Rejection
V
IN
= 8 to 35V
50
60
50
60
dB
Note 5: These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
Note 6: Tested at f
OSC
= 40kHz (R
T
= 3.6k
, C
T
= 0.01
F, R
D
= 0
)
. Approximate oscillator frequency is defined by:
f
=
1
C
T
(
0.7R
T
+
3R
D
)
Note 7: DC transconductance (g
M
) relates to DC open-loop voltage gain (A
V
) according to the following equation: A
V
= g
M
R
L
where R
L
is the resistance from pin 9 to ground
.
.
The minimum g
M
specification is used to calculate minimum A
V
when the error amplifier output is loaded.
UC1525A/27A
UC2525A/27A
UC3525A/27A
+V
IN
= 20V, and over operating temperature, unless otherwise specified, T
A
= T
J
3
ELECTRICAL CHARACTERISTICS:
PARAMETER
TEST CONDITIONS
UC1525A/UC2525A
UC1527A/UC2527A
UC3525A
UC3527A
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
PWM Comparator
Minimum Duty-Cycle
0
0
%
Maximum Duty-Cycle
45
49
45
49
%
Input Threshold (Note 6)
Zero Duty-Cycle
0.7
0.9
0.7
0.9
V
Maximum Duty-Cycle
3.3
3.6
3.3
3.6
V
Input Bias Current (Note 5)
.05
1.0
.05
1.0
A
Shutdown Section
Soft Start Current
V
SD
= 0V, V
SS
= 0V
25
50
80
25
50
80
A
Soft Start Low Level
V
SD
= 2.5V
0.4
0.7
0.4
0.7
V
Shutdown Threshold
To outputs, V
SS
= 5.1V, T
J
= 25C
0.6
0.8
1.0
0.6
0.8
1.0
V
Shutdown Input Current
V
SD
= 2.5V
0.4
1.0
0.4
1.0
mA
Shutdown Delay (Note 5)
V
SD
= 2.5V, T
J
= 25C
0.2
0.5
0.2
0.5
s
Output Drivers (Each Output) (V
C
= 20V)
Output Low Level
I
SINK
= 20mA
0.2
0.4
0.2
0.4
V
I
SINK
= 100mA
1.0
2.0
1.0
2.0
V
Output High Level
I
SOURCE
= 20mA
18
19
18
19
V
I
SOURCE
= 100mA
17
18
17
18
V
Under-Voltage Lockout
V
COMP
and V
SS
= High
6
7
8
6
7
8
V
V
C
OFF Current (Note 7)
V
C
= 35V
200
200
A
Rise Time (Note 5)
C
L
= 1nF, T
J
= 25C
100
600
100
600
ns
Fall Time (Note 5)
C
L
= 1nF, T
J
= 25C
50
300
50
300
ns
Total Standby Current
Supply Current
V
IN
= 35V
14
20
14
20
mA
UC1525A/27A
UC2525A/27A
UC3525A/27A
+V
IN
= 20V, and over operating temperature, unless otherwise specified, T
A
= T
J
Note 5: These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
Note 6: Tested at f
OSC
= 40kHz (R
T
= 3.6k
, C
T
= 0.01
F, R
D
= 0
).
Note 7: Collector off-state quiescent current measured at pin 13 with outputs low for UC1525A and high for UC1527A.
4
PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS
UC1525A/27A
UC2525A/27A
UC3525A/27A
For single-ended supplies, the driver outputs are
grounded. The V
C
terminal is switched to ground by the
totem-pole source transistors on alternate oscillator cy-
cles.
In conventional push-pull bipolar designs, forward base
drive is controlled by R1-R3. Rapid turn-off times for the
power devices are achieved with speed-up capacitors
C1 and C2.
The low source impedance of the output drivers provides
rapid charging of power FET Input capacitance while
minimizing external components.
Low power transformers can be driven by the UC1525A.
Automatic reset occurs during dead time, when both
ends of the primary winding are switched to ground.
UC1525A Output Circuit
(1/2 Circuit Shown)
UC1525A Output Saturation Characteristics
5
PRINCIPLES OF OPERATION AND TYPICAL CHAR-
ACTERISTIC SHUTDOWN OPTIONS
(See Block Diagram)
Since both the compensation and soft-start terminals
(Pins 9 and 8) have current source pull-ups, either can
readily accept a pull-down signal which only has to sink a
maximum of 100
A to turn off the outputs. This is subject
to the added requirement of discharging whatever exter-
nal capacitance may be attached to these pins.
An alternate approach is the use of the shutdown circuitry
of Pin 10 which has been improved to enhance the avail-
able shutdown options. Activating this circuit by applying
a positive signal on Pin 10 performs two functions; the
PWM latch is immediately set providing the fastest turn-
off signal to the outputs; and a 150
A-current sink begins
to discharge the external soft-start capacitor. If the shut-
down command is short, the PWM signal is terminated
without significant discharge of the soft-start capacitor,
thus, allowing, for example, a convenient implementation
of pulse-by-pulse current limiting. Holding Pin 10 high for
a longer duration, however, will ultimately discharge this
external capacitor, recycling slow turn-on upon release.
Pin 10 should not be left floating as noise pickup could
conceivably interrupt normal operation.
UC1525A/27A
UC2525A/27A
UC3525A/27A
UC1525A Oscillator Schematic
Oscillator Charge Time
vs R
T
and C
T
Oscillator Discharge Time
vs R
D
and CT
6
UNITRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD.
MERRIMACK, NH 03054
TEL. (603) 424-2410
FAX (603) 424-3460
LAB TEST FIXTURE
UC1525A/27A
UC2525A/27A
UC3525A/27A
R
L
is impedance from pin 9 to ground. Values below
30k
will begin to limit the maximum duty cycle.
Maximum Value R
D
vs Minimum Value R
T
Error Amplifier Voltage Gain
and Phase vs Frequency
7
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