UC1706
UC2706
UC3706
Dual Output Driver
FEATURES
Dual, 1.5A Totem Pole Outputs
40nsec Rise and Fall into 1000pF
Parallel or Push-Pull Operation
Single-Ended to Push-Pull Conversion
High-Speed, Power MOSFET
Compatible
Low Cross-Conduction Current Spike
Analog, Latched Shutdown
Internal Deadband Inhibit Circuit
Low Quiescent Current
5 to 40V Operation
Thermal Shutdown Protection
16-Pin Dual-In-Line Package
20-Pin Surface Mount Package
DESCRIPTION
The UC1706 family of output drivers are made with a high-speed
Schottky process to interface between low-level control functions and
high-power switching devices - particularly power MOSFET's. These de-
vices implement three generalized functions as outlined below.
First: They accept a single-ended, low-current digital input of either polar-
ity and process it to activate a pair of high-current, totem pole outputs
which can source or sink up to 1.5A each.
Second: They provide an optional single-ended to push-pull conversion
through the use of an internal flip-flop driven by double-pulse-
suppression logic. With the flip-flop disabled, the outputs work in parallel
for 3.0A capability.
Third: Protection functions are also included for pulse-by-pulse current
limiting, automatic deadband control, and thermal shutdown.
These devices are available in a two-watt plastic "bat-wing" DIP for op-
eration over a 0C to 70C temperature range and, with reduced power,
in a hermetically sealed cerdip for -55C to +125C operation. Also avail-
able in surface mount Q and L packages.
BLOCK DIAGRAM
INV
N.I
OUT
H
L
H
L
H
H
L
L
L
H
L
L
OUT = INV and N.I.
OUT = INV or N.I.
TRUTH TABLE
application
INFO
available
SLUS200A - OCTOBER 1998 - REVISED APRIL 2001
2
UC1706
UC2706
UC3706
DIL-16, SOIC-16 (TOP VIEW)
J or N Package, DW Package
PLCC-20, LCC-20 (TOP VIEW)
Q, L Packages
ABSOLUTE MAXIMUM RATINGS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . N--Pkg . . . . . . . . . . . . . . . J--Pkg
Supply Voltage, V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . 40V . . . . . . . . . . . . . . . . . . 40V
Collector Supply Voltage, V
C
. . . . . . . . . . . . . . . . . . 40V . . . . . . . . . . . . . . . . . . 40V
Output Current (Each Output, Source or Sink)
Steady--State . . . . . . . . . . . . . . . . . . . . . . . . . .
500mA. . . . . . . . . . . . . . .
500mA
Peak Transient . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5A. . . . . . . . . . . . . . . . .
1.0A
Capacitive Discharge Energy . . . . . . . . . . . . . . . 20
J
. . . . . . . . . . . . . . . . . . . 15
J
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V . . . . . . . . . . . . . . . . . 5.5V
Analog Stop Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . V
IN
. . . . . . . . . . . . . . . . . . . . V
IN
Power Dissipation at T
A
= 25C (See Note) . . . . . . . 2W . . . . . . . . . . . . . . . . . . 1W
Power Dissipation at T (Leads/Case) = 25C . . . . . . 5W . . . . . . . . . . . . . . . . . . . 2
(See Note)
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . --55C to +125C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . --65C to +150C
Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . . . . . . . 300C
Note: All voltages are with respect to the four ground pins which must be connected
together. All currents are positive into, negative out of the specified trerminal. Consult
Packaging sections of the Databook for thermal limitations and considerations of package.
V
IN
INHIBIT REF
A INHIBIT
GROUND
GROUND
STOP NON-INV.
B OUTPUT
STOP INV.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INV. INPUT
B INHIBIT
V
C
A OUTPUT
FLIP/FLOP
N.I. INPUT
GROUND
GROUND
CONNECTION DIAGRAMS
Note: All four ground pins must be connected to a common
ground.
3
18
17
16
N/C
1
2
20 19
15
14
4
5
6
7
8
9
11
10
12 13
B INHIBIT
INV INPUT
A INHIBIT
INHIBIT REF
V
IN
GROUND
N/C
GROUND
B OUTPUT
N.I.INPUT
GROUND
N/C
GROUND
A OUTPUT
STOP INV.
STOP NON-INV.
N/C
FLIP/FLOP
V
C
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated, these specifications apply for T
A
= 55C to +125C for
the UC1706, 25C to +85C for the UC2706 and 0C to +70C for the UC3706; V
IN
= V
C
= 20V. T
A
= T
J
.
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
Supply Current
V
IN
= 40V
8
10
mA
V
C
Supply Current
V
C
= 40V, Outputs Low
4
5
mA
V
C
Leakage Current
V
IN
= 0, V
C
= 30V, No Load
.05
0.1
mA
Digital Input Low Level
0.8
V
Digital Input High Level
2.2
V
Input Current
V
I
= 0
0.6
1.0
mA
Input Leakage
V
I
= 5V
.05
0.1
mA
3
UC1706
UC2706
UC3706
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated, these specifications apply for T
A
= 55C to +125C for
the UC1706, 25C to +85C for the UC2706 and 0C to +70C for the UC3706; V
IN
= V
C
= 20V. T
A
= T
J
.
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Output High Sat., V
C
-V
O
I
O
= -50mA
2.0
V
Output Low Sat., V
O
I
O
= 50mA
0.4
V
I
O
= 500mA
2.5
V
Inhibit Threshold
V
REF
= 0.5V
0.4
0.6
V
V
REF
= 3.5V
3.3
3.7
V
Inhibit Input Current
V
REF
= 0
10
20
A
Analog Threshold
V
CM
= 0 to 15V, for the UC2706 and UC3706
100
130
160
mV
V
CM
= 0 to 15V, for the UC1706
80
130
160
mV
Input Bias Current
V
CM
= 0
10
20
A
Thermal Shutdown
155
C
TYPICAL SWITCHING CHARACTERISTICS:
V
IN
= V
C
= 20V, T
A
= 25C. Delays measured to 10% output change.
PARAMETERS
TEST CONDITIONS
OUTPUT C
L
=
UNITS
From Inv. Input to Output:
open
1.0
2.2
nF
Rise Time Delay
110
130
140
ns
10% to 90% Rise
20
40
60
ns
Fall Time Delay
80
90
110
ns
90% to 10% Fall
25
30
50
ns
From N. I. Input to Output:
Rise Time Delay
120
130
140
ns
10% to 90% Rise
20
40
60
ns
Fall Time Delay
100
120
130
ns
90% to 10% Fall
25
30
50
ns
V
C
Cross-Conduction Current Spike Duration Output Rise
25
ns
Output Fall
0
ns
Inhibit Delay
Inhibit Ref. = 1V, Inhibit Inv. = 0.5 to 1.5V
250
ns
Analog Shutdown Delay
Stop Non-Inv. = 0V, Stop Inv. = 0 to 0.5V
180
ns
CIRCUIT DESCRIPTION
Outputs
The totem-pole outputs have been designed to minimize
cross-conduction current spikes while maximizing fast,
high-current rise and fall times. Current limiting can be
done externally either at the outputs or at the common
V
C
pin. The output diodes included have slow recovery
and should be shunted with high-speed external diodes
when driving high-frequency inductive loads.
Flip/Flop
Grounding pin 7 activates the internal flip-flop to alter-
nate the two outputs. With pin 7 open, the two outputs
operate simultaneously and can be paralleled for higher
current operation. Since the flip-flop is triggered by the
digital input, an off-time of at last 200nsec must be pro-
vided to allow the flip/flop to change states. Note that the
circuit logic is configured such that the "OFF" state is de-
fined as the outputs low.
Digital Inputs
With both an inverting and non-inverting input available,
either active-high or active-low signals may be accepted.
These are true TTL compatible inputs--the threshold is
approximately 1.2V with no hysteresis; and external pull-
up resistors are not required.
Inhibit Circuit
Although it may have other uses, this circuit is included to
eliminate the need for deadband control when driving
relatively slow bipolar power transistors. A diode from
each inhibit input to the opposite power switch collector
will keep one output from turning-on until the other has
turned-off. The threshold is determined by the voltage on
pin 15 which can be set from 0.5 to 3.5V. When this cir-
cuit is not used, ground pin 15 and leave 1 and 16 open.
4
UC1706
UC2706
UC3706
D1, D2: UC3611 Schottky Diodes
Transformer Coupled MOSFET Drive Circuit
CIRCUIT DESCRIPTION (cont.)
Charge Pump Circuits
D1, D2; UC3611 Schottky Diodes
APPLICATIONS
Power MOSFET Drive Circuit
D1, D2; UC3611 Schottky Diodes
Power MOSFET Drive Circuit Using Negative Bias Voltage and
Level Shifting to Ground Referenced PWMs
Analog Shutdown
This circuit is included to get a latched shutdown as close
to the outputs as possible, from a time standpoint. With
an internal 130mV threshold, this comparator has a
common-mode range from ground to (V
IN
3V). When
not used, both inputs should be grounded. The time re-
quired for this circuit to latch is inversely proportional to
the amount of overdrive but reaches a minimum of
180nsec. As with the flip-flop, an input off-time of at least
200nsec is required to reset the latch between pulses.
Supply Voltage
With an internal 5V regulator, this circuit is optimized for
use with a 7 to 40V supply; however, with some slight re-
sponse time degradation, it can also be driven from 5V.
When V
IN
is low, the entire circuit is disabled and no cur-
rent is drawn from V
C
. When combined with a UC1840
PWM, the Driver Bias switch can be used to supply V
IN
to
the UC1706.
V
IN
switching should be fast as if V
C
is
high, undefined operation of the outputs may occur with
VI
N
less than 5V.
Thermal Considerations
Should the chip temperature reach approximately 155C,
a parallel, non--inverting input is activated driving both
outputs to the low state.
5
UC1706
UC2706
UC3706
APPLICATIONS (cont'd)
D1, D2: UC3611 Schottky Diodes
Transformer Coupled Push-Pull MOSFET Drive Circuit
D1, D2: UC3611 Schottky Diodes
Power Bipolar Drive Circuit
UC3706 Converts Single Output PWMs to High Current Push-Pull Configuration
UNITRODE CORPORATION
7 CONTINENTAL BLVD. MERRIMACK, NH 03054
TEL. (603) 424-2410 FAX (603) 424-3460
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its products to the specifications applicable at the time of sale in accordance with
TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary
to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except
those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
products or services might be or are used. TI's publication of information regarding any third party's products
or services does not constitute TI's approval, license, warranty or endorsement thereof.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation
or reproduction of this information with alteration voids all warranties provided for an associated TI product or
service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.
Resale of TI's products or services with
statements different from or beyond the parameters stated by TI for
that product or service voids all express and any implied warranties for the associated TI product or service,
is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.
Also see: Standard Terms and Conditions of Sale for Semiconductor Products. www.ti.com/sc/docs/stdterms.htm
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright
2001, Texas Instruments Incorporated
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its products to the specifications applicable at the time of sale in accordance with
TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary
to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except
those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
products or services might be or are used. TI's publication of information regarding any third party's products
or services does not constitute TI's approval, license, warranty or endorsement thereof.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation
or reproduction of this information with alteration voids all warranties provided for an associated TI product or
service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.
Resale of TI's products or services with
statements different from or beyond the parameters stated by TI for
that product or service voids all express and any implied warranties for the associated TI product or service,
is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.
Also see: Standard Terms and Conditions of Sale for Semiconductor Products. www.ti.com/sc/docs/stdterms.htm
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright
2001, Texas Instruments Incorporated
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