UC17131/2/3
UC27131/2/3
UC37131/2/3

SLUS340 - APRIL 1999

FEATURES

300mA Continuous Output Current

Low Side or High Side Switch
Configuration

8V to 65V Operation

Overload and Short Circuit Protection

Power Interruption Protection

+6V Regulated Voltage

2mA Quiescent Current

Programmable Overcurrent and
Power Interruption Protection

1% to 30% Programmable Input
Comparator Hysteresis (on UC37132)

Low and High Side Internal High
Current Clamps When Driving
Inductive Loads

Smart Power Switch

VREF

VCC

CSH

CSL

GND

PRE-REGULATOR

INPUT
COMPARATOR

1/2
VREF

HYST

LED

TURN-ON/OFF

AND

SHORT CIRCUIT

PROTECTION

OUT

72V

6V/8mA

CDEL

UC37132 BLOCK DIAGRAM

UDG-98026

DESCRIPTION

The UC37131, UC37132 and UC37133 are a family of smart power
switches which can drive resistive or inductive loads from the high side or
low side.

The UC37132 is available in 14 pin (DIP), 16 pin (SOIC), or 20 pin (CLCC)
packages and can accommodate both low side (load to VCC) or high side
(load to GND) configurations. The UC37131 and UC37133 are exclusively
for a low side or a high side configuration respectively and both are avail-
able in an 8 pin package. Both high side and low side configurations provide
high current switching with low saturation voltages which can drive resistive
or inductive loads.

The input to the switch is driven by a low voltage signal, typically 5V. Addi-
tionally, UC37132 features adjustable hysteresis. The output of the device
can switch a load between 8V and 65V. Output current capability is 300mA
continuous or 700mA peak.

The device also has inherent smart features that allow for programmable
turn-on delay in enabling the output following startup. The same capacitor
that specifies the turn-on delay is also used to program a VCC power inter-
ruption time. If VCC drops below a threshold for a time specified by this ca-
pacitor, the output is turned off and a new turn-on delay will be re-triggered.
Similarly, if high current persists longer than the response delay, the output
driver will operate in a very low duty cycle mode to protect the IC.

UC17131/2/3
UC27131/2/3
UC37131/2/3

CSH

VCC

GND

CDEL

LED

VREF

ABSOLUTE MAXIMUM RATINGS

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65V
LS HS (Clamped by internal circuitry) . . . . . . . . . . . . . . . 78V
CSH, LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65V
Output Current

Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400mA
Peak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900mA

Remaining Pin Voltages . . . . . . . . . . . . . . . . . . . . . 0.3V to 9V
Storage Temperature . . . . . . . . . . . . . . . . . . .

65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . 55°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C

Currents are positive into, negative out of the specified termi-
nal. Consult Packaging Section of Databook for thermal limita-
tions and considerations of packages.

PART

NUMBER

CONFIGURATIONS

PACKAGE

PIN COUNT

UCX7131

Low Side Only

UCX7132

Low Side or High Side

14, 16, 20

UCX7133

High Side Only

PRODUCT SELECTION TABLES

PART

NUMBER

TEMPERATURE

RANGE

AVAILABLE
PACKAGES

UC1713X

55°C to +125°C

J, L

UC2713X

40°C to +85°C

D, N

UC3713X

0°C to +70°C

D, N

HYST

N/C

VREF

CDEL

N/C

LED

GND

N/C

CSH

VCC

CSL

VCC

GND

CDEL

LED

VREF

HYST

N/C

VREF

CDEL

N/C

LED

N/C

GND

N/C

VCC

CSH

N/C

CSL

CONNECTION DIAGRAMS

SOIC-16 (Top View)
(for UCX7132)
D Package

N/C

20 19

12 13

CSH

CSL

N/C

GND

N/C

VCC

N/C

HYST

VREF

CDEL

N/C

LED

PLCC-20 (Top View)
(for UCX7132)
L Packages

DIL-14 (Top View)
(for UCX7132)
J, or N Packages

DIL-8, SOIC-8 (Top View)
(for UCX7131)
J, N, or D Packages

DIL-8, SOIC-8 (Top View)
(for UCX7133)
J, N, or D Packages

UC17131/2/3
UC27131/2/3
UC37131/2/3

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, CDEL = 10nF, VCC = 25V, CSL = GND, CSH = LS;

CSH

= 0.5

(Note 1); IN=0V (for OFF condition) and IN=5V (for ON condition); T

= T

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Reference

VREF

25°C

5.8

6.2

55°C to 125°C

5.6

6.4

Line Regulation

VCC = 8V to 64V

Load Regulation

0 < I

REF

< 8mA

Short Circuit Current

REF = 0V

Input Comparator

Turn-On Threshold Voltage

2.7

3.3

Input Bias Current

= 3.5V

Hysteresis

HYST

= GND (Internally for X31, X33)

0.775

0.9

1.025

HYST

= 96.67k for (X32)

Output: High Side (UCX7133: CSH = LS and CSL = GND Internally; See Fig. 2a)

Rise Time (Off to On)

LOAD

= 250

to GND

Fall Time (On to Off)

LOAD

= 250

to GND

Output Short Circuit

HS = 0.25

to GND

500

900

Voltage Clamp

LSHS

Saturation Voltage

25°C, R

LOAD

= 100

to GND

1.2

40°C, R

LOAD

= 100

to GND

1.3

55°C, R

LOAD

= 100

to GND

1.4

Leakage Current

Output: Low Side (UCX7131; CSH = VCC and CSL = HS Internally; See Fig. 2b)

Rise Time (On to Off)

LOAD

= 250

to VCC, R

CSL

= 0.5

Fall Time (Off to On)

LOAD

= 250

to VCC, R

CSL

= 0.5

Output Short Circuit

LS = 0.25

to VCC

500

700

900

Voltage Clamp

LSHS

Saturation Voltage

25°C, R

LOAD

= 100

to VCC, R

CSL

= 0.5

1.2

40°C, R

LOAD

= 100

to VCC, R

CSL

= 0.5

1.3

55°C, R

LOAD

= 100

to VCC, R

CSL

= 0.5

1.4

Leakage Current

VCC Fault Section

Output Turn-On Delay, t

D(ON)

Step VCC from 0V to 8V (See Fig. 3a)

9.5

13.5

Output Turn-Off Delay, t

D(OFF)

Pulse VCC from 25V to VCC Turn-Off
Threshold

300

500

700

VCC Turn-Off Threshold

Pulse VCC Low

6.5

7.5

CDEL Section

CDEL_MAX

5.8

FAULT_H

4.9

FAULT_L

1.0

Overcurrent Fault Section (See Fig. 3c)

Short Circuit Turn-Off Delay, t

Step I

LOAD:

0mA to 400mA

Short Circuit Recovery Time, t

ROFF

LOAD

= 400mA, 100

High Side Current Threshold, I

TH-H

CSH

= 0.5

250

325

400

Low Side Current Threshold, I

TH-L

CSL

= 0.5

250

325

400

Overcurrent Duty Cycle

LOAD

= 0.25

to GND

0.6

0.8

1.0

UC17131/2/3
UC27131/2/3
UC37131/2/3

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, CDEL = 10nF, VCC = 25V, CSL = GND, CSH = LS;

CSH

= 0.5

(Note 1); IN=0V (for OFF condition) and IN=5V (for ON condition); T

= T

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

LED Output

SINK

, t

DOFF

, t

ROFF

LED

= 7V

5.0

8.0

11.0

LEAKAGE

Overall

Delay to Output

ICC

Output Off

2.0

2.8

= 1mA, 250mA (High Side)

2.3

= 1mA, 250mA (Low Side)

2.5

Note 1: All test conditions are for a high side configuration as in Fig. 2a, unless otherwise specified.

CDEL: A capacitor connected to this pin is used to pro-
gram both VCC pulse interruption time and power
turn-on delay. The capacitor discharge time corresponds
to VCC interruption and the charge time to VCC turn-on
delay. The ratio between turn-on delay and turn-off delay
will be fixed based on internal charge and discharge cur-
rents and voltage thresholds.

The same fault circuitry and capacitor is used for short
circuit and overload protection. If an overcurrent or short
circuit is detected, the capacitor starts charging and
turns off the output if the condition persists at the end of
its charge time. The output will then operate in a low-duty
cycle mode to protect the IC. After short circuit recovery,
the output will be reactivated in order to check if the short
circuit was removed. If the overcurrent persists the chip
will continue in this pulsing mode.

CSH: (For UC37132 and UC37133) This high side cur-
rent sense pin is used to program the current limit for
high side applications by connecting a resistor between
VCC and CSH. An over load current is detected when
the voltage drop between VCC and CSH exceeds
150mV. For the UC37132, in a high side application, the
CSH pin must be tied to the LS pin; in a low side applica-
tion, the CSH pin must be tied to VCC

CSL: (For UC37131 and UC37132) This low side cur-
rent sense pin is used to program the current limit for low
side applications by connecting a resistor between CSL
and GND. An over load current is detected when the volt-
age drop between CSL and GND exceeds 150mV. For
the UC37132, in a high side application, the CSL pin
must be tied to GND; in a low side application, the CSL
pin must be tied to the HS pin.

GND: The reference point for the internal reference, all
thresholds, and the return for the remainder of the de-
vice.

HS: (For UC37132 and UC37133) The output of the
switching transistor in the high side configuration. The
emitter of the output transistor is the HS pin which is con-
nected to the load. For the UC37132, the HS pin must be
tied to the CSL pin in a low side application.

HYST: (For UC37132) The pin used to program the in-
put comparator hysteresis by connecting a resistor to
ground. The hysteresis defaults to 30% with HYST
grounded (internally for UC37131 and UC37133).

HYST

3000

3330

(

)

IN: The input to the comparator that detects when the
output transistor should be turned on. The input thresh-
old is 3.0V (1/2 VREF) and the input voltage range is 0V
to VREF.

LED: Open collector output intended to drive an LED.
This pin is driven low whenever the output is turned off
and is externally pulled high when the output is turned on
(see Fig. 3b and 3c).

LS: (For UC37131 and UC37132) The output of the
switching transistor in the low side configuration. The col-
lector of the output transistor is the LS pin which is con-
nected to the load. For the UC37132, the LS pin must be
tied to the CSH pin in a high side application.

VREF: The 6V regulated reference capable of supplying
up to 8mA. The recommended decoupling capacitor is
1nF.

VCC: The supply voltage for the chip. Decouple this pin
with a good quality ceramic capacitor to ground.

PIN DESCRIPTIONS

UC17131/2/3
UC27131/2/3
UC37131/2/3

Reference

The UC37131/2/3 family of devices features a 6V
bandgap reference that is used to bias on-chip logic. Al-
though the 6V reference is not trimmed, this bandgap ref-
erence provides less than 200ppm/°C. It is also used to
generate the on-chip 3V input comparator threshold and
is needed for the programmable hysteresis. The on-chip
reference has 8mA maximum current sourcing capacity
that is designed to power up external circuitry.

Input Comparator

The input comparator is a high gain comparator with hys-
teresis that fully switches with either a small signal
(30mV, minimum for 1% hysteresis) or a logic signal (0 to
6V max). Only a 5mV overdrive of the 3V threshold is
needed to switch the driver.

The hysteresis is set to 30% on the UC37131 and
UC37133. (This is 30% of 3V equating to 0.9V of hyster-
esis.) On the UC37132 it is programmable from 1% to
30%.

Fault Logic

The output of the comparator is logic ANDed with the
output of the fault logic. If a fault, either a power interrupt
or an overcurrent condition, persists longer than it takes
for the CDEL to discharge from its V

CDEL_MAX

level of

5.8V to its V

FAULT_L

of 1.3V, the fault protection block will

output a logic 0 to the NAND gate and turn off the output
driver. If the fault goes away prior to CDEL being dis-
charged to 1.3V, the chip will resume normal operation
without going through a turn-on delay.

The power interrupt normal operation consists of the chip
turning the driver immediately back on if the interrupt
goes away prior to CDEL reaching its lower threshold as
described above. The CDEL capacitor is chosen based
upon the maximum power interrupt time (t

INT

) allowed

without the output experiencing a turn-on delay. This in-
terrupt time must be less than t

D(OFF)

where t

D(OFF)

equal to the time it takes the CDEL capacitor to dis-
charge from V

CDEL_MAX

(5.8V) to V

FAULT_L

(1.3V) with a

discharge current of approximately 94

A. If the power

stays off only as long as t

D(OFF)

, the minimum power up

delay will be equal to the time it takes to charge CDEL
from V

FAULT_L

(1.3V) to V

FAULT_H

(4.9V) with a charge

current of approximately 4

A. If the power stays off lon-

ger than this time, then a power up delay will be initial-
ized once power is resumed. This delay is the time it
takes for CDEL to charge from 0V to V

FAULT_H

of 4.9V.

The overcurrent fault normal operation consists of the
chip staying off until CDEL fully recharges to V

FAULT_H

4.9V. This is t

R(OFF)

. Once CDEL reaches 4.9V, the driver

will turn back on. If the overcurrent fault is still present,
the chip will operate in a very low duty cycle (approxi-
mately 0.7%) based on the discharge (driver on) and
charge time (driver off) of the CDEL capacitor. This
overcurrent timing makes the chip act "smart" by allowing
very high currents needed to drive large capacitive loads
without setting off an overcurrent fault.

The overcurrent and current limit thresholds are pro-
grammed with the resistor R

CSH

from CSH to VCC (high

side) or R

CSL

from CSL to GND (low side). For example,

a 150mV (I

LOAD

CSH

) threshold will set the high side

overcurrent fault threshold. An overall short circuit protec-
tion threshold is set at 300mV. Therefore, the recom-
mended R

CSH

of 0.5

will result in the 600mA short

circuit. By changing the R

CSH

value the user can opti-

mally set the overcurrent and short circuit current limits.

Output Driver

Once the turn-on signal is gated through from the input
comparator, the output transistor is turned on. The output
drive transistor is a composite PNP, NPN structure. This
is a specially designed structure that keeps all the drive
current needed for the load to be sourced through the LS
pin. This keeps the overall power dissipation to less than
4mA independent of the load.

The output driver also has a 72V zener diode wired be-
tween its base and collector. This allows the output to
swing and clamp to 72V above ground when discharging
an inductive load in a low side application. The inductive
zener clamp can discharge the 250mA to 400mA full
load current. This consequently allows the LS pin to
safely swing above VCC. Similarly, the 72V zener diode
will allow the HS pin to safely swing and clamp 72V be-
low LS/VCC when discharging an inductive load in a high
side application. This 72V zener diode simplifies the user
application by eliminating the need for external clamp di-
odes.

DESCRIPTION OF OPERATION

UC17131/2/3
UC27131/2/3
UC37131/2/3

Choosing The CDEL Capacitor

The maximum amount of time that VCC power can be in-
terrupted and not require the outputs to go through a
turn-on delay cycle is user programmable by the CDEL
capacitor value. While VCC is interrupted, the outputs
will be in an indeterminate state and they may turn off
during this interval, t

INT

. However, as long as the pro-

grammed interruption time is not exceeded, the outputs
will immediately turn back on with the return of VCC.

For example:

INT

500

(User specified)

CDEL is selected such that the time it takes for this ca-
pacitor to discharge from V

CDEL_MAX

(5.8V) to V

FAULT_L

(1.3V) with a discharge current of 94

A is just greater

than this t

INT

. This time is referred to as t

D(OFF)

in Fig.

3b.

(

)

CDEL

DISCHARGE

D OFF

CDEL MAX

FAULT L

If t

D(OFF)

is set equal to t

INT

, which the user has selected

to be 500

s, the minimum CDEL capacitor is calculated:

CDEL

500

For this application, the CDEL capacitor value calculates
to 10.4nF. By using a 10nF capacitor on CDEL, VCC can
be interrupted for up to 478

s and the outputs will experi-

ence an indeterminate state during this interruption, but
resume normal operation when VCC power returns to
normal.

If the VCC power is interrupted for a time equal to or lon-
ger than t

D(OFF)

then the following relationships apply.

As the CDEL capacitor discharges past the V

FAULT_L

threshold, the output is fully disabled and must cycle
through a power up delay equal to t

D(ON)

. The charge

current for the CDEL capacitor is equal to 4

A. The out-

puts will turn on when the CDEL capacitor charges up to
the V

FAULT_H

threshold of 4.9V. The minimum turn-on

delay the outputs will experience will occur if t

INT

is ex-

actly equal to the t

D(OFF)

time and the CDEL capacitor

has only discharged to V

FAULT_L

. This would be the mini-

mum turn-on delay time and is calculated with the follow-
ing equation:

( )

CDEL

D ON

FAULT L

FAULT H

CHARGE

min

Using the 10nF CDEL capacitor, for example, the mini-
mum turn-on delay calculates to 9ms. If the CDEL ca-
pacitor discharges completely to zero, then the 10nF
CDEL capacitor would cause a turn-on delay of 12.25ms.
The outputs would be off for this amount of time after
VCC power is restored. The total amount of time the out-
puts could be disabled is equal to the t

INT

time, which

may include the indeterminate time of t

D(OFF)

, and the

D(ON)

time, as shown in Fig. 3b.

APPLICATION INFORMATION

CDEL

VREF

VCC

CSH

GND

PRE-REGULATOR

INPUT
COMPARATOR

1/2
VREF

HYST

LED

TURN-ON/OFF

AND SHORT

CIRCUIT

PROTECTION

CDEL

OUT

VREF

GND

72V

CSH

CSL

+ L

OUT

LOAD

GND

HYST

POWER
SUPPLY

REF

Figure 2a. High side application.

UDG-98027

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accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
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1999, Texas Instruments Incorporated

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