UC1851
UC2851
UC3851
Programmable, Off-Line, PWM Controller
FEATURES
All Control, Driving, Monitoring, and Protection
Functions Included
Low-Current Off Line Start Circuit
Voltage Feed Forward or Current Mode Control
High Current Totem Pole Output
50% Absolute Max Duty Cycle
PWM Latch for Single Pulse Per Period
Pulse-by-Pulse Current Limiting plus Shutdown
for Over-Current Fault
No Start-Up or Shutdown Transients
Slow Turn-On Both Initially and After Fault
Shutdown
Shutdown Upon Over or Under Voltage Sensing
Latch Off or Continuous Retry After Fault
1% Reference Accuracy
500kHz Operation
18 Pin DIL or 20 Pin PLCC Package
DESCRIPTION
The UC1851 family of PWM controllers are optimized for off-
line primary side control. These devices include a high current
totem pole output stage and a toggle flip-flop for absolute 50%
duty cycle limiting. In all other respects this line of controllers is
pin for pin compatible with the UC1841 series. Inclusion of all
major housekeeping functions in these high performance con-
trollers makes them ideal for use in cost sensitive applications.
Important features of these controllers include low current
start-up, linear feed-forward for constant volt-second operation,
and compatibility with both voltage or current mode control. In
addition, these devices include a programmable start thresh-
old, as well as programmable over-voltage, under-voltage, and
over current fault thresholds. The fault latch on these devices
can be configured for automatic restart, or latched off response
to a fault.
These devices are packaged in 18-pin plastic or ceramic dual-
in-line packages, or for surface mount applications, a 20 Pin
PLCC. The UC1851 is characterized for -55
C to +125
C op-
eration while the UC2851 and UC3851 are designed for -40
C
to +85
C and 0
C to +70
C, respectively.
BLOCK DIAGRAM
10/94
UC1851
UC2851
UC3851
Supply Voltage, +V
IN
(Pin 15)
Voltage Driven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +32V
Current Driven, 100mA maximum . . . . . . . . . . . Self-limiting
PWM Output Voltage (Pin 12) . . . . . . . . . . . . . . . . . . . . . . . 40V
PWM Output Current, Steady-State (Pin 12) . . . . . . . . . 400mA
PWM Output Peak Energy Discharge . . . . . . . . . . . . 20
Joules
Driver Bias Current (Pin 14) . . . . . . . . . . . . . . . . . . . . . -200mA
Reference Output Current (Pin 16) . . . . . . . . . . . . . . . . -50mA
Slow-Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . 20mA
V
IN
Sense Current (Pin 11). . . . . . . . . . . . . . . . . . . . . . . . 10mA
Current Limit Inputs (Pins 6 & 7) . . . . . . . . . . . . . -0.5 to +5.5V
Stop Input (Pin 4) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +5.5V
Comparator Inputs
(Pins 17, 911, 16). . . . . . . . . . . . . . Internally clamped at 12V
Power Dissipation at T
A
= 25C (Note 3). . . . . . . . . . . 1000mW
Power Dissipation at T
C
= 25C (Note 3). . . . . . . . . . . 2000mW
Operating Junction Temperature . . . . . . . . . . . -55C to +150C
Storage Temperature Range . . . . . . . . . . . . . . -65C to +150C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300C
Note 1:All voltages are with respect to ground, Pin 13.
Currents are positive-into, negative-out of the
specified terminal
Note 2:All pin numbers are referenced to DIL-18 package.
Note 3:Consult Packaging Section of Databook for thermal
limitations and considerations of package.
DIL-18, SOIC-18 (TOP VIEW)
J or N, DW Package
CONNECTION DIAGRAMS
PACKAGE PIN FUNCTIONS
FUNCTION
PIN
COMP
1
START/UV
2
OV SENSE
3
STOP
4
RESET
5
CUR THRESH
7
CUR SENSE
8
SLOW START
9
R
T
/C
T
10
RAMP
11
V
IN
SENSE
12
PWM OUT
13
GROUND
14
DRIVE BIAS
15
+V
IN
SUPPLY
17
5.0V REF
18
INV. INPUT
19
N.I. INPUT
20
PLCC-20, LCC-20
(TOP VIEW)
Q, L PACKAGE
ABSOLUTE MAXIMUM RATINGS (Note 1)
Unless otherwise stated, these specifications apply for T
A
= -55C to +125C for the
UC1851, -40C to +85C for the UC2851, and 0C to 70C for the UC3851; V
IN
=
20V, R
T
= 20k
, C
T
= .001 mfd, R
R
= 10k
, C
R
= .001mfd. Current Limit Threshold
= 200mV, T
A
= T
J.
ELECTRICAL CHARACTERISTICS:
PARAMETER
TEST CONDITIONS
UC1851 / UC2851
UC3851
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
Power Inputs
Start-Up Current
V
IN
= 30V, Pin 2 = 2.5V
4.5
6
4.5
6
mA
Operating Current
V
IN
= 30V, Pin 2 = 3.5V
15
21
15
21
mA
Supply OV Clamp
V
IN
= 20mA
33
39
45
33
39
45
V
Reference Section
Reference Voltage
T
J
= 25C
4.95
5.0
5.05
4.9
5.0
5.1
V
Line Regulation
V
IN
=
8 to 30V
10
15
10
20
mV
Load Regulation
I
L
= 0 to 10mA
10
20
10
30
mV
Total Ref Variation
Over Operating Temperature Range
4.9
5.1
4.85
5.15
V
Short Circuit Current
V
REF
= 0, T
J
= 25C
-80
-100
-80
-100
mA
Oscillator
Nominal Frequency
T
J
= 25C
47
50
53
45
50
55
kHz
Voltage Stability
V
IN =
8 to 30V
0.5
1
0.5
1
%
Total Ref Variation
Over Operating Temperature Range
45
55
43
57
kHz
Maximum Frequency
R
T
= 2k
, C
T
= 330pF
500
500
kHz
2
ELECTRICAL CHARACTERISTICS:
PARAMETER
TEST CONDITIONS
UC1851 / UC2851
UC3851
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
Ramp Generator
Ramp Current, Minimum
I
SENSE
=
-
10
A
-11
-14
-11
-14
A
Ramp Current, Maximum
I
SENSE
= 1.0mA
-0.9
-.95
-0.9
-.95
mA
Ramp Valley
0.3
0.4
0.6
0.3
0.4
0.6
V
Ramp Peak
Clamping Level
3.9
4.2
4.5
3.9
4.2
4.5
V
Error Amplifier
Input Offset Voltage
V
CM
= 5.0V
0.5
5
2
10
mV
Input Bias Current
0.5
2
1
5
A
Input Offset Current
0.5
0.5
A
Open Loop Gain
V
O
= 1 to 3V
60
66
60
66
dB
Output Swing (Max Output
Ramp Peak - 100mV)
Minimum Total Range
0.3
3.5
0.3
3.5
V
CMRR
V
CM
= 1.5 to 5.5V
70
80
70
80
dB
PSRR
V
IN
= 8 to 30V
70
80
70
80
dB
Short Circuit Current
V
COMP
= 0V
-4
-10
-4
-10
mA
Gain Bandwidth (Note 1)
T
J
= 25C, A
VOL
= 0dB
1
2
1
2
MHz
Slew Rate (Note 1)
T
J
= 25C, A
VCL
= 0dB
0.8
0.8
V/
s
PWM Section
Continuous Duty Cycle Range
(other than zero) (Note 1)
Minimum Total Continuous Range
Ramp Peak < 4.2V
2
46
2
46
%
Output High Level
I
SOURCE
= 20mA
18
18.5
18
18.5
V
I
SOURCE
= 200mA
17
18.5
17
18.5
V
Rise Time (Note 1)
T
J
= 25C, C
L
= 1nF
50
150
50
150
ns
Fall Time (Note 1)
T
J
= 25C, C
L
= 1nF
50
150
50
150
ns
Output Saturation
I
OUT
= 20mA
0.2
0.4
0.2
0.4
V
I
OUT
= 200mA
1.7
2.2
1.7
2.2
V
Comparator Delay (Note 1)
Pin 8 to Pin 12, T
J
= 25C, R
L
= 1k
300
500
300
500
ns
Sequencing Functions
Comparator Thresholds
Pins 2, 3, 5
2.8
3.0
3.2
2.8
3.0
3.2
V
Input Bias Current
Pins 3, 5 = 0V
-1.0
-4.0
-1.0
-4.0
A
Input Leakage
Pins 3, 5 = 10V
0.1
2.0
0.1
2.0
A
Start/UV Hysteresis Current
Pin 2 = 2.5V
170
200
220
170
200
230
A
Ext. Stop Threshold
Pin 4
0.8
1.6
2.4
0.8
1.6
2.4
V
Error Latch Activate Current
Pin 4 = 0V, Pin 3 > 3V
-120
-200
-120
-200
A
Driver Bias Saturation Voltage,
V
IN
-V
OH
I
B
= -50mA
2
3
2
3
V
Driver Bias Leakage
V
B
= 0V
-0.1
-10
-0.1
-10
A
Slow-Start Saturation
I
S
= 10mA
0.2
0.5
0.2
0.5
V
Slow-Start Leakage
V
S
= 4.5V
0.1
2.0
0.1
2.0
A
Current Control
Current Limit Offset
0
5
0
10
mV
Current Shutdown Offset
370
400
430
360
400
440
mV
Input Bias Current
Pin 7 = 0V
-2
-5
-2
-5
A
Common Mode Range (Note 1)
-0.4
3.0
-0.4
3.0
V
Current Limit Delay (Note 1)
T
J
= 25C, Pin 7 to 12, R
L
= 1k
200
400
200
400
ns
Note 1:Guaranteed by design. Not 100% tested in production.
UC1851
UC2851
UC3851
Unless otherwise stated, these specifications apply for T
A
= -55C to +125C for the
UC1851, -40C to +85C for the UC2851, and 0C to 70C for the UC3851; V
IN
=
20V, R
T
= 20k
, C
T
= .001 mfd, R
R
= 10k
, C
R
= .001mfd. Current Limit Threshold
= 200mV, T
A
= T
J.
3
UC1851
UC2851
UC3851
PWM CONTROL
1. Oscillator
Generates a fixed-frequency internal clock from an external R
T
and C
T
.
Frequency =
K
C
R
T
C
T
where K
C
is a first-order correction factor
0.3 log (C
T
x 10
12
).
2. Ramp Generator:
Develops linear ramp with slope defined externally by
d
V
d
T
=
sense voltage
R
R
C
R
.
C
R
is normally selected
C
T
and its value will have some effect upon valley duty cycle.
Limiting the minimum value for I
SENSE
into pin 11 will establish a maximum duty cycle clamp.
C
R
terminal can be used as an input port for current mode control.
3. Error Amplifier
Conventional operational amplifier for closed-loop gain and phase compensation.
Low output impedance; unity-gain stable.
The output is held low by the slow start voltage at turn on in order to minimize overshoot.
4. Reference Generator:
Precision 5.0V for internal and external usage to 50mA.
Tracking 3.0V reference for internal usage only with nominal accuracy of
2%.
40V clamp zener for chip OV protection, 100mA maximum current.
5. PWM Comparator:
Generates output pulse which starts at termination of clock pulse and ends when the ramp input
crosses the lowest of two positive inputs.
6. PWM Latch:
Terminates the PWM output pulse when set by inputs from either the PWM comparator, the
pulse-by-pulse comparator, or the error latch. Resets with each internal clock pulse.
7. PWM Output Switch:
Totem pole output stage capable of sourcing and sinking 1 amp peak current. The active "on" state
is high.
SEQUENCING FUNCTIONS
1. Start/UV Sense:
With an increasing voltage, this comparator generates a turn-on signal and releases the slow start
clamp at a start threshold.
With a decreasing voltage, it generates a turn-off command at a lower level separated by a 200
A
hysteresis current.
2. Drive Switch:
Disables most of the chip to hold internal current consumption low, and Driver Bias OFF, until input
voltage reaches start threshold.
3. Driver Bias:
Supplies drive to external circuitry upon start-up.
4. Slow Start:
Clamps low to hold PWM OFF. Upon release, rises with rate controlled by R
S
C
S
for slow increase of
output pulse width.
Can also be used as an alternate maximum duty cycle clamp with an external voltage divider.
PROTECTION FUNCTIONS
1. Error Latch:
When set by momentary input, this latch insures immediate PWM shutdown and hold off until reset.
Inputs to Error Latch are:
a. OV > 3.2V (Typically 3V)
b. Stop > 2.4V (Typically 1.6V)
c. Current Sense 400mV over threshold. (Typical).
Error Latch resets when slow start voltage falls to 0.4V if Reset Pin < 2.8V. With Pin 5 > 3.2V,
Error Latch will remain set.
2. Current Limiting:
Differential input comparator terminates individual output pulses each time sense voltage rises
above threshold.
When sense voltage rises to 400mV (typical) above threshold, a shutdown signal is sent to Error
Latch.
3. External Stop:
A voltage over 2.4 will set the Error Latch and hold the output off.
A voltage less than 0.8V will defeat the error latch and prevent shutdown.
A capacitor here will slow the action of the error latch for transient protection by providing a Typical
Delay of 13ms/
F.
FUNCTIONAL DESCRIPTION
4
UC1851
UC2851
UC3851
Start/UV Hysteresis Current
Output Saturation Characteristics
Oscillator Frequency
PWM Output Minimum Pulse Width
Error Amplifier Open-Loop Gain and Phase
Shutdown Timing
5
UC1851
UC2851
UC3851
OPEN-LOOP CIRCUIT
High Peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass
capacitors should be connected close to pin 13 in a single ground point.
Programmable Soft Start and Restart Delay Circuit
For further application information see UC1840/UC1841
Data Sheets
UC1851 Power MOSFET Drive Interface
UNITRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD.
MERRIMACK, NH 03054
TEL. (603) 424-2410
FAX (603) 424-3460
Nominal Frequency =
1
R
T
C
T
= 50kHz
Start Voltage = 3
R1
+
R2
+
R3
R2
+
R3
+0.2R1 = 12V
UV Fault Voltage
= 3
R1
+
R2
+
R3
R2
+
R3
= 8V
OV Fault Voltage
= 3
R1
+
R2
+
R3
R3
= 32V
Current Limit = 200mV
Current Fault Voltage = 600mV
Duty Cycle Clamp = 50%
@V
IN
= 15V, Duty Cycle = 48%
@V
IN
= 30V, Duty Cycle = 24%
6
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER'S RISK.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI's publication of information regarding any third
party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright
1999, Texas Instruments Incorporated
PDF 
ZIP