UC1573
UC2573
UC3573
DESCRIPTION
The UC3573 is a Buck pulse width modulator which steps down and regu-
lates a positive input voltage. The chip is optimized for use in a single in-
ductor buck switching converter employing an external PMOS switch. The
block diagram consists of a precision reference, an error amplifier config-
ured for voltage mode operation, an oscillator, a PWM comparator with
latching logic, and a 0.5A peak gate driver. The UC3573 includes an
undervoltage lockout circuit to insure sufficient input supply voltage is pres-
ent before any switching activity can occur, and a pulse-by-pulse current
limit. Input current can be sensed and limited to a user determined maxi-
mum value. In addition, a sleep comparator interfaces to the UVLO circuit
which turns the chip off when the input voltage is below the UVLO thresh-
old. This reduces the supply current to only 50
A, making the UC3573
ideal for battery powered applications.
Buck Pulse Width Modulator Stepdown Voltage Regulator
FEATURES
Simple Single Inductor Buck PWM
Stepdown Voltage Regulation
Drives External PMOS Switch
Contains UVLO Circuit
Includes Pulse-by-Pulse Current Limit
Low 50
A Sleep Mode Current
SLUS346 - APRIL 1999
BLOCK DIAGRAM
UDG-94106-1
application
INFO
available
2
UC1573
UC2573
UC3573
DIL-8, SOIC-8 (TOP VIEW)
J or N, D Packages
ABSOLUTE MAXIMUM RATINGS
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35V
EAINV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6V to VCC
I
EAOUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
RAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V to 4V
CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V to VCC
I
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7A to 0.7A
I
3VREF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA
Storage Temperature . . . . . . . . . . . . . . . . . . . 65C to +150C
Junction Temperature . . . . . . . . . . . . . . . . . . . 65C to +150C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300C
Currents are positive into, negative out of the specified termi-
nal. Consult Packaging Section of Databook for thermal limita-
tions and considerations of packages.
CONNECTION DIAGRAMS
ELECTRICAL CHARACTERISTICS:
Unless otherwise specified, these parameters apply for T
A
= 55C to +125C for
the UC1573, 40C to +85C for the UC2573, and 0C to +70C for the UC3573, VCC = 5V, CT = 680pF, T
A
= T
J
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Reference Section
3VREF
2.94
3
3.06
V
Line Regulation
VCC = 4.75 to 30V
1
10
mV
Load Regulation
I
3VREF
= 0 to 5mA
1
10
mV
Oscillator Section
Frequency
V
CC
= 5V, 30V
85
100
115
kHz
Error Amp Section
EAINV
EAOUT = 2V
1.45
1.5
1.55
V
I
EAINV
EAOUT = 2V
0.2
1
A
AVOL
EAOUT = 0.5V to 3V
65
90
dB
EAOUT High
EAINV = 1.4V
3.6
4
4.4
V
EAOUT Low
EAINV = 1.6V
0.1
0.2
V
I
EAOUT
EAINV = 1.4V, EAOUT = 2V
350
500
A
EAINV = 1.6V, EAOUT = 2V
7
20
mA
Unity Gain Bandwidth
T
J
= 25C, F = 10kHz
0.6
1
MHz
Current Sense Comparator Section
Threshold (referred to VCC)
0.39
0.43
0.47
V
Input Bias Current
CS = VCC
150
800
nA
CS Propagation Delay
400
ns
Gate Drive Output Section
OUT High Saturation
I
OUT
= 0
0
0.3
V
I
OUT
= 10mA
0.7
1.5
V
I
OUT
= 100mA
1.5
2.5
V
OUT Low Saturation
I
OUT
= 10mA
0.1
0.4
V
I
OUT
= 100mA
1.5
2.2
V
Rise Time
T
J
= 25C, C
LOAD
= 1nF + 3.3 Ohms
30
80
ns
Fall Time
T
J
= 25C, C
LOAD
= 1nF + 3.3 Ohms
30
80
ns
Pulse Width Modulator Section
Maximum Duty Cycle
EAINV = 1.4V
92
96
%
Minimum Duty Cycle
EAINV = 1.6V
0
%
Modulator Gain
EAOUT = 1.5V to 2.5V
25
35
45
%/V
Undervoltage Lockout Section
Start Threshold
3.5
4.2
4.5
V
Hysteresis
100
200
300
mV
3
UC1573
UC2573
UC3573
3VREF: Precision 3V reference. Bypass with 100nF ca-
pacitor.
CS: Peak current limit sense pin. Senses the current
across a current sense resistor placed between VCC and
source of the PMOS Buck switch. OUT will be held high
(PMOS buck switch off) if VCC CS exceeds 0.4V.
EAINV: Inverting input to error amplifier. VOUT sense
feedback connected to this pin. The non-inverting input of
the error amplifier is internally connected to:
3
2
VREF
Volts
.
Connecting the EAINV pin to an external voltage greater
than 2.6V commands the chip to go into a low current
sleep mode.
EAOUT: Output of error amplifier. Use EAOUT and
EAINV for loop compensation components.
GND: Circuit Ground.
OUT: Gate drive for external PMOS switch connected be-
tween VCC and the flyback inductor. OUT drives the gate
of the PMOS switch between VCC and GND.
RAMP: Oscillator and ramp for pulse width modulator.
Frequency is set by a capacitor to GND by the equation
F
k C
RAMP
1
15
Recommended operating frequency range is 10kHz to
200kHz.
VCC: Input voltage supply to chip. Range is 4.75V to 30V.
Bypass with a 1
m
F capacitor.
PIN DESCRIPTIONS
ELECTRICAL CHARACTERISTICS:
Unless otherwise specified, these parameters apply for T
A
= 55C to +125C for
the UC1573, 40C to +85C for the UC2573, and 0C to +70C for the UC3573, VCC = 5V, CT = 680pF, T
A
= T
J
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Sleep Mode Section
Threshold
1.8
2.2
2.6
V
Supply Current Section
I
VCC
VCC = 30V
9
12
mA
I
VCC
VCC = 30V, EAINV = 3V
50
150
m
A
Typical Waveforms.
UDG-94107
4
UC1573
UC2573
UC3573
4
8
7
1
2
6
C
RAMP
680pF
C V
CC
10
F
R
COMP
R
VSENSE2
39k
3
5
RV
SENSE1
91K
R
SLEEP
24k
M
SLEEP
R
SLEEP3
1MEG
VIN
SLEEP
+12V IN
C
BULK
10
F
C
OUT
100
F
R
CS
GND
EAOUT
EAINV
RAMP
3VREF
VCC
CS
OUT
VOUT
GND
+5V
OUT
L
BUCK
D
CATCH
1A
M
SWITCH
UC1573
GND
C3 V
REF
100nF
C
COMP
TYPICAL APPLICATION: 12V TO 5V BUCK CONVERTER
UDG-99050
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