ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Output Sink Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Output Short Circuit Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Sec
Common Mode Input Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Differential Input Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
Failsafe Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to V
CC
PLCC Power Dissipation, T
A
= 25C (Note 2). . . . . . . . . . . . . . . . . . . 1000 mW
DIP Power Dissipation, T
A
= 25C (Note 2) . . . . . . . . . . . . . . . . . . . . 1200 mW
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C
Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . . . . . . . . . . . . . -300C
Note 1: All voltages are with respect to ground, pin 14. Currents are positive
into, negative out of the specified terminal
Note 2: Consult Packaging Section of Databook for thermal limitations and
considerations of package.
Octal Line Receiver
UC5180C
DIL-28 (TOP VIEW)
CONNECTION DIAGRAMS
DESCRIPTION
The UC5180C is an octal line receiver designed to meet a wide range
of digital communications requirements as outlined in EIA standards
EIA232E, EIA423A, EIA422A, and CCITT V.10, V.11, V.28, X.26, and
X.27. The UC5180C includes an input noise filter and is intended for
applications employing data rates up to 200 KBPS. A failsafe function
allows these devices to "fail" to a known state under a wide variety of
fault conditions at the inputs.
FEATURES
Meets EIA 232E/423A/422A and CCITT
V.10,V.11, V.28, X.26, X.27
Single +5V Supply--TTL Compatible
Outputs
Differential Inputs Withstand
25V
Low Open Circuit Voltage for Improved
Failsafe Characteristic
Reduced Supply Current--35 mA Max
Input Noise Filter
Internal Hysteresis
PLCC-28 (TOP VIEW)
1/94
DC ELECTRICAL CHARACTERISTICS:
PARAMETERS
SYMBOL
TEST CONDITIONS
UC5180C
UNITS
MIN
MAX
DC Input Resistance
R
IN
3V
|
V
IN
|
25V
3
7
k
Failsafe Output Voltage
V
OFS
Inputs Open or Shorted
Together, or One Input
Open and One Grounded
0
I
OUT
8mA, V
FAILSAFE
= 0V
0.45
V
0
I
OUT
- 400
A,
V
FAILSAFE
= V
CC
2.7
Differential Input High
Threshold
V
TH
V
OUT
= 2.7V, I
OUT
= 440
A
(See Figure 1)
R
S
= 0 (Note 2)
50
200
mV
R
S
= 500 (Note 2)
400
Differential Input Low
Threshold
V
TL
V
OUT
= 0.45V, I
OUT
= 440 mA
(See Figure 1)
R
S
= 0 (Note 2)
-200
-50
mV
R
S
= 500 (Note 2)
-400
Hysteresis
V
H
F
S
= 0V or V
CC
(See Figure 1)
50
140
mV
Open Circuit Input Voltage
V
ICC
75
mV
Input Capacitance
C
I
20
pF
High Level Output Voltage
V
CH
V
ID
= 1V, I
OUT
= - 440
A
2.7
V
Low Level Output Voltage
V
OL
V
ID
= -1V
(Note 3)
I
OUT
= 4 mA
0.4
V
I
OUT
= 8 mA
0.45
Short Circuit Output
Current
I
OS
Note 4
20
100
mA
Supply Current
I
CC
4.75V
V
CC
5.25V
35
mA
Input Current
I
IN
Other Inputs Grounded
V
IN
= +10V
3.25
mA
V
IN
= -10V
-3.25
UC5180C
Figure 1.
V
tL
, V
tH
, V
H
Definition
Unless otherwise stated these specifications apply for T
A
= 0C to +70C, V
CC
= 5V
5%, Input Common Mode Range
7V, T
A
=T
J
AC ELECTRICAL CHARACTERISTICS:
PARAMETERS
SYMBOL
TEST CONDITIONS
UC5180C
UNITS
MIN
MAX
Propagation Delay - Low to High
t
PLH
C
L
= 50pF, V
IN
=
500mV
550
ns
Propagation Delay - High to Low
t
PHL
C
L
= 50pF, V
IN
=
500mV
550
ns
Acceptance Input Frequency
f
A
Unused Input Grounded, V
IN
=
200mV
0.1
MHz
Rejectable Input Frequency
f
R
Unused Input Grounded, V
IN
=
500mV
5.5
MHz
V
CC
= 5V
5%, T
A
= 0C to + 70C, Figure 2, T
A
= T
J.
Note 2: R
S
is a resistor in series with each input.
Note 3: Measured after 100ms warm up (at 0C)
Note 4: Only 1 output may be shorted at one time
and then only for a maximum of 1 sec.
2
UC5180C
APPLICATIONS INFORMATION
Failsafe Operation
These devices provide a failsafe operating mode to
guard against input fault conditions as defined in
EIA422A and EIA423A standards. These fault condi-
tions are (1) drive in power-off condition, (2) receiver not
interconnected with driver, (3) open-circuited intercon-
necting cable, and (4) short-circuited interconnecting
cable. If one of these four fault conditions occurs at the
inputs of a receiver, then the output of that receiver is
driven to a known logic level. The receiver is pro-
grammed by connecting the failsafe input to V
CC
or
ground. A connection to V
CC
provides a logic "1" output
under fault conditions, while a connection to ground
provides a logic "0". There are two failsafe pins (F
S1
and F
S2
) on the UC5180C where each provides com-
mon failsafe control for four receivers.
Input Filtering (UC5180C)
The UC5180C has input filtering for additional noise re-
jection. This filtering is a function of both signal level
and frequency. For the specified input (5.5 MHz at
500
mV) the input stage filter attenuates the signal such that
the output stage threshold levels are not exceeded and
no change of state occurs at the output.
EIA232E/V.28 / EIA423A/V.10 DATA TRANSMISSION
EIA422A/V.11 DATA TRANSMISSION
UNITRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD.
MERRIMACK, NH 03054
TEL. (603) 424-2410
FAX (603) 424-3410
Figure 2.
AC Test Circuit
3
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Copyright
1999, Texas Instruments Incorporated
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