UCC1806

UCC2806

UCC3806

SLUS272C - FEBRUARY 2000 - REVISED JUNE 2003

LOW-POWER, DUAL OUTPUT,

CURRENT MODE PWM CONTROLLER

www.ti.com

FEATURES

BiCMOS Version of UC3846 Family

1.4-mA Maximum Operating Current

100-

A Maximum Startup Current

0.5-A Peak Output Current

125-ns Circuit Delay

Easier Parallelability

Improved Benefits of Current Mode Control

DESCRIPTION

The UCC3806 family of BiCMOS PWM controllers
offers exceptionally improved performance with a
familiar architecture. With the same block diagram
and pinout of the popular UC3846 series, the
UCC3806 line features increased switching
frequency capability while greatly reducing the
bias current used within the device. With a typical
startup current of 50

A and a well defined voltage

threshold for turn-on, these devices are favored

for applications ranging from off-line power
supplies to battery operated portable equipment.
Dual high-current, MOSFET driving outputs and a
fast current sense loop further enhance device
versatility.

All the benefits of current mode control including
simpler loop closing, voltage feed-forward,
parallelability with current sharing, pulse-by-pulse
current limiting, and push/pull symmetry
correction are readily achievable with the
UCC3806 series.

These devices are available in multiple package
options for both through-hole and surface mount
applications; and in commercial, industrial, and
military temperature ranges.

The UCC3806 is specified for operation from
-55

C to 125

C, the UCC2806 is specified for

operation from -40

C to 85

C, and the UCC3806

is specified for operation from 0

C to 70

SIMPLIFIED APPLICATION DIAGRAM

INV

AOUT

BOUT

VREF

CURLIM

UCC3806

SYNC

CS+

VIN

COMP

UCC3612

CS-

GND

UC39431

+VIN

+VOUT

SHUT

DOWN

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1999 - 2003, Texas Instruments Incorporated

UCC1806

UCC2806

UCC3806

SLUS272C - FEBRUARY 2000 - REVISED JUNE 2003

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)

UCx806

UNIT

Supply voltage, VIN

VIN, low impedance

Supply current, IIN

VIN, high impedance

Output supply voltage

Continuous source or sink

200

Output current

Gate drive

500

Output current

SYNC

COMP

10 to -(self-limiting)

Analog input voltage range

CS-, CS+, NI, INV, SHUTDOWN

-0.3 to (VIN + 0.3)

Storage temperature, Tstg

-65 to 150

Operating temperature, TJ

-55 to 150

Lead temperature, Tsol, 1,6 mm (1/16 inch) from case for 10 seconds

300

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to
GND. Currents are positive into and negative out of, the specified terminal.

RECOMMENDED OPERATING CONDITIONS

MIN

NOM

MAX

UNIT

Input voltage, VIN

8.0

14.5

UCC1806

-55

125

Operating junction temperature, TJ

UCC2806

-40

Operating junction temperature, TJ

UCC3806

PACKAGE DESCRIPTION

CURLIM

VREF

CS-

CS+

INV

COMP

SHUTDOWN
VIN
BOUT
VC
GND
AOUT
SYNC
RT

D, DW, J, M, N OR PW PACKAGE

(TOP VIEW)

1 20 19

9 10 11 12 13

BOUT
VC
N/C
GND
AOUT

CS-

CS+

N/C

INV

Q OR L PACKAGE

(TOP VIEW)

VREF

CURLIM

SYNC

SHUTDOWN

VIN

COMP

N/C

N/C - No connection

UCC1806

UCC2806

UCC3806

SLUS272C - FEBRUARY 2000 - REVISED JUNE 2003

www.ti.com

ORDERING INFORMATION

PACKAGED DEVICES

TA = TJ

DESIGNATOR

TYPE

OPTION

QUANTITY

- 55

C to 125

- 40

C to 85

C to 70

SOIC-16

Tube

UCC2806D

SOIC-16

Reeled

2,500

UCC2806DTR

SOICW-16

Tube

UCC2806DW

UCC3806DW

SOICW-16

Reeled

2,000

UCC2806DWTR

UCC3806DWTR

CDIP-16

Tube

UCC1806J

UCC2806J

UCC3806J

CLCC-20

Tube

UCC1806L

SSOP-16

Reeled

2,500

UCC2806MTR

PDIP-16

Tube

UCC2806N

UCC3806N

TSSOP-16

Tube

UCC2806PW

UCC3806PW

TSSOP-16

Reeled

2,000

UCC2806PWTR

UCC3806PWTR

PLCC-20

Tube

UCC2806Q

UCC3806Q

PLCC-20

Reeled

1,000

UCC2806QTR

UCC3806QTR

ELECTRICAL CHARACTERISTICS

VIN = 12 V, RT = 33 k

, CT = 330 pF, CBYPASS on VREF = 0.01

F, -55

C < TA < 125

C for the UCC1806, -40

C < TA < 85

C for the

UCC2806, 0

C < TA < 70

C for the UCC3806, and TA = TJ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

REFERENCE

VREF

Supply, UVLO, turn-on

UCC1806
UCC2806

5.02

5.10

5.17

VREF

Supply, UVLO, turn-on

UCC3806

5.00

5.10

5.20

Load regulation

0.2 mA

IOUT

5 mA

Total output variation (1)(2)

Line, load, temperature

-150

150

Output noise voltage (2)

10 Hz

fOSC

10 kHz,

TJ = 25

Long term stability (2)

TA = 125

C, 1000

hours

Output short circuit

-10

-30

OSCILLATOR

Initial accuracy

TJ = 25

kHz

Temperature stability (2)

T(min)

T(max)

Amplitude

2.35

tDELAY

Delay-to-output time, SYNC

UCC1806
UCC2806

VCT = 0 V,

VRT = VREF

0.8 V

VSYNC

2.0 V

125

tDELAY

Delay-to-output time, SYNC

UCC3806

VCT = 0 V,

VRT = VREF

0.8 V

VSYNC

2.0 V

100

UCC1806

UCC2806

UCC3806

SLUS272C - FEBRUARY 2000 - REVISED JUNE 2003

www.ti.com

ELECTRICAL CHARACTERISTICS

VIN = 12 V, RT = 33 k

, CT = 330 pF, CBYPASS on VREF = 0.01

F, -55

C < TA < 125

C for the UCC1806, -40

C < TA < 85

C for the

UCC2806, 0

C < TA < 70

C for the UCC3806, and TA = TJ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OSCILLATOR (continued)

IDCHG

Discharge current

TJ = 25

C, VCT = 2.0 V

VOL

Low-level output voltage, SYNC

IOUT = 1 mA

0.4

VOH

High-level output voltage, SYNC

IOUT = -4 mA

2.4

VIL

Low-level input voltage, SYNC

VCT = 0 V,

VRT = VREF

0.8

VIH

High-level input voltage, SYNC

VCT = 0 V,

VRT = VREF

2.0

ISYNC

Input current, SYNC

-1

ERROR AMPLIFIER

Input offset voltage

UCC1806
UCC2806

Input offset voltage

UCC3806

IBIAS

Input bias current

-1

IOFSET

Input offset current

500

CMR

Common mode range(1)

VIN-2

AVOL

Open loop gain

1 V

VOUT

4 V

100

GBW

bandwidth

MHz

ICOMP_SINK Output sink current

VID < -20 mV,

VCOMP = 1 V

ICOMP_SRC Output source current

VID < 20 mV,

VCOMP = 3 V

-80

-120

VCOMP_L

Low-level output voltage

VID = -50 mV

0.5

VCOMP_H

High-level output voltage

VID = -50 mV

4.5

CURRENT SENSE AMPLIFIER

Amplifier gain(3)(4)

VCS- = 0 V,

VCURLIM = VREF

2.75

3.00

3.35

V/V

Maximum differential input signal (VCS+
- VCS-)

VCURLIM = VNI = VREF,
VINV = 0V

1.1

Input offset voltage

UCC1806
UCC2806

VCURLIM = 0.5 V, VCOMP = OPEN

Input offset voltage

UCC3806

VCURLIM = 0.5 V, VCOMP = OPEN

CMRR

Common mode rejection ratio

0 V

VCM

(VIN - 3.5 V)

PSRR

Power supply rejection ratio

IBIAS

Input bias current (3)

VCURLIM = 0.5 V, VCOMP = OPEN

-1

Input offset current (3)

VCURLIM = 0.5 V, VCOMP = OPEN

Delay-to-output time (5)

VNI = VREF,

VINV = 0 V,

VCURLIM = 2.75 V,
(VCS+ - VCS-) = 0 V to 1.5 V step

125

175

CURRENT LIMIT ADJUST

Current limit offset

VCS- = VCS+ = 0 V, VCOMP = OPEN

0.4

0.5

0.6

IBIAS

Input bias current

Minimum latching current

300

200

Maximum non-latching current

200

(1)

Line range = 10 V to 15 V, load range = 0.2 mA to 5 mA

(2)

Ensured by design. Not production tested.

UCC1806

UCC2806

UCC3806

SLUS272C - FEBRUARY 2000 - REVISED JUNE 2003

www.ti.com

ELECTRICAL CHARACTERISTICS

VIN = 12 V, RT = 33 k

, CT = 330 pF, CBYPASS on VREF = 0.01

F, -55

C to 125

C for the UCC1806, -40

C < TA < 85

C for the UCC2806,

C < TA < 70

C for the UCC3806, and TA = TJ (unless otherwise noted)

SHUTDOWN TERMINAL

Threshold voltage

UCC1806
UCC2806

0.94

1.00

1.06

Threshold voltage

UCC3806

0.9

1.0

1.1

Input voltage range

VIN

tDLY

Delay-to-output time

0 V

VSHUTDOWN

1.3 V

150

OUTPUT

Output supply voltage

2.5

15.0

UCC1806

ISINK = 20 mA

100

300

Low-level output voltage

UCC1806
UCC2806

ISINK = 100 mA

0.4

1.1

Low-level output voltage

UCC3806

ISINK = 20 mA

100

200

UCC3806

ISINK = 100 mA

0.4

1.1

High-level output voltage

ISRC = -20 mA

11.6

11.9

High-level output voltage

ISRC = -100 mA

11.0

11.6

tRISE

Rise time

TJ = 25

C, CLOAD = 1000 pF

tFALL

Fall time

TJ = 25

C, CLOAD = 1000 pF

UNDERVOLTAGE LOCKOUT (UVLO)

VSTART Startup threshold voltage

6.5

7.5

8.0

Threshold hysteresis

0.75

ISTART Startup current

VIN < VSTART

100

Operating supply current

1.0

1.4

VIN shunt voltage

IVIN = 10 mA

15.0

17.5

(1)

Line range = 10 V to 15 V, load range = 0.2 mA to 5 mA

(2)

Ensured by design. Not production tested.

(3)

Parameters measured at trip point of latch with VNI = VREF , VINV = 0V.

(4)

Amplifier gain defined as: G = delta change at COMP /delta change forced at CS+ delta voltage at CS+ = 0 to 1V

(5)

Current-sense amplifier output is slew rate limited to provide noise immunity.

THERMAL RESISTANCE TABLE

PACKAGE

DESIGNATOR

PACKAGE TYPE

(

C/W)

(

C/W)

SOIC-16

50 to 120(1)

SOICW-16

50 to 100(1)

CDIP-16

80 to 120

CLCC-20

70 to 80

SSOP-16

144 to 172(2)

PDIP-16

90(1)

TSSOP-16

123 to 147(2)

PLCC-20

43 to 75(1)

(1) Specified

JA (junction to ambient) is for devices mounted to 5 in2 FR4 PC board

with one ounce copper where noted. When resistance range is given, lower values
are for 5 in2 aluminum PC board. Test PWB was 0.062 in thick and typically used
0.635 mm trace widths for power packages and 1.3 mm trace widths for non-power
packages with a 100x100 mil probe land area at the end of each trace.

(2) Modeled data. If value range given for

JA, the lower value is for 3x3 inch1 oz

internal copper ground plane, and the higher value is for 1x1 inch ground plane. All
model data assumes only one trace for each non-fused lead.

UCC1806

UCC2806

UCC3806

SLUS272C - FEBRUARY 2000 - REVISED JUNE 2003

www.ti.com

TERMINAL FUNCTIONS

TERMINAL

PACKAGES

I/O

DESCRIPTION

NAME

D/DW/J/M

/N/PW

L,Q

I/O

DESCRIPTION

AOUT

High-current gate drive for the external MOSFETs

BOUT

High-current gate drive for the external MOSFETs

COMP

Output of the error amplifier

CS-

Inverting input of the 3

, differential current sense amplifier

CS+

Non-inverting input of the 3

, differential current sense amplifier

Oscillator timing capacitor connection point

CURLIM

Programs the primary current limit threshold that determins latching or retry after an
overcurrent situation

GND

Reference ground and power ground for all functions of this device

INV

Inverting input of the error amplifier.

Non-nverting input of the error amplifier.

Connection point for the oscillator timing resistor

SHUTDOWN

Provided for enhanced protection. When SHUTDOWN is driven above 1 V, AOUT and
BOUT are forced low.

SYNC

I/O

Allows providing external synchronization with TTL compatible thresholds.

Input supply connection for the FET drive outputs.

VIN

Input supply connection for this device.

VREF

Reference output.

DETAILED PIN DESCRIPTIONS

AOUT and BOUT: AOUT and BOUT provide alternating high current gate drive for the external MOSFETs. Duty
cycle can be varied from 0% to 50% where minimum dead time is a function of CT. Both outputs use MOS
transistor switches with inherent anti-parallel body diodes to clamp voltage swings to the supply rails, allowing
operation without the use of clamp diodes.

COMP: COMP is the output of the error amplifier and the input of the PWM comparator. The error amplifier is
a low output impedance, 2-MHz operational amplifier which allows sinking or sourcing of current at the COMP
pin. The error amplifier is internally current limited, so that zero duty cycle can be commanded by externally
forcing COMP to GND.

CS-: CS- is the inverting input of the 3

differential current sense amplifier.

CS+: CS+ is the non-inverting input of the 3

differential current sense amplifier.

CT: CT is the oscillator timing capacitor connection point, which is charged by the current set by RT. CT is
discharged to GND through a 2.6-mA current sink. This causes a linear discharge of CT to 0 V which then
initiates the next switching cycle. Dead time occurs during the discharge of CT, forcing AOUT and BOUT low.
Switching frequency (f

) and dead time (t

) are approximated by:

)

and

961

(1)

UCC1806

UCC2806

UCC3806

SLUS272C - FEBRUARY 2000 - REVISED JUNE 2003

www.ti.com

DETAILED PIN DESCRIPTIONS (continued)

CURLIM: CURLIM programs the primary current limit threshold and determines whether the device latches off
or retries after an overcurrent condition. When a shutdown signal is generated, a 200-

A current source to

ground pulls down on CURLIM. If the voltage on the pin remains above 350 mV the device remains latched and
the power must be cycled to restart. If the voltage on the pin falls below 350 mV, the device attempts a restart.
The voltage threshold is typically set by a resistor divider from V

REF

to ground. To calculate the current limit

adjust voltage threshold the following equations can be used.

Current limit adjust latching mode voltage is calculated in equation (2)

REF

(R1

300

)

R1
R2

350 mV

Current limit adjust non-latching mode voltage is calculated in equation (3)

REF

(R1

)

R1
R2

350 mV

where

R1 is the resistance from the VREF to CURLIM

R2 is the resistance from CURLIM to GND

GND: GND is the reference ground and power ground for all functions of this part. Bypass and timing capacitors
should be connected as close as possible to GND.

RT: RT is the connection point for the oscillator timing resistor. It has a low impedance input and is nominally
at 1.25 V. The current through RT is mirrored to the timing capacitor pin, CT. This causes a linear charging of
CT from 0 V to 2.35 V. Note that the current mirror is limited to a maximum of 100

A so R

must be greater

than 12.5 k

SYNC: SYNC is a bi-directional pin, allowing or providing external synchronization with TTL compatible
thresholds. In a typical application RT is connected through a timing resistor to GND which allows the internal
oscillator to free run. In this mode SYNC outputs a TTL compatible pulse during the oscillator dead time (when
CT is being discharged). If RT is forced above 4.4 V, SYNC acts as an input with TTL compatible thresholds
and the internal oscillator is disabled. When SYNC is high, greater than 2 V the outputs are held active low.
When SYNC returns low, the outputs may be high until the on-time is terminated by the normal peak current
signal, a fault seen at SHUTDOWN or the next high assertion of SYNC. Multiple UCC3806s can be
synchronized by a single master UCC3806 or external clock.

VC: VC is the input supply connection for the FET drive outputs and has an input range from 2.5 V to 15 V. VC
should be capacitively bypassed for proper operation.

VIN: VIN is the input supply connection for this device. The UCC1806 has a maximum startup threshold of 8 V
and internally limited by means of a 15 V shunt regulator. The shunted supply current must be limited to 2.5 mA.
For proper operation, VIN must be bypassed to GND with at least a 0.01-

F ceramic capacitor

VREF: VREF is a 5.1 V

1% trimmed reference output with a 5 mA maximum available current. VREF must be

bypassed to GND with at least a 0.1-

F ceramic capacitor for proper operation.

(2)

(3)

UCC1806

UCC2806

UCC3806

SLUS272C - FEBRUARY 2000 - REVISED JUNE 2003

www.ti.com

FUNCTIONAL BLOCK DIAGRAM

UDG-99035

SYNC

4.4V

1.5 V

OSC

AOUT

BOUT

GND

Shutdown

Lockout

1.0 V

0.35 V

Current Limit

Restart

UVLO

15 V

5.1 V

Reference

Regulator

Reference Low

4.25 V

CURLIM

SHUT

VREF

0.5 V

Comparator

7.0 V

7.5 V

CS-

CS+

INV

COMP

VIN

200k

200

120

DOWN

UCC1806

UCC2806

UCC3806

SLUS272C - FEBRUARY 2000 - REVISED JUNE 2003

www.ti.com

TYPICAL CHARACTERISTICS

Figure 1.

1 k

-20

10 k

-45

135

180

100 k

1 M

10 M

ERROR AMPLIFIER GAIN AND PHASE

FREQUENCY

fOSC - Oscillator Frequency - Hz

Gain - dB

Phase -

Gain

Phase

Figure 2.

-55

-25

100

125

TJ - Junction Temperature -

OSCILLATOR FREQUENCY

JUNCTION TEMPERATURE

f OSC

- Oscillator Frequency - kHz

10 k

100 k

1 M

10 k

100 k

1 M

CT = 47 pF

CT = 100 pF

f OSC

- Oscillator Frequency - kHz

RT - Timing Resistance -

CT = 220 pF

CT = 2.2 nF

CT = 1.0 nF

CT = 470 pF

CT = 330 pF

Figure 3.

OSCILLATOR FREQUENCY

TIMING RESISTANCE

PACKAGING INFORMATION

Orderable Device

Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

MSL Peak Temp

(3)

5962-9457501MEA

ACTIVE

CDIP

None

A42 SNPB

Level-NC-NC-NC

5962-9457501Q2A

ACTIVE

LCCC

None

POST-PLATE

Level-NC-NC-NC

5962-9457501V2A

ACTIVE

LCCC

None

Call TI

Level-NC-NC-NC

5962-9457501VEA

ACTIVE

CDIP

None

Call TI

Level-NC-NC-NC

UCC1806J

ACTIVE

CDIP

None

A42 SNPB

Level-NC-NC-NC

UCC1806J883B

ACTIVE

CDIP

None

A42 SNPB

Level-NC-NC-NC

UCC1806JQMLV

ACTIVE

CDIP

None

Call TI

UCC1806L

ACTIVE

LCCC

None

POST-PLATE

Level-NC-NC-NC

UCC1806L883B

ACTIVE

LCCC

None

POST-PLATE

Level-NC-NC-NC

UCC1806LQMLV

ACTIVE

LCCC

None

Call TI

UCC2806D

ACTIVE

SOIC

None

CU NIPDAU

Level-1-220C-UNLIM

UCC2806DTR

ACTIVE

SOIC

2500

None

CU NIPDAU

Level-1-220C-UNLIM

UCC2806DW

ACTIVE

SOIC

None

CU NIPDAU

Level-2-220C-1 YEAR

UCC2806DWTR

ACTIVE

SOIC

2000

None

CU NIPDAU

Level-2-220C-1 YEAR

UCC2806J

ACTIVE

CDIP

None

A42 SNPB

Level-NC-NC-NC

UCC2806M

ACTIVE

SSOP/

QSOP

DBQ

None

CU NIPDAU

Level-2-220C-1 YEAR

UCC2806MTR

ACTIVE

SSOP/

QSOP

DBQ

2500

None

CU NIPDAU

Level-2-220C-1 YEAR

UCC2806N

ACTIVE

PDIP

None

CU SNPB

Level-NA-NA-NA

UCC2806PW

ACTIVE

TSSOP

None

CU NIPDAU

Level-2-220C-1 YEAR

UCC2806PWTR

ACTIVE

TSSOP

2000

None

CU NIPDAU

Level-2-220C-1 YEAR

UCC2806PWTRG4

ACTIVE

TSSOP

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

UCC2806Q

ACTIVE

PLCC

None

CU SNPB

Level-2-220C-1 YEAR

UCC2806QTR

ACTIVE

PLCC

1000

None

CU SNPB

Level-2-220C-1 YEAR

UCC3806DW

ACTIVE

SOIC

None

CU NIPDAU

Level-2-220C-1 YEAR

UCC3806DWTR

ACTIVE

SOIC

2000

None

CU NIPDAU

Level-2-220C-1 YEAR

UCC3806J

ACTIVE

CDIP

None

A42 SNPB

Level-NC-NC-NC

UCC3806N

ACTIVE

PDIP

None

CU SNPB

Level-NA-NA-NA

UCC3806PW

ACTIVE

TSSOP

None

CU NIPDAU

Level-2-220C-1 YEAR

UCC3806PWTR

ACTIVE

TSSOP

2000

None

CU NIPDAU

Level-2-220C-1 YEAR

UCC3806Q

ACTIVE

PLCC

None

CU SNPB

Level-2-220C-1 YEAR

UCC3806QTR

ACTIVE

PLCC

1000

None

CU SNPB

Level-2-220C-1 YEAR

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check

http://www.ti.com/productcontent

for the latest availability information and additional

product content details.
None: Not yet available Lead (Pb-Free).

PACKAGE OPTION ADDENDUM

www.ti.com

8-Mar-2005

Addendum-Page 1

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com

8-Mar-2005

Addendum-Page 2

MECHANICAL DATA

MLCC006B OCTOBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

4040140 / D 10/96

28 TERMINAL SHOWN

0.358

(9,09)

MAX

(11,63)

0.560

(14,22)

0.560

0.458

0.858

(21,8)

1.063

(27,0)

(14,22)

NO. OF

MIN

MAX

0.358

0.660

0.761

0.458

0.342

(8,69)

MIN

(11,23)

(16,26)

0.640

0.739

0.442

(9,09)

(11,63)

(16,76)

0.962

1.165

(23,83)

0.938

(28,99)

1.141

(24,43)

(29,59)

(19,32)

(18,78)

0.020 (0,51)

TERMINALS

0.080 (2,03)
0.064 (1,63)

(7,80)

0.307

(10,31)

0.406

(12,58)

0.495

(12,58)

0.495

(21,6)

0.850

(26,6)

1.047

0.045 (1,14)

0.035 (0,89)

0.010 (0,25)

0.020 (0,51)
0.010 (0,25)

B SQ

A SQ

0.055 (1,40)

0.045 (1,14)

0.028 (0,71)
0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.

E. Falls within JEDEC MS-004

MECHANICAL DATA

MPLC004A OCTOBER 1994

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

FN (S-PQCC-J**)

PLASTIC J-LEADED CHIP CARRIER

4040005 / B 03/95

20 PIN SHOWN

0.026 (0,66)

0.032 (0,81)

D2 / E2

0.020 (0,51) MIN

0.180 (4,57) MAX

0.120 (3,05)

0.090 (2,29)

D2 / E2

0.013 (0,33)

0.021 (0,53)

Seating Plane

MAX

D2 / E2

0.219 (5,56)

0.169 (4,29)

0.319 (8,10)

0.469 (11,91)

0.569 (14,45)

0.369 (9,37)

MAX

0.356 (9,04)

0.456 (11,58)

0.656 (16,66)

0.008 (0,20) NOM

1.158 (29,41)

0.958 (24,33)

0.756 (19,20)

0.191 (4,85)

0.141 (3,58)

MIN

0.441 (11,20)

0.541 (13,74)

0.291 (7,39)

0.341 (8,66)

MIN

MAX

MIN

PINS

0.385 (9,78)

0.485 (12,32)

0.685 (17,40)

1.185 (30,10)

0.985 (25,02)

0.785 (19,94)

D / E

0.395 (10,03)

0.495 (12,57)

1.195 (30,35)

0.995 (25,27)

0.695 (17,65)

0.795 (20,19)

NO. OF

D1 / E1

0.350 (8,89)

0.450 (11,43)

1.150 (29,21)

0.950 (24,13)

0.650 (16,51)

0.750 (19,05)

0.004 (0,10)

0.007 (0,18)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

MECHANICAL DATA

MTSS001C JANUARY 1995 REVISED FEBRUARY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

0,10

0,25

0,50

0,75

0,15 NOM

Gage Plane

9,80

9,60

7,90

7,70

6,60

6,40

4040064/F 01/97

0,30

6,60
6,20

0,19

4,30

4,50

0,15

1,20 MAX

5,10

4,90

3,10

2,90

A MAX

A MIN

DIM

PINS **

0,05

4,90

5,10

Seating Plane

 8

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

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