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FEATURES
APPLICATIONS
DESCRIPTION
TYPICAL APPLICATION
1
2
3
4
8
7
6
5
VCC
DRV
GND
ZCD
VO_SNS
COMP
MULTIN
CS
UCC28051
1
2
3
4
8
7
6
5
STATUS
OVP
VDD
OUT
SS
FB
CS
GND
UCC28600
Primary
Secondary
TL431
Feedback
18 V
C
DD
R
DD
R
SU
R
OVP1
R
OVP2
M
1
Q
ST
R
ST2
R
ST1
C
SS
C
BP
R
PL
R
CS
C
BULK
N
P
N
S
N
B
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
8-PIN QUASI-RESONANT FLYBACK GREEN-MODE CONTROLLER
Bias Supplies for LCD-Monitors, LCD-TV,
Green-Mode Controller With Advanced
PDP-TV, and Set Top Boxes
Energy Saving Features
AC/DC Adapters and Offline Battery Chargers
Quasi-Resonant Mode Operation for Reduced
Energy Efficient Power Supplies up to 200 W
EMI and Low Switching Losses (Low Voltage
Switching)
Low Standby Current for System No-Load
Power Consumption to 150 mW
The UCC28600 is a PWM controller with advanced
energy features to meet stringent world-wide energy
Low Startup Current: 25
A Maximum
efficiency requirements.
Programmable Overvoltage Protection, Line
UCC28600
integrates
built-in
advanced
energy
and Load
saving features with high level protection features to
Internal Overtemperature Protection:
provide cost effective solutions for energy efficient
Prevents Restart Until Temperature Fault
power supplies. UCC28600 incorporates frequency
Cleared
fold back and burst mode operation to reduce the
Current Limit Protection
operation frequency at light load and no load
operations.
Cycle-by-Cycle Power Limit
Overcurrent Hiccup Restart Mode
UCC28600 is offered in the 8-pin SOIC (D) package.
Operating temperature range is -40
C to 105
C.
1-A Sink TrueDriveTM, -0.75-A Source Gate
Drive Output
Programmable Soft-Start
Greenmode STATUS pin (PFC Disable
Function)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TrueDrive is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 20052006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
over operating free-air temperature range unless otherwise noted
(1)
UCC28600
UNIT
V
DD
Supply voltage range
I
DD
< 20 mA
32
V
I
DD
Supply current
20
mA
I
OUT(sink)
Output sink current (peak)
1.2
A
I
OUT(source)
Output source current (peak)
-0.8
Analog inputs
FB, CS, SS
-0.3 to 6.0
V
V
OVP
-1.0 to 6.0
I
OVP(source)
-1.0
mA
V
STATUS
VDD = 0 V to 30 V
30
V
Power dissipation
SOIC-8 package, T
A
= 25
C
650
mW
T
J
Operating junction temperature range
55 to 150
T
stg
Storage temperature
65 to 150
C
T
LEAD
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
300
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages
are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the databook
for thermal limitations and considerations of packages.
MIN
NOM
MAX
UNIT
V
DD
Input voltage
21
V
I
OUT
Output sink current
0
A
T
J
Operating junction temperature
-55
150
C
MIN
MAX
UNIT
Human body model
2000
V
CDM
1500
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ELECTRICAL CHARACTERISTICS
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
VDD = 15 V, 0.1-
F capacitor from VDD to GND, 3.3-nF capacitor from SS to GND charged over 3.5 V, 500-
resistor from
OVP to -0.1 V, FB = 4.8 V, STATUS = not connected, 1-nF capacitor from OUT to GND, CS = GND, T
A
= T
J
= -40
C to
105
C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Overall
I
STARTUP
Startup current
V
DD
= V
UVLO
-0.3 V
12
25
A
I
STANDBY
Standby current
V
FB
= 0 V
350
550
Not switching
2.5
3.5
I
DD
Operating current
mA
130 kHz, QR mode
5.0
7.0
VDD clamp
FB = GND, I
DD
= 10 mA
21
26
32
V
Undervoltage Lockout
V
DD(uvlo)
Startup threshold
10.3
13.0
15.3
Stop threshold
6.3
8
9.3
V
Hysteresis
4.0
5.0
6.0
PWM (Ramp)
(1)
D
MIN
Minimum duty cycle
V
SS
= GND, V
FB
= 2 V
0%
D
MAX
Maximum duty cycle
QR mode, f
S
= max, (open loop)
99%
Oscillator (OSC)
f
QR(max)
Maximum QR frequency
117
130
143
f
QR(min)
Minimum QR and FFM frequency
V
FB
= 1.3 V
32
40
48
kHz
f
SS
Soft start frequency
V
SS
= 2.0 V
32
40
48
dT
S
/dFB
VCO gain
T
S
for 1.6 V < V
FB
< 1.8 V
-38
-30
-22
s/V
Feedback (FB)
Feedback pullup resistor
12
20
28
k
FB, no load
QR mode
3.30
4.87
6.00
Green-mode ON threshold
V
FB
threshold
0.3
0.5
0.7
Green-mode OFF threshold
V
FB
threshold
1.2
1.4
1.6
Green-mode hysteresis
V
FB
threshold
0.7
0.9
1.1
V
FB threshold burst-ON
V
FB
during green mode
0.3
0.5
0.7
FB threshold burst-OFF
V
FB
during green mode
0.5
0.7
0.9
Burst Hysteresis
V
FB
during green mode
0.13
0.25
0.42
Status
STATUS R
DS(on)
V
STATUS
= 1 V
1.0
2.4
3.8
k
STATUS leakage/off current
V
FB
= 0.44 V, V
STATUS
= 15 V
-0.1
2.0
A
(1)
R
SCT
and C
CST
are not connected in the circuit for maximum and minimum duty cycle tests, current sense tests and power limit tests.
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UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
ELECTRICAL CHARACTERISTICS (continued)
VDD = 15 V, 0.1-
F capacitor from VDD to GND, 3.3-nF capacitor from SS to GND charged over 3.5 V, 500-
resistor from
OVP to -0.1 V, FB = 4.8 V, STATUS = not connected, 1-nF capacitor from OUT to GND, CS = GND, T
A
= T
J
= -40
C to
105
C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Current Sense (CS)
(2)
A
CS(FB)
Gain, FB =
V
FB
/
V
CS
QR mode
2.5
V/V
Shutdown threshold
V
FB
= 2.4 V, V
SS
= 0 V
1.13
1.25
1.38
V
CS to output delay time (power limit)
CS = 1.0 V
PULSE
100
175
300
ns
CS to output delay time (over current fault)
CS = 1.45 V
PULSE
50
100
150
CS discharge impedance
CS = 0.1 V, V
SS
= 0 V
25
115
250
CS offset
SS mode, V
SS
2.0 V, via FB
0.35
0.40
0.45
V
Power Limit (PL)
(2)
CS current
OVP = -300
A
-165
-150
-135
A
CS working range
QR mode, peak CS voltage
0.70
0.81
0.92
V
PL threshold
Peak CS voltage + CS offset
1.05
1.20
1.37
Soft Start (SS)
I
SS(chg)
Softstart charge current
V
SS
= GND
-8.3
-6.0
-4.5
A
I
SS(dis)
Softstart discharge current
V
SS
= 0.5 V
2.0
5.0
10
mA
V
SS
Switching ON threshold
Output switching start
0.8
1.0
1.2
V
Overvoltage Protection (OVP)
OVP
(line)
Line overvoltage protection
I
OVP
threshold, OUT = HI
-512
-450
-370
A
OVP voltage at OUT = HIGH
V
FB
= 4.8 V, V
SS
= 5.0 V, I
OVP
, = -300
A
-125
-25
mV
OVP
(load)
Load overvoltage protection
V
OVP
threshold, OUT = LO
3.37
3.75
4.13
V
Thermal Protection (TSD)
Thermal shutdown (TSP) temperature
(3)
130
140
150
C
Thermal shutdown hysteresis
15
OUT
t
RISE
Rise time
10% to 90% of 13 V typical out clamp
50
75
ns
t
FALL
Fall time
10
20
(2)
R
SCT
and C
CST
are not connected in the circuit for maximum and minimum duty cycle tests, current sense tests and power limit tests.
(3)
Ensured by design. Not production tested.
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OPEN LOOP TEST CIRCUIT
STATUS
GND
V
FB
V
CS
V
OVP
V
OUT
V
DD
I
DD
I
OVP
R
OVP
500
C
OUT
1.0 nF
R
OUT
10
C
BIAS
1
F
C
DD
100 nF
I
CS
C
FB
47 pF
C
SS
3.3 nF
C
CST
560 pF
See Note
R
CST
37.4 k
See Note
SS
VDD
GND
OUT
FB
CS
OVP
STATUS
UCC28600
+
1
2
3
4
5
6
7
8
5 V
BLOCK DIAGRAM/TYPICAL APPLICATION
2
1
6
5.0
VREF
SS
VDD
4
GND
5
OUT
FB
1.5R
8
3
CS
UVLO
+
Feedback
From Auxiliary
Winding
20K
7
OVP
On-Chip
Thermal
Shutdown
REF
26V
13V
R
STATUS
13/8V
+
400 mV
REF
+
Q
Q
SET
CLR
D
REF
GAIN = 1/2.5
+
Modulation
Comparison
VDD
UCC28600
Fault Logic
LINE_OVP
LOAD_OVP
REF_OK
RUN
UVLO
CS
OVR_T
STATUS
SS_DIS
Green Mode
FB_CLAMP
OSC_CL
FB
QR Detect
LOAD_OVP
LINE_OVP
QR_DONE
OUT
CS
Oscillator
QR_DONE
CLK
RUN
SS_OVR
OSC_CL
1.2V
SS_OVR
BURST
BURST
R
SU
PL
R
DD
R
OVP1
R
OVP2
C
BULK
C
SS
R
CS
R
PL
C
DD
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
NOTE:
R
CST
and C
CST
are not connected for maximum and minimum duty cycle tests,
current sense tests and power limit tests.
5
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DEVICE INFORMATION
1
2
3
4
8
7
6
5
SS
FB
CS
GND
STATUS
OVP
VDD
OUT
UCC28600
D PACKAGE
(TOP VIEW)
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
ORDERING INFORMATION
T
A
PACKAGES
PART NUMBER
-40
C to 105
C
SOIC (D)
(1)
UCC28600D
(1)
SOIC (D) package is available taped and reeled by adding "R" to the above part numbers. Reeled quantities for UCC28600DR is 2,500
devices per reel.
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Current sense input. Also programs power limit, and used to control modulation and activate overcurrent
CS
3
I
protection. The CS voltage input originates across a current sense resistor and ground. Power limit is
programmed with an effective series resistance between this pin and the current sense resistor.
Feedback input or control input from the optocoupler to the PWM comparator used to control the peak current
in the power MOSFET. An internal 20-k
resistor is between this pin and the internal 5-V regulated voltage.
FB
2
I
Connect the collector of the photo-transistor of the feedback optocoupler directly to this pin; connect the
emitter of the photo-transistor to GND. The voltage of this pin controls the mode of operation in one of the
three modes: quasi resonant (QR), frequency foldback mode (FFM) and green mode (GM).
Ground for internal circuitry. Connect a ceramic 0.1-
F bypass capacitor between VDD and GND, with the
GND
4
-
capacitor as close to these two pins as possible.
1-A sink (TrueDriveTM ) and 0.75-A source gate drive output. This output drives the power MOSFET and
OUT
5
O
switches between GND and the lower of VDD or the 13-V internal output clamp.
Over voltage protection (OVP) input senses line-OVP, load-OVP and the resonant trough for QR turn-on.
OVP
7
I
Detect line, load and resonant conditions using the primary bias winding of the transformer, adjust sensitivity
with resistors connected to this pin.
Soft-start programming pin. Program the soft-start rate with a capacitor to ground; the rate is determined by
the capacitance and the internal soft-start charge current. All faults discharge the SS pin to GND through an
SS
1
I
internal MOSFET with an R
DS(on)
of approximately 100
. The internal modulator comparator reacts to the
lowest of the SS voltage, the internal FB voltage and the peak current limit. Typically, T
SS
= 1.5 ms for C
SS
=
3.3 nF.
ACTIVE HIGH open drain signal that indicates the device has entered standby mode. This pin can be used to
STATUS
8
O
disable the PFC control circuit (high impedance = green mode). STATUS pin is high during UVLO, (V
DD
<
startup threshold), and softstart, (SS < FB).
Provides power to the device. Use a ceramic 0.1-
F by-pass capacitor for high-frequency filtering of the VDD
VDD
6
I
pin, as described in the GND pin description. Operating energy is usually delivered from auxiliary winding. To
prevent hiccup operation during start-up, a larger energy storage cap is also needed between VDD and GND.
6
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R
CS
+
V
PL
*
V
CS(os)
I
CS(2)
*
I
CS(1)
I
CS(2)
I
P(1)
*
I
CS(1)
I
P(2)
R
PL
+
V
PL
*
V
CS(os)
I
P(2)
*
I
P(1)
I
CS(1)
I
P(2)
*
I
CS(2)
I
P(1)
R
OVP1
+
1
I
OVP(lineth)
N
B
N
P
V
BULK(ov)
R
OVP2
+
R
OVP1
V
OVP(load th)
N
B
N
S
V
OUT(ov)
)
V
F
*
V
OVP(load th)
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
TERMINAL COMPONENTS
TERMINAL
I/O
DESCRIPTION
(1) (2) (3)
NAME
NO.
CS
3
I
where:
I
P1
is the peak primary current at low line, full load
I
P2
is the peak primary current at high line, full load
I
CS1
is the power limit current that is sourced at the CS pin at low-line voltage
I
CS2
is the power limit current that is sourced at the CS pin at high-line voltage
V
PL
is the Power Limit (PL) threshold
V
CS(os)
is the CS offset voltage
FB
2
I
Opto-isolator collector
GND
4
-
Bypass capacitor to VDD, C
BP
= 0.1
F
OUT
5
O
Power MOSFET gate
OVP
7
I
where:
I
OVP(line th)
is OVP
line
current threshold
V
BULK(ov)
is the allowed input over- voltage level
V
OVP(load_th)
is OVP
load
V
OUT(ov)
is the allowed output over-voltage level
V
F
is the forward voltage of the secondary rectifier
N
B
is the number of turns on the bias winding
N
S
is the number of turns on the secondary windings
N
P
is the number of turns on the primary windings
(1)
Refer to
Figure 1
for all reference designators in the Terminal Components Table.
(2)
Refer to the Electrical Characteristics Table for constant parameters.
(3)
Refer to the UCC28600 Design Calculator (TI Literature Number SLVC104) or laboratory measurements for currents, voltages and times
in the operational circuit.
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C
SS
u
I
SS
t
SS(min)
(due power limit)
A
CS(FB)
V
PL
*
V
CS(os)
t
SS(min)
+
*
R
OUT(ss)
C
OUT
2
n 1
*
V
OUT
* D
V
OUT(step)
2
R
OUT(ss)
P
LIM
t
SS(min)
+
C
OUT
V
OUT
2
2 P
LIM
R
ST2
+
V
BE(off)
I
STATUS(leakage)
R
ST1
+
R
ST2
V
DD(uvlo
*
on)
*
V
BE(sat)
*
R
DS(on)
I
CC
b
sat
*
R
DS(on)
V
BE(sat)
I
CC
b
sat
R
ST2
)
V
BE(sat)
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
TERMINAL COMPONENTS (continued)
TERMINAL
I/O
DESCRIPTION
(1) (2) (3)
NAME
NO.
where t
SS(min)
is the greater of:
SS
1
I
or
R
OUT(ss)
is the effective load impedance during soft-start
V
OUT(step)
is the allowed change in V
OUT
due to a load step
P
LIM
is the programmed power limit level, in W
A
CS(FB)
is the current sense gain.
V
CS(os)
is the CS offset voltage
STATUS
8
O
where:
SAT
is the gain of transistor Q
ST
in saturation
V
BE(sat)
is the base-emitter voltage of transistor Q
ST
in saturation
V
DD(uvlo-on)
is the startup threshold
I
CC
is the collector current of Q
ST
I
STATUS(leakage)
is the maximum leakage/off current of the STATUS pin
V
BE(off)
is the maximum allowable voltage across the base emitter junction that will not turn Q
ST
on
R
DS(on)
is the R
DS(on)
of STATUS
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C
DD
+
I
DD
)
C
ISS
V
OUT(hi)
f
QR(max)
T
BURST
D
V
DD(burst)
C
DD
+
I
DD
)
C
ISS
V
OUT(hi)
f
QR(max)
t
SS
D
V
DD(uvlo)
R
DD
+
p
4
N
B
N
P
V
DS1(os)
f
QR(max)
L
LEAKAGE
C
D
)
C
SNUB
I
DD
)
C
ISS
V
OUT(hi)
f
QR(max)
R
SU
+
V
BULK(min)
I
STARTUP
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
TERMINAL COMPONENTS (continued)
TERMINAL
I/O
DESCRIPTION
(1) (2) (3)
NAME
NO.
C
DD
is the greater of:
or
VDD
6
I
where:
I
DD
is the operating current of the UCC28600
C
ISS
is the input capacitance of MOSFET M
1
V
OUT(hi)
is VOH of the OUT pin, either 13 V (typ) V
OUT
clamp or as measured
f
QR(max)
is f
S
at high line, maximum load
T
BURST
is the measured burst mode period
V
DD(burst)
is the UVLO-allowed V
DD
ripple during burst mode
V
DD(uvlo)
is the UVLO hysteresis, equal to V
DD
or 13 V whichever is less
V
DS1(os)
is the amount of drain-source overshoot voltage
L
LEAKAGE
is the leakage inductance of the primary winding
C
D
is the total drain node capacitance of MOSFET M
1
I
STARTUP
is I
DD
start-up current of the UCC28600
C
SNUB
is the snubber capacitor value
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FEEDBACK
TL431
2
1
6
SS
VDD
4
GND
5
OUT
FB
8
3
CS
7
OVP
STATUS
UCC28600
PRIMARY
SECONDARY
+
-
+
-
PFC OUTPUT
or
BRIDGE RECTIFIER
PFC CONTROLLER BIAS
(if used)
C
BULK
V
BULK
R
SU
R
SNUB
C
SNUB
R
DD
C
DD
R
OVP1
R
OVP2
N
P
N
B
N
S
C
OUT
V
OUT
R
OUT
M
1
C
SS
I
CC
Q
ST
R
ST1
R
ST2
C
BP
100 nF
R
PL
R
CS
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
Figure 1. Pin Termination Schematic
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APPLICATION INFORMATION
Functional Description
0.5V
0.7V
1.4V
2.0V
5.0V
0V
Green Mode
FFM
QR Mode or DCM Mode
V
FB
V
F
B
Control Range Limit
Internal Reference
Green Mode = OFF
,
Burst = OFF
Green Mode = ON,
Burst = ON
Burst
Hysteresis
Green Mode
Hysteresis
40 kHz
3
f
S
3
130 kHz
3.0V
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
The UCC28600 is a multi-mode controller, as illustrated in
Figure 3
and
Figure 4
. The mode of operation
depends upon line and load conditions. Under all modes of operation, the UCC28600 terminates the OUT = HI
signal based on the switch current. Thus, the UCC28600 always operates in current mode control so that the
power MOSFET current is always limited.
Under normal operating conditions, the FB pin commands the operating mode of the UCC28600 at the voltage
thresholds shown in
Figure 2
. Soft-start and fault responses are the exception. Soft-start mode hard-switch
controls the converter at 40 kHz. The soft-start mode is latched-OFF when V
FB
becomes less than V
SS
for the
first time after UVLO
ON
. The soft-start state cannot be recovered until after passing UVLO
OFF
, and then,
UVLO
ON
.
At normal rated operating loads (from 100% to approximately 30% full rated power) the UCC28600 controls the
converter in quasi-resonant mode (QRM) or discontinuous conduction mode (DCM), where DCM operation is at
the clamped maximum switching frequency (130 kHz). For loads that are between approximately 30% and 10%
full rated power, the converter operates in frequency foldback mode (FFM), where the peak switch current is
constant and the output voltage is regulated by modulating the switching frequency. Effectively, operation in
FFM results in the application of constant volt-seconds to the flyback transformer each switching cycle. Voltage
regulation in FFM is achieved by varying the switching frequency in the range from 130 kHz to 40 kHz. For
extremely light loads (below approximately 10% full rated power), the converter is controlled using bursts of
40-kHz pulses. Keep in mind that the aforementioned boundaries of steady-state operation are approximate
because they are subject to converter design parameters.
Refer to the typical applications block diagram for the electrical connections to implement the features.
Figure 2. Mode Control with FB Pin Voltage
11
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START
Vcc > 13V?
Soft Start
Freq. Foldback
(Light Load)
Quasi-Resonant
Mode or DCM
(Normal Load)
Vcc < 8V?
REF < 4V?
OVP = Logic High?
OT = Logic High?
OC = Logic High
RUN = Logic High
STATUS = Hi Z
Y
N
N
Y
RUN = Logic Low
STATUS = Hi Z
40kHz Burst
RUN = Logic Low
Y
N
40kHz
Zero Pulses
STATUS = Hi Z
(In Green-Mode)
STATUS = 0V
(In Run-Mode)
STATUS = 0V
(In Run-Mode)
STATUS = 0V
(In Run-Mode)
N
N
Y
Y
Fixed V/s
Fixed V/s
Fixed V/s
Continuous
Fault Monitor
Monitor V
FB
V
FB
> 2.0 V
V
FB
> 0.7 V
V
FB
> 1.4 V
V
FB
< 0.5 V
V
FB
< 0.4 V
1.4 V < V
FB
< 2.0 V
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
Figure 3. Control Flow Chart
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fsw
QR Mode
Switching
Frequency
Feedback
V
oltage
Power Supply
Output V
oltage
t
t
t
(40 kHz)
This mode applies bursts of
40kHz soft-start pulses to the
power MOSFET gate. The
average fsw is shown in this
operating mode.
DCM
(maximum fs)
IC Off Softstart
Regular Operation
Green Mode
Peak MOSFET
Current
t
Fixed Frequency
Status, pulled up
to VDD
t
Green Mode,
PFC bias OFF
Load Power
t
f
MAX
=
Oscillator Frequency
(130 kHz)
SS Mode
(Fixed f
SW
)
f
SS
V
FB
V
OUT
V
STATUS
Load shown is slightly
less than overcurrent
threshold
P
OUT, (max)
P
OUT
f
GRMODE_MX
(40 kHz)
f
QR_MIN
Internally Limit-
ed to 40 kHz
Hysteretic
Transition into
Green Mode
Frequency
Foldback
(Valley Switching, VS)
(VS)
FFM, (VS)
Green Mode
Burst Hysteresis
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
Figure 4. Operation Mode Switching Frequencies
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OSC_CL
QR_DONE
4.0V
0.1V
SS_OVR
REF
S
Q
Q
R
CLK
130 kHz OSC
Clamp
Comparator
OSC Valley
Comparator
OSC Peak
Comparator
RUN
+
+
+
Oscillator
+
+
+
FB_CL
OSC_CL
FB
1.4 V
2.0 V
450 k
450 k
100 k
100 k
Mode Clamps
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
Details of the functional boxes in the Block Diagram/Typical Application drawing are shown in
Figure 5
,
Figure 6
,
Figure 7
and
Figure 8
. These figures conceptualize how the UCC28600 executes the command of the FB
voltage to have the responses that are shown in
Figure 2
,
Figure 3
and
Figure 4
. The details of the functional
boxes also conceptualize the various fault detections and responses that are included in the UCC28600. During
all modes of operation, this controller operates in current mode control. This allows the UCC28600 to monitor
the FB voltage to determine and respond to the varying load levels such as heavy, light or ultra-light.
Quasi-resonant mode and DCM occurs for feedback voltages V
FB
between 2.0 V and 4.0 V, respectively. In turn,
the CS voltage is commanded to be between 0.4 V and 0.8 V. A cycle-by-cycle power limit imposes a fixed
0.8-V limit on the CS voltage. An overcurrent shutdown threshold in the fault logic gives added protection
against shorted winding faults, shown in
Figure 8
. The power limit feature in the QR DETECT circuit of
Figure 7
adds an offset to the CS signal that is proportional to the line voltage. The power limit feature is programmed
with R
PL
, as shown in the typical applications diagram.
Figure 5. Oscillator Details
Figure 6. Mode Clamp Details
14
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Auxiliary
Winding
+
+
+
+
7
Slope
+
0.1 V
0.1 V
-0.1 V
REF (5 V)
3.75 V
0.45 V
QR_DONE
(Oscillator)
LOAD_OVP
(Fault Logic)
LINE_OVP
(Fault Logic)
REF (5 V)
3
CS
OVP
VDD
OUT (From Driver)
UCC28600
CS
Power Limit
Offset
Burst
(from FAULT
logic)
0
1
+
QR Detect
R
PL
R
CS
1 k
I
LINE
I
LINE
I
LINE
2
R
SU
R
OVP1
R
OVP2
N
B
N
P
N
S
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
Figure 7. QR Detect Details
15
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S
Q
Q
R
REF
D
Q
Q
CLR
SET
Power-Up Reset
Thermal
Shutdown
+
+
1.25 V
+
SS/DIS
RUN
3
CS
OVR_T
LINE_OVP
(QR Detect)
LOAD_OVP
(QR Detect)
UVLO
REF_OK
Burst
REF
(5 V)
FB
7
FB
CS
SS_OVR
STATUS
8
UCC28600
BURST
Over-Current
Shutdown
20 k
Fault Logic
0.5 V/0.7 V
0.5 V/1.4 V
Quasi-Resonant / DCM Control
Frequency Foldback Mode Control
Green-Mode Control
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
Figure 8. Fault Logic Details
Quasi-resonant (QR) and DCM operation occur for feedback voltages V
FB
between 2.0 V and 4.0 V. In turn, the
peak CS voltage is commanded to be between 0.4 V and 0.8 V. During this control mode, the rising edge of
OUT always occurs at the valley of the resonant ring after demagnetization. Resonant valley switching is an
integral part of QR operation. Resonant valley switching is also imposed if the system operates at the maximum
switching frequency clamp. In other words, the frequency varies in DCM operation in order to have the switching
event occur on the first resonant valley that occurs after a 7.7-
s (130-kHz) interval. Notice that the CS pin has
an internal dependent current source, 1/2 I
LINE
. This current source is part of the cycle-by-cycle power limit
function that is discussed in the Protection Features section.
Frequency foldback mode uses elements of the FAULT LOGIC, shown in
Figure 8
and the mode clamp circuit,
shown in
Figure 6
. At the minimum operating frequency, the internal oscillator sawtooth waveform has a peak of
4.0 V and a valley of 0.1 V. When the FB voltage is between 2.0 V and 1.4 V, the FB_CL signal in
Figure 6
commands the oscillator in a voltage controlled oscillator (VCO) mode by clamping the peak oscillator voltage.
The additional clamps in the OSCILLATOR restrict VCO operation between 40 kHz and 130 kHz. The FB_CL
voltage is reflected to the modulator comparator effectively clamping the reflected CS command to 0.4 V.
Green mode uses element of the fault logic, shown in
Figure 8
and the mode clamps circuit, shown in
Figure 6
.
The OSC_CL signal clamps the Green-mode operating frequency at 40 kHz. Thus, when the FB voltage is
between 1.4 V and 0.5 V, the controller is commanding an excess of energy to be transferred to the load which
in turn, drives the error higher and FB lower. When FB reaches 0.5 V, OUT pulses are terminated and do not
resume until FB reaches 0.7 V. In this mode, the converter operates in hysteretic control with the OUT pulse
terminated at a fixed CS voltage level of 0.4 V. The power limit offset is turned OFF during Green mode and it
returns to ON when FB is above 1.4 V, as depicted in
Figure 8
. Green mode reduces the average switching
frequency in order to minimize switching losses and increase the efficiency at light load conditions.
16
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Fault Logic
Oscillator
Status
8
5
VCC
GND
UCC28051
2
4
8
6
STATUS
VDD
FB
GND
UCC28600
Primary
Secondary
10 V
TL431
Feedback
M1
To Zero
Current
Detection
M2
D
Z1
C
CC
R
CC
C
BULK
R
SU
R
CS
0.1
F
R
ST2
R
ST1
Q
ST
N
P
N
S
N
B
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
Advanced logic control coordinates the fault detections to provide proper power supply recovery. This provides
the conditioning for the thermal protection. Line overvoltage protection (line OVP) and load OVP are
implemented in this block. It prevents operation when the internal reference is below 4.5 V. If a fault is detected
in the thermal shutdown, line OVP, load OVP, or REF, the UCC28600 undergoes a shutdown/retry cycle.
Refer to the fault logic diagram in
Figure 8
and the QR detect diagram in
Figure 7
to program line OVP and load
OVP. To program the load OVP, select the R
OVP1
R
OVP2
divider ratio to be 3.75 V at the desired output
shut-down voltage. To program line OVP, select the impedance of the R
OVP1
R
OVP2
combination to draw 450
A when the V
OVP
is 0.45 V during the ON-time of the power MOSFET at the highest allowable input voltage.
The oscillator, shown in
Figure 5
, is internally set and trimmed so it is clamped by the circuit in
Figure 5
to a
nominal 130-kHz maximum operating frequency. It also has a minimum frequency clamp of 40 kHz. If the FB
voltage tries to drive operation to less than 40 kHz, the converter operates in green mode.
The STATUS pin is an open drain output, as shown in
Figure 8
. The status output goes into the OFF-state when
FB falls below 0.5 V and it returns to the ON-state (low impedance to GND) when FB rises above 1.4 V. This pin
is used to control bias power for a PFC stage, as shown in
Figure 9
. Key elements for implementing this function
include Q
ST
, R
ST1
and R
ST2
, as shown in the figure. Resistors R
ST1
and R
ST2
are selected to saturate Q
ST
when it
is desirable for the PFC to be operational. During green mode, the STATUS pin becomes a high impedance and
R
ST1
causes Q
ST
to turn-OFF, thus saving bias power. If necessary, use a zener diode and a resistor (D
Z1
and
R
CC
) to maintain V
CC
in the safe operating range of the PFC controller.
Figure 9. Using STATUS for PFC Shut-Down During Green Mode
17
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Operating Mode Programming
Protection Features
Overtemperature
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
Boundaries of the operating modes are programmed by the flyback transformer and the four components R
PL
,
R
CS
, R
OVP1
and R
OVP2
; shown in the Block Diagram/Application drawing.
The transformer characteristics that predominantly affect the modes are the magnetizing inductance of the
primary and the magnitude of the output voltage, reflected to the primary. To a lesser degree (yet significant),
the boundaries are affected by the MOSFET output capacitance and transformer leakage inductance. The
design procedure here is to select a magnetizing inductance and a reflected output voltage that operates at the
DCM/CCM boundary at maximum load and maximum line. The actual inductance should be noticeably smaller
to account for the ring between the magnetizing inductance and the total stray capacitance measured at the
drain of the power MOSFET. This programs the QR/DCM boundary of operation. All other mode boundaries are
preset with the thresholds in the oscillator and green-mode blocks.
The four components R
PL
, R
CS
, R
OVP1
and R
OVP2
must be programmed as a set due to the interactions of the
functions. The use of the UCC28600 design calculator, TI Literature Number SLVC104, is highly recommended
in order to achieve the desired results with a careful balance between the transformer parameters and the
programming resistors.
The UCC28600 has many protection features that are found only on larger, full featured controllers. Refer to the
Block Diagram/Typical Application and Figures 1, 4, 5, 6 and 7 for detailed block descriptions that show how the
features are integrated into the normal control functions.
Overtemperature lockout typically occurs when the substrate temperature reaches 140
C. Retry is allowed if the
substrate temperature reduces by the hysteresis value. Upon an overtemperature fault, C
SS
on softstart is
discharged and STATUS is forced to a high impedance.
18
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Cycle-by-Cycle Power Limit
Current Limit
Over-Voltage Protection
Undervoltage Lockout
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
The cycle terminates when the CS voltage plus the power limit offset exceeds 0.8 V.
In order to have power limited over the full line voltage range of the QR Flyback converter, the CS pin voltage
must have a component that is proportional to the primary current plus a component that is proportional to the
line voltage due to predictable switching frequency variations due to line voltage. At power limit, the CS pin
voltage plus the internal CS offset is compared against a constant 1.2-V reference in the PWM comparator.
Thus during cycle-by-cycle power limit, the peak CS voltage is typically 0.8 V.
The current that is sourced from the OVP pin (I
LINE
) is reflected to a dependent current source of I
LINE
, that is
connected to the CS pin. The power limit function can be programmed by a resistor, R
PL
, that is between the CS
pin and the current sense resistor. The current, I
LINE
, is proportional to line voltage by the transformer turns ratio
N
B
/N
P
and resistor R
OVP1
. Current I
LINE
is programmed to set the line over voltage protection. Resistor R
PL
results in the addition of a voltage to the current sense signal that is proportional to the line voltage. The proper
amount of additional voltage has the effect of limiting the power on a cycle-by-cycle basis. Note that R
CS
, R
PL
,
R
OVP1
and R
OVP2
must be adjusted as a set due to the functional interactions.
When the primary current exceeds maximum current level which is indicated by a voltage of 1.25 V at the CS
pin, the device initiates a shutdown. Retry occurs after a UVLO
OFF
/UVLO
ON
cycle.
Line and load over voltage protection is programmed with the transformer turn ratios, R
OVP1
and R
OVP2
. The
OVP pin has a 0-V voltage source that can only source current; OVP cannot sink current.
Line over voltage protection occurs when the OVP pin is clamped at 0 V. When the bias winding is negative,
during OUT = HI or portions of the resonant ring, the 0-V voltage source clamps OVP to 0 V and the current that
is sourced from the OVP pin is mirrored to the Line_OVP comparator and the QR detection circuit. The
Line_OVP comparator initiates a shutdown-retry sequence if OVP sources any more than 450
A.
Load-over voltage protection occurs when the OVP pin voltage is positive. When the bias winding is positive,
during demagnetization or portions of the resonant ring, the OVP pin voltage is positive. If the OVP voltage is
greater than 3.75 V, the device initiates a shutdown. Retry occurs after a UVLO
OFF
/UVLO
ON
cycle.
Protection is provided to guard against operation during unfavorable bias conditions. Undervoltage lockout
(UVLO) always monitors VDD to prevent operation below the UVLO threshold.
19
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TYPICAL CHARACTERISTICS
-50
0
100
150
117
122
127
132
50
137
142
T
J
- Temperature -
C
f
S
- Switching Frequency - kHz
-50
0
100
150
21
23
25
27
50
29
31
T
J
- Temperature -
C
V
D
D
- Clamp V
oltage - V
-50
0
100
150
0.70
0.75
0.80
0.85
50
0.90
0.95
T
J
- Temperature -
C
PL Threshold, QR Mode, Peak CS V
oltage - V
-50
0
100
150
-512
-492
-472
-432
50
-412
-372
-452
-392
T
J
- Temperature -
C
I
O
V
P
- Over V
oltage Protection Threshold -
A
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
PL THRESHOLD
SWITCHING FREQUENCY
vs
vs
TEMPERATURE
TEMPERATURE
Figure 10.
Figure 11.
PL THRESHOLD
OVER VOLTAGE PROTECTION THRESHOLD
vs
vs
TEMPERATURE
TEMPERATURE
Figure 12.
Figure 13.
20
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PRACTICAL DESIGN NOTES
Non-Ideal Current Sense Value
R
PL1
+
R
PL
R
CS
R
DCS
(2)
R
PL2
+
R
PL1
R
CS
R
DCS
*
1
(3)
R
CS
R PL1
R
PL2
From power
MOSFET
To CS
R
DCS
R PL
From power
MOSFET
To CS
(a)
(b)
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
Resistors R
CS
, R
PL
, R
OVP1
and R
OVP2
must be programmed as a set due to functional interactions in the
converter. Often, the ideal value for R
CS
is not available because the selection range of current sense resistors
is too coarse to meet the required power limit tolerances. This issue can be solved by using the next larger
available value of R
CS
and use a resistive divider with a Thevenin resistance that is equal to the ideal R
PL
value
in order to attenuate the CS signal to its ideal value, as shown in
Figure 14
. The equations for modifying the
circuit are:
R
DCS
= ideal, but non-standard, value of current sense resistor.
R
PL
= previously calculated value of the power limit resistor.
R
CS
= available, standard value current sense resistor.
The board should be laid out to include R
PL2
in order to fascillitate final optimization of the design based upon
readily available components.
Figure 14. Modifications to Fit a Standard Current Sense Resistor Value
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Snubber Damping
PRIMARY
SECONDARY
+
-
+
-
+
-
PRIMARY
SECONDARY
+
-
+
-
+
-
(a)
(c)
0V
0V
(b)
0V
0V
(d)
V
D
V
D
V
D
V
D
V
G
V
G
V
G
V
G
L
M
L
M
L
LEAK
L
LEAK
V
BULK
V
BULK
C
BULK
C
BULK
V
IN
V
IN
V
R
V
R
V
SNUB
V
SNUB
C
SNUB
C
SNUB
R
SNUB2
R
SNUB1
R
SNUB1
C
D
C
D
R
CS
R
CS
M
1
M
1
D
S
D
S
Reduced L
LEAK
C
D
Resonance
L
LEAK
C
D
Resonance
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
PRACTICAL DESIGN NOTES (continued)
Resonance between the leakage inductance and the MOSFET drain capacitance can cause false load-OVP
faults, in spite of the typical 2-
s delay in load-OVP detection. The bias winding is sensitive to the overshoot and
ringing because it is well coupled to the primary winding. A technique to eliminate the problem is to use an R
2
CD
snubber instead of an RCD snubber, shown in
Figure 15
. A damping resistor added to the RCD snubber
reduces ringing between the drain capacitor and the inductance when the snubber diode commutates OFF.
Figure 15. (a) RCD Snubber, (b) RCD Snubber Waveform, (c) R
2
CD Snubber, (d) R
2
CD Snubber Waveform
22
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Pick
D
V
SNUB
V
R
+
between 0.5 and 1
(4)
C
SNUB
+
I
cs(peak)
2
L
LEAK
V
R
) D
V
SNUB
2
*
V
R
2
(5)
R
SNUB1
+
1
2
)
V
R
D
V
SNUB
1
C
SNUB
1
f
S(max)
*
L
LEAK
I
CS(peak)
D
V
SNUB
(6)
P R
SNUB1
+
V
R
R
SNUB1
)
1
2
I
CS(peak)
2
L
LEAK
f
S(max)
(7)
R
SNUB2
+
D
V
SNUB
I
CS(peak)
(8)
P R
SNUB
+
I
CS(peak)
2
R
SNUB2
1
3
L
LEAK
f
S(max)
V
R
)
D
V
SNUB
2
(9)
Q
+
2V
R
D
V
SNUB
)
1
(10)
REFERENCES
RELATED PRODUCTS
UCC28600
SLUS646B NOVEMBER 2005 REVISED MAY 2006
PRACTICAL DESIGN NOTES (continued)
Begin the design of the R
2
CD using the same procedure as designing an RCD snubber. Then, add the damping
resistor, R
SNUB2
. The procedure is as follows:
Select a capacitor for
V
SNUB
:
Pick R
SNUB
to discharge C
SNUB
:
Pick R
SNUB2
to dampen the L
LEAK
-C
SNUB
resonance with a Q that is between 1.7 and 2.2:
For the original selection of
V
SNUB
,
1. Power Supply Seminar SEM-1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate
Drive Circuits, by Laszlo Balogh, Texas Instruments Literature Number SLUP133
2. Datasheet, UCC3581 Micro Power PWM Controller, Texas Instruments Literature Number SLUS295
3. Datasheet, UCC28051 Transition Mode PFC Controller, Texas Instruments Literature Number SLUS515
4. UCC28600 Design Calculator, A QR Flyback Designer.xls, spreadsheet for Microsoft Excel 2003, Texas
Instruments Literature Number SLVC104
UCC28051 Transition Mode PFC Controller (SLUS515)
UCC3581 Micro Power PWM Controller (SLUS295)
23
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