UCC2585
UCC3585
SLUS304E JULY 1999 REVISED NOVEMBER 2001
LOW VOLTAGE SYNCHRONOUS
BUCK CONTROLLER
1
www.ti.com
FEATURES
D
VOUT Resistor Programmable Down to 0.9 V
D
3.3-V or 5.0-V Input Supply
D
1% DC Accuracy
D
High Efficiency Synchronous Switching
D
Drives P-Channel (High Side) and N-Channel
(Low Side) MOSFETs
D
Lossless Programmable Current Limit
D
Logic Compatible Shutdown
APPLICATIONS
D
Local Microprocessor Core Voltage Power
Supplies for Desktop and Notebook
Computers
D
DSP Core or I/O Powering
D
High-Speed GTL Bus Regulation
DESCRIPTION
The UCC3585 synchronous buck controller
provides flexible high efficiency power conversion
for output voltages as low as 0.9 V with ensured
1% dc accuracy. With an input voltage range of
3.0 V to 5.5 V, it is the ideal choice for 3.3 V only,
5.0 V only, or other low voltage systems. The fixed
frequency oscillator is capable of providing
practical PWM operation to 500 kHz.
The UCC3585 drives a complementary pair of
power MOSFET transistors. A P-channel on the
high side, and an N-channel on the low side step
down the input voltage at up to 90% efficiency.
A programmable two-level current limiting
function is provided by sensing the voltage drop
across the high side P-channel MOSFET. This
circuit can be configured to provide pulse-
by-pulse limiting, timed shutdown after seven
consecutive faults, or latch-off after fault detec-
tion, allowing maximum application flexibility. The
current limit threshold can be programmed over a
wide range with a single resistor.
12
14
6
11
8
PDRV
CLSET
ISENSE
13
5
9
NDRV
PWRGND
N/C
N/C
1
4
10
2
15
VIN
VFB
ENB
COMP
SD
16
7
3
SS
GND
CT
ISET
UCC3585
+
+
+
ENABLE
VIN
RTN
RTN
UDG01127
VOUT
VIN = 3.3 V
VOUT = 1.8 V
IOUT = 3 A (max)
R6
2 k
R5
2 k
R4
14 k
R3 100 k
C5 0.1
F
C4 0.47
F
R2 10 k
C1
150
F
R1
10 k
C7
0.47
F
C8
150
F
C9
10
F
C2 5600 pF
C3 47 pF
L1
3.7
H
C6 470 pF
Q1
SI4562DY
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2001, Texas Instruments Incorporated
UCC2585
UCC3585
SLUS304E JULY 1999 REVISED NOVEMBER 2001
2
www.ti.com
description (continued)
The UCC3585 also includes undervoltage lockout, a logic controlled enable, and softstart functions. The
UCC3585 is offered in the 16-pin surface mount and through-hole packages.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Analog pins
Minimum and maximum forced voltage (reference to GND)
0.3 V to 6.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
Digital pins
Minimum and maximum forced voltage (reference to GND)
0.3 V to 6.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
Power driver output pins
Maximum forced current
1.0 A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating junction temperature, T
J
55
C to 125
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
}
Unless otherwise noted, voltages are reference to ground and currents are positive into, negative out of, the specified terminals. Pulsed is defined
as a less than 10% duty cycle with a maximum duration of 500 ns.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ENB
COMP
SS
VFB
GND
N/C
ISET
CLSET
CT
VIN
NDRV
PWRGND
PDRV
ISENSE
SD
N/C
N, D and M PACKAGES
(TOP VIEW)
AVAILABLE OPTIONS
T
PACKAGED DEVICES
TA
DIL (N)
SOIC (D)
QSOP (M)
40
C to 85
C
UCC2585N
UCC2585D
UCC2585M
0
C to 85
C
UCC3585N
UCC3585D
UCC3585M
The M and D packages are available taped and reeled. Add an R suffix to the device
type (e.g., UCC3585DR).
DISSIPATION RATING TABLE
PACKAGE
TA
25
C
POWER RATING
DERATING FACTOR
ABOVE TA = 25
C
TA = 70
C
POWER RATING
TA = 85
C
POWER RATING
N
1.1 W
11 mW/
C
610 mW
440 mW
D
830 mW
8.3 mW/
C
450 mW
330 mW
M
580 mW
5.8 mW/
C
320 mW
230 mW
UCC2585
UCC3585
SLUS304E JULY 1999 REVISED NOVEMBER 2001
3
www.ti.com
electrical characteristics, these specifications hold for T
A
= 0 C to 85 C for the UCC3585 and
T
A
= 40 C to 85 C for the UCC2585, T
A
= T
J,
VIN = 3.3 V, ENB, ISENSE = VIN, VFB = 0.9 V,
COMP = 1.5 V, C
T
= 330 pF, R
ISET
= 100 k
, R
CLSET
= 10 k
(unless otherwise noted)
input supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Supply current total (active)
2.3
3.5
mA
Supply current shutdown
ENB = 0 V
10
25
A
VIN turnon threshold (UVLO)
1.60
1.95
2.20
V
VIN turnon hysteresis
50
110
200
mV
voltage amplifier
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VIN = 3.0 V to 3.6 V,
TA = 25
C,
See Note 1
0.891
0.9
0.909
V
Input voltage (internal reference)
VIN = 3.0 V to 3.6 V,
TA = 0
C to 85
C,
See Note 1
0.889
0.9
0.911
V
In ut voltage (internal reference)
VIN = 3.0 V to 3.6 V,
TA = 40
C to 85
C,
See Note 1
0.886
0.9
0.914
V
Open loop gain
COMP = 0.5 V to 2.5 V
60
80
dB
Output voltage high
ICOMP = 50
A
2.80
2.95
V
Output voltage low
ICOMP = 50
A
0.10
0.25
V
Output source current
200
300
A
Output sink current
2.0
3.0
mA
NOTE: 1. Measured on COMP with the error amplifier in a unity gain (voltage follower) configuration.
oscillator/PWM
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Initial accuracy
VIN = 3.3 V
345
420
475
kHz
Initial accuracy
VIN = 5.0 V
345
425
485
kHz
CT ramp peak to valley
1.9
2.1
2.3
V
CT ramp peak
2.5
2.7
V
CT ramp valley voltage
0.3
0.4
V
PWM maximum duty cycle
COMP = 2.8 V,
Measured on PDRV
100
%
PWM delay to outputs
COMP = 2.5 V
75
110
ns
Enable high threshold
Measured on ENB,
See Note 3
2.8
V
Enable low threshold
Measured on ENB
0.5
V
Softstart charge current
SS = 0 V,
TA = 0
C to 85
C
10
13.5
16
A
Softstart charge current
SS = 0 V,
TA = 40
C to 85
C
10
13.5
19
A
NOTE: 3. Enable high threshold = (VIN 0.5).
UCC2585
UCC3585
SLUS304E JULY 1999 REVISED NOVEMBER 2001
4
www.ti.com
electrical characteristics, these specifications hold for T
A
= 0 C to 85 C for the UCC3585 and
T
A
= 40 C to 85 C for the UCC2585, T
A
= T
J,
VIN = 3.3 V, ENB, ISENSE = VIN, VFB = 0.9 V,
COMP = 1.5 V, C
T
= 330 pF, R
ISET
= 100 k
, R
CLSET
= 10 k
(unless otherwise noted)
current limit
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Comparator offset voltage
25
0
25
mV
CLSET c rrent
VIN = 3.3 V
10
11.5
14
A
CLSET current
VIN = 5 V
11
12.5
15
A
SD sink current
SD = 2 V
9
11
13
A
SD source current
SD = 2 V
0.8
1.1
mA
Restart threshold
Measured on SD
0.40
0.55
0.70
V
output driver
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Pullup resistance (PDRV)
50 mA (source),
TA = 0
C to 85
C
4.5
6
9
Pullup resistance (PDRV)
50 mA (source),
TA = 40
C to 85
C
3.5
6
9
P lldo n resistance (PDRV)
50 mA (sink),
TA = 0
C to 85
C
6
9
16
Pulldown resistance (PDRV)
50 mA (sink),
TA = 40
C to 85
C
5
9
16
Pullup resistance (NDRV)
50 mA (source),
TA = 0
C to 85
C
4.5
6
9
Pullup resistance (NDRV)
50 mA (source),
TA = 40
C to 85
C
3.5
6
9
P lldo n resistance (NDRV)
100 mA (sink),
TA = 0
C to 85
C
2
3
4.5
Pulldown resistance (NDRV)
50 mA (sink),
TA = 40
C to 85
C
1.8
3
4.5
Deadtime delay (PDRV high to NDRV high)
See Note 2
150
200
225
ns
Deadtime delay (NDRV low to PDRV low)
See Note 2
70
110
150
ns
NOTE: 1. Measured on COMP with the error amplifier in a unity gain (voltage follower) configuration.
NOTE: 2. 50% point of PDRV rise to NDRV rise and 50% point of NDRV fall to PDRV fall.
NOTE: 3. Enable high threshold = (VIN 0.5).
pin descriptions
CLSET: CLSET is used to program the pulse-by-pulse and overcurrent shutdown levels for the UCC3585. A
resistor connected between CLSET and VIN sets the over-current threshold. The over-current threshold follows
the following relationship:
l
CL
+
1.25
R
ISET
R
CLSET
R
DS on
COMP: Output of the voltage error amplifier. Loop compensation components are connected between COMP
and VFB.
CT: A high quality ceramic capacitor connected between this pin and ground sets the PWM oscillator frequency
by the following relationship:
f
+
1
7000
C
T
The oscillator is capable of reliable operation up to 500 kHz.
UCC2585
UCC3585
SLUS304E JULY 1999 REVISED NOVEMBER 2001
5
www.ti.com
pin descriptions (continued)
ENB: A logical 1 (V
IN
0.5 V) on this input will activate the output drivers. A logical zero (0.5 V) will prevent
switching of the output drivers. Do not allow ENB to remain between these levels steady state.
GND: Reference level for the IC. All voltages and currents are with respect to GND.
ISENSE: ISENSE monitors the voltage dropped across the high side P-channel MOSFET switch while it is
conducting. This information is used to detect overcurrent conditions by the current limit circuitry.
ISET: A resistor is connected between ISET and ground to program a precision bias for many of the UCC3585
circuit blocks. This resistor should be 100 k
with a maximum tolerance of 5%. 1.25 V is provided to ISET via
a buffered version of the internal bandgap voltage reference. The resulting current, 1.25 V / R
ISET
, is mirrored
directly over to CLSET to program the overcurrent threshold.
NDRV: High current driver output for the low side N-channel MOSFET switch.
PDRV: High current driver output for the high side P-channel MOSFET switch.
PWRGND: High current return path for the MOSFET drivers. PWRGND and GND should be terminated
together as close as possible to the device package .
SD: This pin can configure current limit to operate in any one of three different ways.
1.
A forced voltage of less than 250 mV on SD inhibits the shutdown function causing pulse by pulse limiting.
2.
A capacitor from SD to GND provides a controller-converter shutdown timeout after seven consecutive
overcurrent signals are received by the current limit circuitry. An internal 11-
A (typ) current source
discharges the SD capacitor to the 0.55-V (typ) restart threshold. The shutdown time is given by:
t
SHUT
+
C
SD
V
IN
*
0.55 V
11
m
A
where C
SD
is the value of the capacitor from SD to GND, and VIN is the chip supply voltage (on pin 15).
At this point, a softstart cycle is initiated, and a 1-mA current source (typ) quickly recharges SD to VIN.
During softstart, pulse-by-pulse current limiting is enabled, and the 7-cycle counter is disabled until
softstart is complete (i.e. charged to approximately VIN volts).
3.
A forced voltage of greater than 1 V on SD will cause the UCC3585 to latch off after seven overcurrent
signals are received. After the controller is latched off, SD must drop below 250 mV to restart the
controller.
SS: A low leakage capacitor connected between SS and GND will provide a softstart function for the converter.
The voltage on this capacitor slowly charges on start-up via an internal 13.5
A (typ.) current source. The output
of the voltage error amplifier (COMP) tracks this voltage, thereby limiting the controller duty ratio.
VFB: Inverting input to the voltage type error amplifier. The common mode input range for VFB extends from
GND to 1.5 V.
VIN: Supply voltage for the UCC3585. Bypass with a 0.1-
F ceramic capacitor (minimum) to supply the peak
gate drive currents required to change and discharge the power MOSFET gates. See application information
for details.
UCC2585
UCC3585
SLUS304E JULY 1999 REVISED NOVEMBER 2001
6
www.ti.com
block diagram
UDG00070
11
16
10
CURENT
LIMIT ADJ
8
CLSET
SD
ISENSE
DISABLE DRIVERS
CURRENT
LIMIT
PRECISION
BIAS SET
7
12 PDRV
ANTI
SHOOT THRU
14 NDRV
DRIVER
15
ISET
VIN
1
ENB
VIN
1.25 V
REF
UVLO
2 V
2
COMP
4
VFB
0.9 V
3
SS
VIN
9
NC
OSCILLATOR
PWM
PRECISION
BIAS
OVER CURRENT COUNTER
SHUTDOWN TIMER
CT
13 PWRGND
SOFTSTART COMPLETE
5
GND
UVLO
ENABLE
L = NO SHUTDOWN
H = LATCHED SHUTDOWN
CAP = TIMED SHUTDOWN
R
Q
Q
S
PWM
LATCH
D
CLK
UVLO
DRIVER
6
NC
ILIM
ILIM
13.5
A
11
A
0.8 V
APPLICATION INFORMATION
ISET pin operation
The ISET pin develops a precision current reference for many of the UCC3585's internal circuit blocks. A
resistor, R
ISET
, connected from the ISET pin to ground sets the precision current value. The internal current
reference is set by buffering the 1.25-V internal reference to the ISET pin, which results in a current of
1.25 V/R
ISET
. The UCC3585 is designed for R
ISET
= 100 k
with a maximum tolerance of 5%. Using a different
resistor value results in changed parametric performance and possibly unpredictable operation.
oscillator
The oscillator frequency is programmed by a timing capacitor connected from CT to ground. The maximum
recommended frequency is 500 kHz. The timing capacitor is charged and discharged by current sources
derived from the ISET pin. The voltage waveform on CT is a sawtooth ramp with approximately 95% of the period
spent charging the timing capacitor. Ceramic capacitors should be used, and the capacitance tolerance adds
to the accuracy of the oscillator frequency. For applications that operate over a wide temperature range or where
the highest accuracy is required, temperature stable ceramic capacitors such as NPO or COG dielectric should
be used for the CT capacitor. The aproximate operating frequency is determined by:
f
+
1
7000
C
T
UCC2585
UCC3585
SLUS304E JULY 1999 REVISED NOVEMBER 2001
7
www.ti.com
APPLICATION INFORMATION
soft-start
The SS pin provides a way to prevent overshoot of the output voltage by slowly increasing the duty cycle of the
PDRV output. A capacitor on SS to ground provides a controlled start-up of the supply. During start-up the
COMP pin is directly clamped to the SS pin. The SS pin has an internal current source of 13.5
A (typical) which
charges the SS capacitor. Figure 1 shows the waveforms during softstart. The SS pin charges the external
capacitor to VIN volts after start-up is complete.
SS
COMP
VOUT
0.4 V
VIN
ENB or VIN
switching
disabled until
SS reaches
0.4 V
switching
starts, V OUT
charging up
VOUT in
regulation, SS
continues to
charge to VIN
VOUT in
regulation, SS
charged to VIN
t SS
V = 0.4 V + D x 2.1
t
Figure 1. Waveforms During Softstart
The softstart time is approximately:
t
SS
+
C
SS
0.4
)
V
OUT
V
IN
2.1
13.5
m
A
current limit operation
The UCC3585 has a user configurable current limit for output overload protection. To reduce external
component count and minimize losses, the P-channel MOSFET's R
DS(on)
is used as a current sense element.
The ISENSE pin is connected to the P-channel MOSFET drain, which is internally connected to the negative
input to the current-sense comparator. The positive comparator input is connected to the CLSET pin, which has
an internal current sink of 11.5
A (typical). For highest accuracy, this current sink is derived from the ISET
circuitry. A resistor from VIN to CLSET sets the current limit threshold. To eliminate errors due to PCB trace
impedances, the CLSET resistor should be connected directly to the P-channel MOSFET source, and the
ISENSE pin should be directly connected to the P-channel MOSFET drain. Figure 2 shows a simplified diagram
of the current limit circuitry.
UCC2585
UCC3585
SLUS304E JULY 1999 REVISED NOVEMBER 2001
8
www.ti.com
APPLICATION INFORMATION
11.5
A
RCLSET
12
8
11
14
G
15
VOUT
PChannel
MOSFET
Package
VIN
To
PWM
Logic
ISENSE
ENABLE
D
S
Figure 2. Current Limit Circuitry
The peak current limit is calculated using the following equation:
l
CL
+
1.25
R
ISET
R
CLSET
R
DS on
When the R
DS(on)
of the P-channel MOSFET is used as the sense element, several issues arise. Before the
current limit comparator is enabled, the P-channel MOSFET must be fully enhanced, and the drain to source
voltage must be allowed to settle. The UCC3585 has an internal circuit that disables the current limit comparator,
t
ISENSE,
for a fixed time, starting at the PDRV output falling edge. It is important that no external gate resistor
is used between the PDRV output and the P-channel gate. If a resistor is used, the PDRV output falls quickly,
and the turnon of the P-channel MOSFET is delayed, possibly causing a false overcurrent event to be detected.
Figure 3 shows the waveforms at the P-channel turnon instance and the t
ISENSE
time interval.
UCC2585
UCC3585
SLUS304E JULY 1999 REVISED NOVEMBER 2001
9
www.ti.com
APPLICATION INFORMATION
PDRV
ISENSE
0 V
VIN
tISENSE
0.7 V
VIN/2
Comparator
Enabled
time
ISENSE
Figure 3. t
ISENSE
Time Interval
The t
ISENSE
time interval follows the approximate relationship:
t
ISENSE
+
V
BE
)
12.5
m
A
R
CLSET
3.2 pF
12.5
m
A
As can be seen from the above equation, t
ISENSE
is dependent upon two variables. First, t
ISENSE
is longer for
higher values of R
CLSET
. This allows more time for ISENSE to settle, which is beneficial for supplies with a higher
current limit threshold. Second, t
ISENSE
varies with the inherent temperature dependence of the V
BE
in the
above equation. V
BE
can be assumed to be 0.65 V at 25
C with a temperature coefficient of 2 mV/
C. Since
the t
ISENSE
time interval decreases at high temperature, operation of the supply must be verified at the maximum
ambient temperature at full output load.
Another issue with using the MOSFET R
DS(on)
for the sense element is the minimum on time for the P-channel
MOSFET. Since there is a blanking interval, t
ISENSE
, there is a minimum time that the P-channel MOSFET stays
on during any PWM period. The minimum on time occurs even with the power supply output shorted,
experimentally the minimum on time is approximately 400 ns. When a converter is operated continuously into
a shorted or overloaded output, this minimum on time results in a significant power dissipation and stress on
both MOSFETs.
UCC2585
UCC3585
SLUS304E JULY 1999 REVISED NOVEMBER 2001
10
www.ti.com
APPLICATION INFORMATION
A solution to this minimum on-time is a counter and time-out circuit. As described in the SD pin description, a
capacitor on SD enables the time-out circuit. An internal digital counter is used to count the overcurrent events
at the current-sense comparator output. When seven overcurrent conditions are reached, both MOSFET
switches are turned off, the SS capacitor is discharged, and an 11
A (typical) internal current sink discharges
the SD capacitor. During this discharge time, both MOSFETs are held off, and the inductor current decays to
zero. When the SD capacitor voltage reaches 0.55 V (typical), a softstart cycle restarts the converter. During
softstart, the 7-cycle counter is disabled. However, the peak current limit comparator is enabled. When the SS
voltage reaches the threshold equal to (V
IN
0.5 V), the 7-cycle counter is enabled. By sizing the SS capacitor
relative to the SD capacitor, the amount of time spent switching the MOSFETs can be reduced when the output
is overloaded. If the timeout mode is used, the relative capacitance values for C
SS
and C
SD
must fall into the
following relationship:
C
SD
v
20
C
SS
This equation also states that, if the time-out mode is used, a softstart capacitor must be used. Figure 4 shows
the waveforms when the converter is operated into a short circuit.
V(PDRV)
V(SD)
0.55 V
VIN0.5 V
VIN
V(SS)
time
0 V
VIN
t
SHUT
Figure 4. Converter Operated Into Short Circuit
UCC2585
UCC3585
SLUS304E JULY 1999 REVISED NOVEMBER 2001
11
www.ti.com
APPLICATION INFORMATION
VIN bypass capacitor selection
A ceramic capacitor must be used across VIN to GND on the UCC3585. This capacitor supplies the transient
currents required to turn on and off both power MOSFETs. It is important to select a high enough capacitance
value to keep the peak-to-peak ripple voltage at VIN below 100 mV. The maximum peak-to-peak ripple on VIN
is somewhat arbitrary, and 100 mV is used as an estimate. Knowing the P-channel total gate charge, Q
P
and
the total gate charge for the N-channel MOSFET, Q
N
, the minimum capacitance can be found:
C
VIN(min)
+
Q
P
)
Q
N
100 mV
An estimate of Q
P
can be found from the manufacturer's data sheet curve for gate charge vs gate to source
voltage. Since the N-channel MOSFET is switched with essentially zero volts across it, a better estimation of
Q
N
is found by multiplying the input capacitance, C
ISS
and the V
IN
voltage. Because C
ISS
is voltage dependent,
it is important to use the C
ISS
value for approximately zero volts drain to source. This gives a more accurate
estimation of the N-channel gate charge.
power MOSFET drivers
The UCC3585 contains two high current power MOSFET drivers. The source and sink current capability of
these drivers has been sized to allow operation without external gate resistors. The P-channel driver has
approximately three times stronger source current than sink current. This intentionally slows down the turnon
of the P-channel MOSFET, which reduces the reverse recovery snap of the N-channel MOSFET body diode.
The N-channel driver has a stronger sink current than source current which aids in keeping the N-channel
MOSFET off when the P-channel MOSFET is turned on. Adding a gate resistor from NDRV to the N-channel
MOSFET gate makes the N-channel more sensitive to dV/dt induced turnon and should be avoided. The
MOSFET drivers have lower resistance at VIN = 5 V as compared to VIN = 3.3 V. At VIN = 5 V, the drivers have
approximately 60% of the resistance specified at VIN = 3.3 V.
operation over wide VIN ranges
It is possible to design UCC3585 based supplies to operate over both the 3.3-V and 5-V input ranges. The
resulting V
IN
range can be as wide at 3.0 V to 5.5 V. For a successful design, several design steps must be taken.
First, both MOSFETs should have R
DS(on)
rated at 2.7 V or 2.5 V. This assures reasonable efficiency at the
lowest input voltage. Second, the current limit threshold should be set at the minimum input voltage. At the
minimum input voltage, the P-channel MOSFET has maximum R
DS(on)
. As VIN is increased to 5.5 V, the R
DS(on)
decreases considerably. The effect of this reduction in R
DS(on)
is a higher current limit. Also, note that critical
parameters, such as CLSET current and oscillator frequency are specified at both 3.3 V and 5.0 V.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding thirdparty products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright
2001, Texas Instruments Incorporated
PDF 
ZIP