UCC28083, UCC28084, UCC28085, UCC28086

UCC38083, UCC38084, UCC38085, UCC38086

SLUS488B - SEPTEMBER 2002 - REVISED MAY 2003

8 PIN CURRENT MODE PUSH PULL PWM CONTROLLERS

WITH PROGRAMMABLE SLOPE COMPENSATION

www.ti.com

FEATURES

Programmable Slope Compensation

Internal Soft-Start on the UCC38083/4

Cycle-by-Cycle Current Limiting

Low Start-Up Current of 120

A and 1.5 mA

Typical Run Current

Single External Component Oscillator
Programmable from 50 kHz to 1 MHz

High-Current Totem-Pole Dual Output Stage
Drives Push-Pull Configuration with 1-A Sink
and 0.5-A Source Capability

Current Sense Discharge Transistor to
Improve Dynamic Response

Internally Trimmed Bandgap Reference

Undervoltage Lockout with Hysteresis

APPLICATIONS

High-Efficiency Switch-Mode Power Supplies

Telecom dc-to-dc Converters

Point-of-Load or Point-of-Use Power Modules

Low-Cost Push-Pull and Half-Bridge
Applications

DESCRIPTION

The UCC38083/4/5/6 is a family of BiCMOS pulse width
modulation (PWM) controllers for dc-to-dc or off-line
fixed-frequency current-mode switching power
supplies. The dual output stages are configured for the
push-pull topology. Both outputs switch at half the
oscillator frequency using a toggle flip-flop. The dead
time between the two outputs is typically 110 ns, limiting
each output's duty cycle to less than 50%.

The new UCC3808x family is based on the UCC3808A
architecture. The major differences include the addition
of a programmable slope compensation ramp to the CS
signal and the removal of the error amplifier. The current
flowing out of the ISET pin through an external resistor
is monitored internally to set the magnitude of the slope
compensation function. This device also includes an
internal discharge transistor from the CS pin to ground,
which is activated at each clock cycle after the pulse is
terminated. This discharges any filter capacitance on
the CS pin during each cycle and helps minimize filter
capacitor values and current sense delay.

The UCC38083 and the UCC38084 devices have a
typical soft-start interval time of 3.5 ms while the
UCC38085 and the UCC38086 has less than 100

s for

applications where internal soft-start is not desired.

The UCC38083 and the UCC38085 devices have the
turn-on/off thresholds of 12.5 V / 8.3 V, while the
UCC38084 and the UCC38086 has the turn-on/off
thresholds of 4.3 V / 4.1 V. Each device is offered in 8-pin
TSSOP (PW), 8-pin SOIC (D) and 8-pin PDIP (P)
packages.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

2002-2003, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.

UDG-01080

BASIC APPLICATION

OUTA

OUTB

CTRL

ISET

GND

VDD

RSET

POWER

TRANSFORMER

VIN

UCC3808x

FEEDBACK

VOUT

UCC28083, UCC28084, UCC28085, UCC28086

UCC38083, UCC38084, UCC38085, UCC38086

SLUS488B - SEPTEMBER 2002 - REVISED MAY 2003

www.ti.com

ORDERING INFORMATION

THERMAL RESISTANCE TABLE

PACKAGE

jc(

C/W)

ja(

C/W)

SOIC-8 (D)

84 to 160(1)

PDIP-8 (P)

110(1)

TSSOP-8 (PW)

32(2)

232 to 257(2)

NOTES: (1) Specified

ja (junction to ambient) is for devices mounted to 5-inch2 FR4 PC board

with one ounce copper where noted. When resistance range is given, lower values
are for 5 inch2 aluminum PC board. Test PWB was 0.062 inch thick and typically
used 0.635-mm trace widths for power packages and 1.3-mm trace widths for
non-power packages with a 100-mil x 100-mil probe land area at the end of each
trace.

(2). Modeled data. If value range given for

ja, lower value is for 3x3 inch. 1 oz internal

copper ground plane, higher value is for 1x1-inch. ground plane. All model data
assumes only one trace for each non-fused lead.

AVAILABLE OPTIONS

INTERNAL

SOFT START

UVLO

PACKAGES

INTERNAL

SOFT START

OFF

SOIC-8 (D)

PDIP-8 (P)

TSSOP-8 (PW)

3.5 ms

12.5 V

8.3 V

UCC28083D

UCC28083P

UCC28083PW

-40

C to 85

3.5 ms

4.3 V

4.1 V

UCC28084D

UCC28084P

UCC28084PW

-40

C to 85

12.5 V

8.3 V

UCC28085D

UCC28085P

UCC28085PW

4.3 V

4.1 V

UCC28086D

UCC28086P

UCC28086PW

3.5 ms

12.5 V

8.3 V

UCC38083D

UCC38083P

UCC38083PW

C to 70

3.5 ms

4.3 V

4.1 V

UCC38084D

UCC38084P

UCC38084PW

C to 70

12.5 V

8.3 V

UCC38085D

UCC38085P

UCC38085PW

4.3 V

4.1 V

UCC38086D

UCC38086P

UCC38086PW

The D and PW packages are available taped and reeled. Add R suffix to device type, e.g. UCC28083DR (2500 devices

per reel) or UCC38083PWR (2000 devices per reel).

CTRL

ISET

VDD
OUTA
OUTB
GND

D OR P PACKAGE

(TOP VIEW)

PW PACKAGE

(TOP VIEW)

OUTB
GND
RT
CS

OUTA

VDD

CTRL

ISET

UCC28083, UCC28084, UCC28085, UCC28086

UCC38083, UCC38084, UCC38085, UCC38086

SLUS488B - SEPTEMBER 2002 - REVISED MAY 2003

www.ti.com

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage, V

< 10 mA)

15 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply current, I

20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Sink current (peak):

OUTA

1.0 A

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OUTB

1.0 A

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Source current (peak): OUTA

-0.5 A

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OUTB

-0.5 A

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog inputs:

CTRL

-0.3 V to V

+0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

-0.3 V to V

+0.3 V, not to exceed 6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SET

(minimum)

>5 k

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(-100

A < I

< 100

-0.3 V to 2.0 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power dissipation at T

= 25

C (P package)

1 W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power dissipation at T

= 25

C (D package)

650 mW

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power dissipation at T

= 25

C (PW package)

400 mW

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Junction operating temperature, T

-55

C to 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature, T

stg

-65

C to 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature (soldering 10 seconds)

300

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND.
Currents are positive into, and negative out of the specified terminal.

electrical characteristics over recommended operating virtual junction temperature range,
V

= 10 V (See Note 1),1-

F capacitor from VDD to GND, R

= 165 k

, R

= 1 k

, C

= 220 pF,

SET

= 50 k

, T

= -40

C to 85

C for UCC2808x, T

= 0

C to 70

C for UCC3808x, T

= T

(unless otherwise noted)

overall

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Start-up current

VDD < UVLO start threshold voltage

120

200

Supply current

CTRL = 0 V,

CS = 0 V,

See Note 1

1.5

2.5

undervoltage lockout

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Start threshold voltage

UCC38083/5

See Note 1

11.5

12.5

13.5

Start threshold voltage

UCC38084/6

4.1

4.3

4.5

Minimum operating voltage

UCC38083/5

7.6

8.3

9.0

Minimum operating voltage
after start

UCC38084/6

3.9

4.1

4.3

Hysteresis voltage

UCC38083/5

3.5

4.2

5.1

Hysteresis voltage

UCC38084/6

0.1

0.2

0.3

oscillator

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Frequency

2 x f(OUTA)

180

200

220

kHz

Voltage amplitude

See Note 2

1.4

1.5

1.6

Oscillator fall time (dead time)

110

220

RT pin voltage

1.2

1.5

1.6

UCC28083, UCC28084, UCC28085, UCC28086

UCC38083, UCC38084, UCC38085, UCC38086

SLUS488B - SEPTEMBER 2002 - REVISED MAY 2003

www.ti.com

electrical characteristics over recommended operating virtual junction temperature range,
V

= 10 V (See Note 1),1-

F capacitor from VDD to GND, R

= 165 k

, R

= 1 k

, C

= 220 pF,

SET

= 50 k

, T

= -40

C to 85

C for UCC2808x, T

= 0

C to 70

C for UCC3808x, T

= T

(unless otherwise noted)

current sense

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Gain

See Note 3

1.9

2.2

2.5

V/V

Maximum input signal voltage

CTRL = 5 V,

See Note 4

0.47

0.52

0.57

CS to output delay time

CTRL = 3.5 V,

0 mV

600 mV

100

200

Source current

-200

Sink current

CS = 0.5 V,

RT = 2.0 V,

See Note 5

Overcurrent threshold voltage

0.70

0.75

0.80

CTRL to CS offset voltage

CS = 0 V, 25

0.55

0.70

0.90

CTRL to CS offset voltage

CS = 0 V

0.37

0.70

1.10

pulse width modulation

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Maximum duty cycle

Measured at OUTA or OUTB

48%

49%

50%

Minimum duty cycle

CTRL = 0 V

output

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Low-level output voltage (OUTA or OUTB)

IOUT = 100 mA

0.5

1.0

High-level output voltage (OUTA or OUTB)

IOUT = -50 mA,

(VDD - VOUT), See Note 6

0.5

1.0

Rise time

CLOAD = 1 nF

Fall time

CLOAD = 1 nF

soft-start

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

OUTA/OUTB soft-start interval time,
UCC38083/4

CTRL = 1.8 V,

CS = 0 V,

Duty cycle from 0 to full

1.3

3.5

8.5

OUTA/OUTB soft-start interval time,
UCC38085/6

CTRL = 1.8 V,

CS = 0 V,

Duty cycle from 0 to full

110

slope compensation

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

IRAMP, peak

ISET, peak = 30

A, Full duty cycle

125

150

175

NOTE 1: For UCCx8083/5, set VDD above the start threshold before setting to 10 V.
NOTE 2: Measured at ISET pin.

NOTE 3: Gain is defined by A

CTRL

, 0

VCS

0.4 V.

NOTE 4: Measured at trip point of latch with CS ramped from 0.4 V to 0.6 V.
NOTE 5: This internal current sink on the CS pin is designed to discharge and external filter capacitor. It is not intended to be a dc sink path.
NOTE 6: Not 100% production tested. Ensured by design and also by the rise time test.

UCC28083, UCC28084, UCC28085, UCC28086

UCC38083, UCC38084, UCC38085, UCC38086

SLUS488B - SEPTEMBER 2002 - REVISED MAY 2003

www.ti.com

functional block diagram

UDG-01081

CTRL

VDD

ISET

GND

OUTA

OUTB

0.75V

0.5V

1.5V

0.2V

0.5V

Vdd-1

VREF

ISLOPE

Css

Iss

Soft Start and Fault Latch

PWM Comparator/Latch

Output Driver

Oscillator

CS Circuitry

Slope Circuit

Bias/UVLO

ISLOPE =

5 x I SET

ICT

1.5V

80 k

60 k

0.3 V

Terminal Functions

TERMINAL

NAME

PACKAGE

I/O

DESCRIPTION

NAME

D OR P

I/O

DESCRIPTION

The current-sense input to the PWM comparator, the cycle-by-cycle peak current comparator, and the
overcurrent comparator. The overcurrent comparator is only intended for fault sensing. Exceeding the
overcurrent threshold causes a soft-start cycle. An internal MOSFET discharges the current-sense filter
capacitor to improve dynamic performance of the power converter.

CTRL

Error voltage input to PWM comparator.

GND

Reference ground and power ground for all functions. Due to high currents, and high-frequency operation
of the IC, a low-impedance circuit board ground plane is highly recommended.

ISET

Current selection for slope compensation.

OUTA

Alternating high-current output stages.

OUTB

Alternating high-current output stages.

Programs the oscillator.

VDD

Power input connection.

UCC28083, UCC28084, UCC28085, UCC28086

UCC38083, UCC38084, UCC38085, UCC38086

SLUS488B - SEPTEMBER 2002 - REVISED MAY 2003

www.ti.com

detailed pin descriptions

CTRL: The error voltage is typically generated by a secondary-side error amplifier and transmitted to the
primary-side referenced UCC3808x by means of an opto-coupler. CTRL has an internal divider ratio of 0.45 to
maintain a usable range with the minimum V

of 4.1 V. The UCC38083/UCC38084 family features a built-in

full-cycle soft start while the UCC38085/6 does not.

For the UCC38083/4, soft-start is implemented as a clamp at the input to the PWM comparator. This causes
the output pulses to start near 0% duty cycle and increase until the clamp exceeds the CTRL voltage.

ISET: Program the slope compensation current ramp by connecting a resistor, RSET, from ISET to ground. The
voltage of the ISET pin tracks the 1.5-V internal oscillator ramp, as shown in Figure 1.

UCC38083

CTRL

VDD

ISET

OUTA

OUTB

GND

1uF

10k

165k

220pF

RSET

V(CS)

VDD

I SET

I RAMP

ISET

IRAMP

OUTA

OUTB

I RAMP, peak = 5 x ISET, peak

Figure 1. Full Duty Cycle Output

The compensating current source, I

SLOPE

, at the CS pin is proportional to the ISET current, according to the

relation:

SLOPE

SET

The ramping current due to I

SLOPE

develops a voltage across the effective filter impedance that is normally

connected from the current sense resistor to the CS input. In order to program a desired compensating slope
with a specific peak compensating ramp voltage at the CS pin, use the RSET value in the following equation:

RSET

OSC(peak)

RAMP VOLTAGE HEIGHT

Where V

OSC(peak)

1.5 V

Notice that the PWM Latch drives an internal MOSFET that will discharge an external filtering capacitor on the
CS pin. Thus, I

SLOPE

will appear to terminate when the PWM comparator or the cycle-by-cycle current limit

comparator sets the PWM latch. The actual compensating slope is not affected by premature termination of the
switching cycle.

(1)

(2)

UCC28083, UCC28084, UCC28085, UCC28086

UCC38083, UCC38084, UCC38085, UCC38086

SLUS488B - SEPTEMBER 2002 - REVISED MAY 2003

www.ti.com

detailed pin descriptions (continued)

OUTA and OUTB: Alternating high-current output stages. Both stages are capable of driving the gate of a power
MOSFET. Each stage is capable of 500-mA peak-source current, and 1-A peak-sink current.

The output stages switch at half the oscillator frequency, in a push-pull configuration. When the voltage on the
internal oscillator capacitor is rising, one of the two outputs is high, but during fall time, both outputs are off. This
dead time between the two outputs, along with a slower output rise time than fall time, ensures that the two
outputs cannot be on at the same time. This dead time is typically 110 ns.

The high-current output drivers consist of MOSFET output devices, which switch from VDD to GND. Each output
stage also provides a very low impedance to overshoot and undershoot. This means that in many cases,
external Schottky clamp diodes are not required.

RT: The oscillator programming pin. The oscillator features an internal timing capacitor. An external resistor,
R

, sets a current from the RT pin to ground. Due to variations in the internal C

, nominal V

of 1.5 V can vary

from 1.2 V to 1.6 V

Selecting RT as shown programs the oscillator frequency:

28.7

-12

OSC

2.0

-7

where f

OSC

is in Hz, resistance in

. The recommended range of timing resistors is between 25 k

and 698 k

For best performance, keep the timing resistor lead from the RT pin to GND (pin 5) as short as possible.

UDG-01083

Approximate Frequency

28.7

-12

)

2.0

-7

1.5 V

0.2 V

C T

1.5 V

OSCILLATOR

OUTPUT

Figure 2. Block Diagram for Oscillator

VDD: The power input connection for this device. Although quiescent VDD current is very low, total supply
current may be higher, depending on OUTA and OUTB current, and the programmed oscillator frequency. Total
VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating
frequency and the MOSFET gate charge (Q

), average OUT current can be calculated from:

OUT

OSC

where f is the oscillator frequency.

To prevent noise problems, bypass VDD to GND with a ceramic capacitor as close to the chip as possible along
with an electrolytic capacitor. A 1-

F decoupling capacitor is recommended.

(3)

(4)

UCC28083, UCC28084, UCC28085, UCC28086

UCC38083, UCC38084, UCC38085, UCC38086

SLUS488B - SEPTEMBER 2002 - REVISED MAY 2003

www.ti.com

APPLICATION INFORMATION

operational waveforms

Figure 3 illustrates how the voltage ramp is effectively added to the voltage across the current sense element
V

, to implement slope compensation.

UDG-01085

OUTA

OUTB

VRS

ADDED

RAMP

VOLTAGE

VCS, Pin 3

Figure 3. Typical Slope Compensation Waveforms at 80% Duty Cycle

In Figure 3, OUTA and OUTB are shown at a duty cycle of 80%, with the associated voltage VRS across the
current sense resistor of the primary push-pull power MOSFETs. The current flowing out of CS generates the
ramp voltage across the filter resistor R

that is positioned between the power current sense resistor and the

CS pin. This voltage is effectively added to VRS to provide slope compensation at VCS, pin 3. A capacitor C

is also recommended to filter the waveform at CS.

UCC28083, UCC28084, UCC28085, UCC28086

UCC38083, UCC38084, UCC38085, UCC38086

SLUS488B - SEPTEMBER 2002 - REVISED MAY 2003

www.ti.com

layout considerations

To prevent noise problems, bypass VDD to GND with a ceramic capacitor as close to the chip as possible along
with an electrolytic capacitor. A 1-

F decoupling capacitor is recommended.

Use a local ground plane near the small signal pins (CTRL, ISET, CS and RT) of the IC for shielding. Connect
the local ground plane to the GND pin with a single trace. Do not extend the local ground plane under the power
pins (VDD, OUTA, OUTB and GND). Instead, use signal return traces to the GND pin for ground returns on the
side of the integrated circuit with the power pins.

For best performance, keep the timing resistor lead from RT pin (pin 4) to GND (pin 5) as short as possible.

special layout considerations for the TSSOP package

Due to the different pinout and smaller lead pitch of the TSSOP package, special attention must be paid to
minimize noise problems. The pinout is different because the device had to be rotated 90

to fit into the smaller

TSSOP package.

For example, the two output pins are now on opposite sides of the package. The traces should not run under
the package together as they will couple switching noise into analog pins.

Another common problem is when RT and OUTB (pins 6 and 8) are routed together for some distance even
though they are not immediate side by side pins. Because of this, when OUTB rises, a voltage spike of upto
400 mV can couple into the RT. This spike causes the internal charge current into CT to be turned off
momentarily resulting in lower duty cycle. It is also important that note that the RT pin voltage cannot be
stabilized with a capacitor. The RT pin is just a dc voltage to program the internal CT. Instead, keep the OUTB
and RT runs short and far from each other and follow the printed wiring board layout suggestions above to fix
the problem.

reference design

A reference design is discussed in 50-W Push-Pull Converter Reference Design Using the UCC38083, TI
Literature Number SLUU135. This design controls a push-pull synchronous rectified topology with input range
of 18 V to 35 V (24 nominal) and 3.3-V output at 15 A. The schematic is shown in Figure 5 and the board layout
for the reference design is shown in Figure 4. Refer to the document for further details.

Figure 4. Reference Design Layout

UCC28083, UCC28084, UCC28085, UCC28086

UCC38083, UCC38084, UCC38085, UCC38086

SLUS488B - SEPTEMBER 2002 - REVISED MAY 2003

www.ti.com

TYPICAL CHARACTERISTICS

Figure 6

100

1000

1200

1000

800

600

400

200

Frequency

OSCILLATOR FREQUENCY

TIMING RESISTANCE

VDD = 15 V

VDD = 6 V

VDD = 10 V

T = 25

T = 85

T = 40

RT - Timing Resistance - k

Figure 7

-50

125

Temperature -

220

215

205

200

195

185

180

-25

100

210

190

OSCILLATOR FREQUENCY

TEMPERATURE

Frequency

RT = 165 k

RF= 1 k

CF = 220 k

RSET = 50 k

Figure 8

1000

Frequency - kHz

100

IDD

OSCILLATOR FREQUENCY, (NO LOAD)

IDD -

VDD = 14 V

VDD = 10 V

VDD = 6 V

Figure 9

1000

Frequency - kHz

100

IDD

OSCILLATOR FREQUENCY, 1 nF LOAD

IDD -

VDD = 14 V

VDD = 10 V

VDD = 6 V

UCC28083, UCC28084, UCC28085, UCC28086

UCC38083, UCC38084, UCC38085, UCC38086

SLUS488B - SEPTEMBER 2002 - REVISED MAY 2003

www.ti.com

TYPICAL CHARACTERISTICS

1000

200

160

120

100

140

180

Figure 10

DEAD TIME

TIMING RESISTANCE OVER VDD

Dead T

ime - ns

VDD = 14 V

T = -40

T = 25

VDD = 6 V*

VDD = 10 V

VDD = 6 V*

T = 85

VDD = 14 V

RT - Timing Resistance - k

* UCCx8084/6, only

Figure 11

-50

125

Temperature -

160

100

120

140

-25

100

DEAD TIME

TEMPERATURE

Dead T

ime - ns

RT = 165 k

RF= 1 k

CF = 220 k

RSET = 50 k

Figure 12

-50

125

Temperature -

2.0

1.6

1.2

0.8

0.4

0.0

0.2

0.6

1.0

1.4

1.8

-25

100

CONTROL TO CS OFFSET

TEMPERATURE

CTRL

- Control V

ltage - V

VCS = 0.40 V

VCS = 0 V

Figure 13

VDD - Volts

0.6

0.5

0.1

0.2

0.3

0.4

(OC Clamped)

RAMP HEIGHT

VDD

PK(cs)

- V

RSET = 18

TA = 25

RSET = 10

RSET = 50

RSET = 100

UCC28083, UCC28084, UCC28085, UCC28086

UCC38083, UCC38084, UCC38085, UCC38086

SLUS488B - SEPTEMBER 2002 - REVISED MAY 2003

www.ti.com

TYPICAL CHARACTERISTICS

Figure 14

1000

RT - k

0.7

0.6

0.4

0.3

0.1

100

0.2

0.5

(OC Clamped)

RAMP HEIGHT

PK(cs)

- V

RSET = 18

TA = 25

RSET = 10

RSET = 50

RSET = 100

Figure 15

-50

125

Temperature -

0.6

0.5

0.1

0.0

0.2

0.3

0.4

(OC Clamped)

-25

100

RAMP HEIGHT

TEMPERATURE

PK(cs)

- V

RSET = 18

RSET = 10

RSET = 50

RSET = 100

Figure 16

-50

125

Temperature -

-25

100

SOFT START

TEMPERATURE

Soft Start Internal - ms

UCCx8083 AND UCCx8084

Figure 17

-50

125

Temperature -

100

-25

SOFT START

TEMPERATURE

Soft Start Internal -

UCCx8085 AND UCCx8086

UCC28083, UCC28084, UCC28085, UCC28086

UCC38083, UCC38084, UCC38085, UCC38086

SLUS488B - SEPTEMBER 2002 - REVISED MAY 2003

www.ti.com

TYPICAL CHARACTERISTICS

Figure 18

-50

125

Temperature -

150

130

110

100

120

140

100

-25

CS TO OUTX DELAY TIME

TEMPERATURE

CS Prop Delay - ns

RELATED PRODUCTS

UCC3808, 8-Pin Low Power Current Mode Push-Pull PWM, (SLUS168)

UCC3808A, 8-Pin Low-Power Current-Mode Push-Pull PWM, (SLUS456)

UCC3806, Low Power, Dual Output, Current Mode PWM Controller, (SLUS272)

Table 1. 8-Pin Push-Pull PWM Controller Family Feature Comparison

Part Number

UVLO On

UVLO Off

Discharge FET

Error

Amplifier

Programmable

Slope

Compensation

Internal
Softstart

UCC38083

12.5 V

8.3 V

Yes

UCC38084

4.3 V

4.1 V

Yes

UCC38085

12.5 V

8.3 V

Yes

UCC38086

4.3 V

4.1 V

Yes

UCC3808A-1

12.5 V

8.3 V

Yes

UCC3808A-2

4.3 V

4.1 V

Yes

UCC3808-1

12.5 V

8.3 V

Yes

UCC3808-2

4.3 V

4.1 V

Yes

UCC28083, UCC28084, UCC28085, UCC28086

UCC38083, UCC38084, UCC38085, UCC38086

SLUS488B - SEPTEMBER 2002 - REVISED MAY 2003

www.ti.com

MECHANICAL DATA

D (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

8 PINS SHOWN

0.197

(5,00)

A MAX

A MIN

(4,80)

0.189

0.337

(8,55)

(8,75)

0.344

0.386

(9,80)

(10,00)

0.394

DIM

PINS **

4040047/E 09/01

0.069 (1,75) MAX

Seating Plane

0.004 (0,10)

0.010 (0,25)

0.016 (0,40)

0.044 (1,12)

0.244 (6,20)

0.228 (5,80)

0.020 (0,51)

0.014 (0,35)

0.150 (3,81)

0.157 (4,00)

0.008 (0,20) NOM

- 8

Gage Plane

0.004 (0,10)

0.010 (0,25)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

UCC28083, UCC28084, UCC28085, UCC28086

UCC38083, UCC38084, UCC38085, UCC38086

SLUS488B - SEPTEMBER 2002 - REVISED MAY 2003

www.ti.com

MECHANICAL DATA

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

PACKAGE

14 PINS SHOWN

0,65

0,10

0,25

0,50

0,75

0,15 NOM

Gage Plane

9,80

9,60

7,90

7,70

6,60

6,40

4040064/F 01/97

0,30

6,60
6,20

0,19

4,30

4,50

0,15

1,20 MAX

5,10

4,90

3,10

2,90

A MAX

A MIN

DIM

PINS **

0,05

4,90

5,10

Seating Plane

- 8

NOTES:A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

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