UCC5640
SLUS314C JANUARY 2000 REVISED JUNE 2003
LOW VOLTAGE DIFFERENTIAL (LVD) SCSI 9 LINE TERMINATOR
1
www.ti.com
FEATURES
D
First LVD only Active Terminator
D
Meets SCSI SPI-2 Ultra2 (Fast-40), SPI-3 Ultra3
/ Ultra160 (Fast-80) and SPI-4 (Fast-160)
Ultra320 Standards
D
2.7-V to 5.25-V Operation
D
Differential Failsafe Bias
DESCRIPTION
The UCC5640 is an active terminator for low voltage
differential (LVD) SCSI networks. This LVD only design
allows the user to reach peak bus performance while
reducing system cost. The device is designed as an
active Y-terminator to improve the frequency response
of the LVD bus. Designed with a 1.5-pF channel
capacitance, the UCC5640 allows for minimal bus
loading for a maximum number of peripherals. With the
UCC5640, the designer will be able to comply with the
Fast-40 SPI-2, Fast-80 SPI-3 and Fast-160 SPI-4
specifications. The UCC5640 also provides a much
needed system migration path for ever improving SCSI
system standards. This device is available in the 24-pin
TSSOP and 28-pin TSSOP for ease of layout use.
The UCC5640 is not designed for use in single ended
(SE) or high voltage differential (HVD) systems.
BLOCK DIAGRAM
UDG98181
REF 1.25V
15
DISCNCT
27
LVD*
1
REG
11
DIFFB
4
L1
3
L1+
26
L9
25
L9+
56mV
SOURCE/SINK REGULATOR
REF 1.3V
1.3V
+
0.1V
0.7V > 0.5V
2.4V > 1.9V
HIGH IMPEDANCE RECEIVER
EVEN WITH POWER OFF
SINGLE
ENDED
HIGH POWER
DIFFERENTIAL
12
DIFSENS
SOURCE 5 15mA
SINK 200
A MAXIMUM (NOISE LOAD)
OPEN CIRCUIT ON POWER OFF
OR OPEN CIRCUIT IN A
DISABLED TERMINATOR MODE
10
A
28
TRMPWR
124
124
52
52
52
52
14
GND
2.7V to 5.25V
56mV
+
+
56mV
+
56mV
+
*28 pin package only
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
UCC5640
SLUS314C JANUARY 2000 REVISED JUNE 2003
2
www.ti.com
ORDERING INFORMATION
T
PACKAGED DEVICE
{
TA
TSSOP-24 (PW)
TSSOP-28 (PW)
0
C to 70
C
UCC5640PW24
UCC5640PW28
The TSSOP packages are available taped and reeled. Add TR suffix to device type (e.g.
UCC5640PW24TR) to order quantities of 2,000 devices per reel.
CONNECTION DIAGRAM
TSSOP24 (Top View)
PW Package
TSSOP28 (Top View)
PW Package
DIFFB
L6+
L8
L8+
L7
TRMPWR
L1+
N/C
L4
L3+
L4+
L1
L2+
L2
REG
L3
DIFSENS
L7+
L6
L5
N/C
GND 14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
16
17
18
19
20
21
22
23
24
25
26
27
28
L5+
N/C
DISCNCT
L9
L9+
LVD
DIFFB
L6+
L8
L8+
L7
TRMPWR
L1+
L4
L3+
L4+
L1
L2+
L2
REG
L3
DIFSENS
L7+
L6
L5
12
11
10
9
8
7
6
5
4
3
2
1
13
14
15
16
17
18
19
20
21
22
23
24
L5+
L9
L9+
GND
DISCNCT
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
TRMPWR voltage
2.7
5.25
V
Signal line voltage
0
3.6
V
Disconnect input voltage
0
TRMPWR
C
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
{}
UCC5640
UNIT
TRMPWR voltage
6
V
Signal line voltage
0 to 3.6
V
Package dissipation
1
W
Storage temperature, Tstg
65 to 150
Operating junction temperature, TJ
55 to 150
C
Lead temperature (soldering, 10 sec.)
300
C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect
to GND. Currents are positive into and negative out of, the specified terminal.
Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and
considerations of packages. All voltages are referenced to GND.
UCC5640
SLUS314C JANUARY 2000 REVISED JUNE 2003
3
www.ti.com
ELECTRICAL CHARACTERISTICS
T
A
= 0
C to 70
C, TRMPWR = 3.3 V, T
A
= T
J
, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
TRMPWR Supply Current Section
TRMPWR supply current
No load
25
mA
TRMPWR supply current
Disabled terminator
400
A
TRMPWR voltage
2.7
5.25
V
Regulator Section
1.25V regulator
DIFSENS connected to DIFFB
1.15
1.25
1.35
V
1.25V regulator source current
DIFSENS connected to DIFFB
100
80
mA
1.25V regulator sink current
DIFSENS connected to DIFFB
80
100
mA
1.3V regulator
DIFFB connected to GND
1.2
1.3
1.4
V
1.3V regulator source current
DIFSENS to GND
15
5
mA
1.3V sink current
DIFSENS to 3.3 V
50
200
A
Differential Termination Section
Differential impedance
2.5 mA to 4.5 mA
100
105
110
Common mode impedance
L+ connected to L
110
150
165
Differential bias voltage
No load, L+ or L
100
125
mV
Common mode bias
1.15
1.25
1.35
V
Output leakage, disconnect
DISCNCT, TRMPWR = 0 V to 5.25 V,
VLINE = 0.2 V to 5.25 V
10
400
nA
Output capacitance
Single ended measurement to ground (1)
3
pF
Low Voltage Differential (LVD) Status Bit Section
ISOURCE
VLOAD = 2.4 V
6
4
mA
ISINK
VLOAD = 0.4 V
2
5
mA
Disconnect & Differential Sense Input Section
DISCNCT threshold
0.8
2
V
Input current
At 0 V and 3.3 V
30
10
A
Differential sense SE to LVD threshold
0.5
0.7
V
Differential sense LVD to HPD threshold
1.9
2.4
V
NOTE:
(1) Ensured by design. Not production tested.
TERMINAL FUNCTIONS
TERMINAL(1)
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
DIFFB
10
Differential sense filter pin should be connected to a 4.7-
F capacitor and 50-k
resistor to diff
sense.
DIFSENS
11
The SCSI bus differential sense line to detect what type of devices are connected to the SCSI bus.
DISCNCT
13
Disconnect pin shuts down the terminator when it is not at the end of the bus.
GND
12
I
Ground reference for the device.
Ln
I
Negative line in differential applications for the SCSI bus.
Ln+
I
Positive line in differential applications for the SCSI bus.
LVD
I
Indicates that the bus is in LVD mode (28-pin package only).
REG
1
I
Regulator bypass; must be connected to a 4.7-
F capacitor to ground.
TRMPWR
24
I
VIN 2.7-V to 5.25-V power supply.
NOTE:
(1) 24-pin package.
UCC5640
SLUS314C JANUARY 2000 REVISED JUNE 2003
4
www.ti.com
APPLICATION INFORMATION
All SCSI buses require a termination network at each end to function properly. Specific termination requirements
differ, depending on which types of SCSI driver devices are present on the bus. The UCC5640 is a low-voltage
differential only device. It senses which types of drivers are present on the bus. If it detects the presence of a
single-ended or high-voltage differential driver, the UCC5640 will place itself in a high-impedance input state,
effectively disconnecting the chip from the bus.
The UCC5640 senses what drivers are present on the bus by the voltage on SCSI bus control line DIFFSENS,
which is monitored by the DIFFB input pin. The DIFSENS output pin on the UCC5640 attempts to drive a
DIFFSENS control line to 1.3 V. If only LVD devices are present, the DIFFSENS line will be successfully driven
to that voltage. If HVD drivers are present, they will pull the DIFFSENS line high. If any single-ended drivers
are present, they pull the DIFSENS line to ground (even if HVD drivers are also present on the bus). If the voltage
on the DIFFB is below 0.5 V or above 2.4 V, the UCC5640 enters the high-impedance SE/HVD state. If it is
between 0.7 V and 1.9 V, the UCC5640 enters the LVD mode. These thresholds accommodate differences in
ground potential that can occur between the ends of long bus lines.
Three UCC5640 devices are required at each end of the SCSI bus to terminate 27 lines (18 data, 9 control).
Every UCC5640 contains a DIFSENS driver, but only one should be used to drive the line at each end. The
DIFSENS pin on the other devices should be left unconnected.
On power up, the voltage on the TRMPWR pin rising above 2.7 V, the UCC5640 assumes the SE/HVD mode.
The DIFFB inputs on all three chips at each end of the bus should be connected together. Properly filtered, noise
on DIFFB will not cause a false mode change. There should be a shared 50-Hz noise filter implemented on
DIFFB at each end of the bus as close as possible to the DIFFB pins. This is implemented with a 50-k
resistor
between the DIFFB and DIFSENS pins, and a 4.7-
F capacitor from DIFFB to ground. See Figure 1, the typical
application diagram on page 6.
In LVD mode, the regulated voltage is switched to 1.25 V and a resistor network is presented to each line pair
that provides common-mode impedance of 150
and differential impedance of 105
. The lines in each
differential pair are biased so that when not driven, Line(n)+ and Line(n) are driven 56 mV below and above
the common-mode bias voltage of 1.25 V respectively.
In SE/HVD mode, all the terminating resistors are switched off the bus. The 1.25 V and 1.3 V (DIFSENS)
regulators are left on.
When the disconnect input (DISCNCT) is active (high), the terminating resistors are switched off the bus and
both voltage regulators are turned off to save power. The mode change filter/delay function is still active and
the LVD pin in the 28-pin package continues to indicate the correct bus mode.
UCC5640
SLUS314C JANUARY 2000 REVISED JUNE 2003
5
www.ti.com
APPLICATION INFORMATION
The UCC5640 operates down to a TRMPWR voltage of 2.7 V. This accommodates a 3.3-V system with
allowance for supply tolerance of +10%, a unidirectional fusing device and cable drop. The UCC3912 or
UCC3918 is recommended on a 3.3-V systems and the UCC3916 is recommended on 5-V systems in place
of a fuse and diode implementation, as its lower voltage drop provides additional voltage margin for the system.
Layout is important in all SCSI implementations and critical in SPI-3 and SPI-4 systems, which have stringent
requirements on both the absolute value of capacitance on differential signal lines and the balancing of
capacitance between paired lines and from pair-to-pair.
Feedthroughs, through-hole connections, and etch lengths need to be carefully balanced. Standard multilayer
power and ground plane spacing adds about 1 pF to each plane. Each feed-through will add 2.5 pF to 3.5 pF.
Enlarging the clearance holes on both power and ground planes reduces capacitance. Opening up the power
and ground planes under a through-hole connector reduces added capacitance in those applications.
Capacitance is also affected by components in close proximity on both sides of the board.
Table 1. Maximum Capacitance
SCSI CLASS
TRACE TO GND:
REQ, ACK, DATA,
PARITY, P_CRCA
TRACE TO TRACE:
REQ, ACK, DATA,
PARITY, P_CRCAALS
TRACE TO GND:
OTHER SIGNALS
TRACE TO TRACE:
OTHER SIGNALS
Ultra1
25 pF
N/A
25 pF
N/A
Ultra2
20 pF
10 pF
25 pF
13 pF
Ultra3/Ultra160
15 pF
8 pF
25 pF
13 pF
Ultra320
13 pF
6.5 pF
21 pF (est.)
10 pF (est.)
TI terminators are designed with very tightly controlled capacitance on their signal lines. Between the positive
and negative lines in a differential pair the difference is typically no more than 0.1 pF, and only 0.3 pF between
pairs.
Multilayer boards need to adhere to the 120-
impedance standard, including the connector and feedthroughs.
Bus traces are normally run on the outer layers of the board with 4-mil etch and 4-mil spacing between the two
lines in each differential pair, and a minimum of 8-mil spacing to adjacent pairs to minimize crosstalk. Microstrip
technology is too low in impedance and should not be used, they are designed for 50-
rather than 120-
differential systems.
Decoupling capacitors should be installed as close as possible to the following input pins of the UCC5640:
1.
TRMPWR: 4.7-
F capacitor to ground, 0.01-
F capacitor to ground (high frequency, low ESR)
2.
REG: 4.7-
F capacitor to ground, 0.01-
F capacitor to ground (high frequency, low ESR)
UCC5640
SLUS314C JANUARY 2000 REVISED JUNE 2003
6
www.ti.com
APPLICATION INFORMATION
UDG98100
REG
TRMPWR
DISCNCT
TRMPWR
DIFFB
REG
Termpower
Termpower
28
15
12
1
11
11
1
24
DISCNCT 13
CONTROL LINES (9)
50k
50k
DIFF SENSE
3
2
4
3
4.7
F
4.7
F
25
22
26
23
L1+
L1
L9+
L9
L1+
L1
L9+
L9
4.7
F
DIFFB
10
4.7
F
REG
TRMPWR
DISCNCT
TRMPWR
DIFFB
REG
28
15
1
11
1
24
DISCNCT 13
DATA LINES (9)
3
2
4
3
4.7
F
25
22
26
23
L1+
L1
L9+
L9
L1+
L1
L9+
L9
4.7
F
DIFFB
10
REG
TRMPWR
DISCNCT
TRMPWR
DIFFB
REG
28
15
1
11
1
24
DISCNCT 13
DATA LINES (9)
3
2
4
3
4.7
F
25
22
26
23
L1+
L1
L9+
L9
L1+
L1
L9+
L9
4.7
F
DIFFB
10
4.7
F
4.7
F
UCC5640PW28
UCC5640PW24
UCC5640PW24
UCC5640PW28
UCC5640PW24
UCC5640PW28
27
LVD
S2*
S1*
* CLOSE S1 AND S2 TO CONNECT TERMINATORS
12
11
11
12
NC
NC
NC
NC
Figure 1. Application Diagram
UCC5640
SLUS314C JANUARY 2000 REVISED JUNE 2003
7
www.ti.com
MECHANICAL DATA
PWP (R-PDSO-G**)
PowerPAD
PLASTIC SMALL-OUTLINE
4073225/F 10/98
0,50
0,75
0,25
0,15 NOM
Thermal Pad
(See Note D)
Gage Plane
28
24
7,70
7,90
20
6,40
6,60
9,60
9,80
6,60
6,20
11
0,19
4,50
4,30
10
0,15
20
A
1
0,30
1,20 MAX
16
14
5,10
4,90
PINS **
4,90
5,10
DIM
A MIN
A MAX
0,05
Seating Plane
0,65
0,10
M
0,10
0
8
20 PINS SHOWN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusions.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
UCC5640PW24
ACTIVE
TSSOP
PW
24
60
None
CU SNPB
Level-2-220C-1 YEAR
UCC5640PW24TR
ACTIVE
TSSOP
PW
24
2000
None
CU SNPB
Level-2-220C-1 YEAR
UCC5640PW28
ACTIVE
TSSOP
PW
28
50
None
CU SNPB
Level-2-220C-1 YEAR
UCC5640PW28TR
ACTIVE
TSSOP
PW
28
2000
None
CU SNPB
Level-2-220C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check
http://www.ti.com/productcontent
for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
11-Feb-2005
Addendum-Page 1
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
20
16
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
8
0,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM
PINS **
0,05
4,90
5,10
Seating Plane
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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