UCC5696
SLVS406B JUNE 2002 REVISED JUNE 2003
27 LINE LVD ONLY SCSI TERMINATOR FOR SPI 5
1
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FEATURES
D
Meets Ultra2 (SPI-2 LVD SCSI), Ultra3, Ultra
160 (SPI-3), Ultra320 (SPI-4), and Ultra640
(SPI-5) Standards
D
2.7-V to 5.25-V Termpwr Operation
D
Differential Fail-Safe Bias
D
I
2
C Bus Adjustable Impedance and
Differential Bias Current
D
80-Pin Low Profile Quad Flat Pack Package
(QFP)
APPLICATION DIAGRAM
DESCRIPTION
The UCC5696 is a 27-line LVD only SCSI
programmable terminator. The nominal settings
on power up are compliant to SPI-2 through SPI-4.
The programmable settings are used for SPI-5.
The UCC5696 uses the I
2
C to program the
differential impedance and the differential bias
current. The differential impedance is
programmed in 5-
increments from 55
to
130
using 4 bits (16 steps). The differential bias
current is programmed in 50
A from 0.7 mA to
1.45 mA using 4 bits (16 steps). The UCC5696
has the SPI-3 mode change delay, the typical
value is 200 ms.
UDG01093
REG
TERMPWR
ICAD0
Termpower
7
49
15
10
DIFSENS
CONTROL LINES (9)
1
2
30
29
L1+
L1
L9+
L9
DATA (9)
LOW BYTE 07
+ PARITY LINES
32
31
61
62
L10+
L10
L18+
L18
63
64
79
80
L19+
L19
L27+
L27
52
DISCNCT
ICBD
50
4.7
F
UCC5696
4.7
F
DATA (9)
HIGH BYTE 815
+ PARITY LINES
TERMPWR
REG
15
10
7
DIFSENS
1
2
30
29
L1+
L1
L9+
L9
32
31
61
62
L10+
L10
L18+
L18
Termpower
63
64
79
80
L19+
L19
L27+
L27
52
UCC5696
4.7
F
4.7
F
ICBC
51
16
DIFFB
16
DIFFB
ICAD6
43
49
50
51
43
ICAD0
ICBD
ICBC
ICAD6
I2 CBUS
I2 CBUS
DISCNCT
54
54
8
PVDD
8
PVDD
GND
GND
I2 C Address
20 k
20 k
0.1
F
0.1
F
I2 C Address
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
UCC5696
SLVS406B JUNE 2002 REVISED JUNE 2003
2
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DESCRIPTION (CONTINUED)
The UCC5696 can not be used for single-ended or HVD SCSI, the termination lines will open when it detects
either single-ended or HVD devices on the SCSI bus.
ORDERING INFORMATION
22 23
L17
L17+
L16
L16+
N/C
N/C
GND
N/C
DISCNT
ICBC
ICBD
ICAD0
ICAD1
ICAD2
ICAD3
ICAD4
ICAD5
ICAD6
L15+
L15
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
L1+
L1
L2+
L2
N/C
N/C
TERMPWR
PVDD
N/C
REG
N/C
SE
LVD
HVD
DIFSENS
DIFFB
L3
L3+
L4
L4+
25 26 27 28
PN PACKAGE
(TOP VIEW)
L22
79 78 77 76 75
80
74
L26
L26+
L25
L25+
L24
L24+
L23
L10
L1
1
L6
L6+
L7
L7+
L8
L8+
L9
72 71 70
73
29 30 31 32 33
69 68
21
L5
L21
67 66 65 64
34 35 36 37
L1
1+
L12
L12+
L13
L21+
L20
L20+
L19
L27
L27+
L13+
L14
38 39 40
L19+
L18
63 62 61
L23+
L22+
L18+
L9+
L5+
L10+
L14+
NOTE: N/C No connect
AVAILABLE OPTIONS
T
Disconnect
Packaged Devices
TA
Disconnect
Status
LQFP
0
C to 70
C
Regular
UCC5696PN
LQFP (PN) package is available taped and reeled. Add R suffix to device
type (e.g. UCC5696PNR) to order quantities of 1000 devices per reel.
UCC5696
SLVS406B JUNE 2002 REVISED JUNE 2003
3
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted)
Parameter
UCC5696
UNIT
TERMPWR voltage
6
V
Signal line voltage
0 to 6
V
Package power dissipation
1
W
Operating junction temperature, TJ
55 to 150
C
Storage temperature, Tstg
65 to 150
C
Lead temperature (soldering, 10 sec.), Tsol
300
C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage are with respect to ground. Currents are positive into, negative out of the specified terminal.
RECOMMENDED OPERATING CONDITIONS
TERMPWR voltage
2.7 V to 5.25 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ELECTRICAL CHARACTERISTICS
T
A
= 0
C to 70
C, TERMPWR = 2.7 V to 5.25 V, (unless otherwise specified, the measurements are specified at the
default impedance and bias current)
TERMPWR supply current
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
TERMPWR supply current
(No load)
65
mA
TERMPWR supply current
Disabled terminator
2.5
mA
TERMPWR voltage
2.7
5.25
V
regulator
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
1.25-V regulator
LVD mode,
0.5 V
VCM
2.0 V, all lines loaded
1.15
1.25
1.35
V
1.3-V regulator
Differential sense,
5 mA
IDIFSENS
50
A
1.2
1.3
1.4
V
1.25-V regulator source current
LVD mode,
VREG = 0 V
250
300
mA
1.25-V regulator sink current
LVD mode,
VREG = 3.3 V
250
300
mA
1.3-V regulator source current
Differential sense,
VDIFSENS = 0 V
5
15
mA
1.3-V regulator sink current
Differential sense,
VDIFSENS = 2.75 V
50
200
A
NOTES:
1. At powerup or after the device comes out of disconnect mode.
2. For SPI-2, SPI-3 and SPI-4.
3. Ensured by design and engineering test, but not production tested.
4. Current is the absolute value of current as some addresses are pulled high, while others are pulled low.
UCC5696
SLVS406B JUNE 2002 REVISED JUNE 2003
4
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ELECTRICAL CHARACTERISTICS
T
A
= 0
C to 70
C, TERMPWR = 2.7 V to 5.25 V, (unless otherwise specified, the measurements are specified at the
default impedance and bias current)
differential termination (default)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Differential impedance (1)
Default
100
105
110
Steps 5, 10, 20, 40
,
14
%
overall accuracy
55
130
Differential impedance steps
55
47.5
55
62.5
Differential impedance steps
130
112
130
147
The difference between all lines at any step
10
Common mode impedance (1)
Default
100
300
Common mode impedance (1)
Over the impedance adjustment range
75
400
Differential bias voltage (2)
Default I2C settings
100
125
mV
Default
1
1.1
Differential bias c rrent (1)
Steps 0.05, 0.1, 0.2, 0.4 mA
,
14
%
overall accuracy
0.70
1.45
mA
Differential bias current (1)
0.7 mA
0.6
0.7
0.8
mA
1.45 mA
1.25
1.45
1.65
Output leakage
Disabled,
TERMPWR 0 V < 5.25 V
400
nA
Output capacitance (3)
Single ended measurement to ground
3
pF
disconnect and diff sense input
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
DISCNT threshold
0.8
2.0
V
Input current DISCNT
10
30
A
Input current, ICBC, ICBD
1
1
A
Input current, ICAD06 (4)
10
30
A
Input current DIFF B
0 V
VDIFFB
2.75 V
1
1
A
DIFF B single ended to LVD threshold
0.5
0.7
V
DIFF B LVD to HPD threshold
1.9
2.4
V
time delay/filter
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Mode change delay (2)
100
190
310
ms
status line output characteristics
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Source current
VLOAD = 2.4 V
4
6
mA
Sink current
VLOAD = 0.4 V
2
5
mA
NOTES:
1. At powerup or after the device comes out of disconnect mode.
2. For SPI-2, SPI-3 and SPI-4.
3. Ensured by design and engineering test, but not production tested.
4. Current is the absolute value of current as some addresses are pulled high, while others are pulled low.
UCC5696
SLVS406B JUNE 2002 REVISED JUNE 2003
5
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Terminal Functions
TERMINAL
FUNCTION
NAME
NO.
I/O
FUNCTION
DIFSENS
15
O
The SCSI bus DIFF SENSE line detects what types of devices are connected to the SCSI bus.
DISCNT
52
I
The disconnect pin shuts down the terminator when it is not at the end of the bus. The disconnect pin low en-
ables the terminator.
DIFFB
16
I
Senses the bus mode, a 50-Hz filter is required, 0.1
F to ground and 20 k
to the SCSI bus DIFF SENSE line
with internal SPI-3 100-ms to 310-ms delay.
HVD
14
O
A high-voltage differential voltage level has been detected on the DIFF B pin. HVD pin high indicates that the
terminator is in high impedance mode.
ICBD
50
I/O
I2C bus data. Serial control for impedance and bias current adjustments.
ICBC
51
I
I2C bus clock.
ICAD06
I
I2C address.
Line n
O
Negative line for differential applications of the SCSI bus.
Line n+
O
Positive line for differential applications of the SCSI bus.
LVD
13
O
A low-voltage differential voltage level has been detected on the DIFF B pin. LVD pin high indicates that the ter-
minator is in LVD mode.
PVDD
8
I
Power supply for the regulator. PVDD should be tied to TERMPWR pin.
REG
10
O
Regulator bypass pin must be bypassed to ground with a 4.7-
F low ESR capacitor.
SE
12
O
A single ended voltage level has been detected on the DIFF B pin. SE pin high indicates that the terminator is in
high impedance mode.
TERMPWR
7
I
VIN 2.7-V to 5.25-V supply. TERMPWR should be bypassed to ground with a 4.7-
F low ESR capacitor.
UCC5696
SLVS406B JUNE 2002 REVISED JUNE 2003
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block diagram
UDG01094
REF 1.25 V
DISCNT
LVD
REG
DIFFB
L27
L27+
L1
L1+
SOURCE/SINK REGULATOR
REF 1.3 V
0.7 V to 0.5 V
2.4 V to 1.9 V
HIGH IMPEDANCE RECEIVER EVEN WITH POWER OFF
SINGLE ENDED
HIGH POWER DIFFERENTIAL
DIFSENS
OPEN CIRCUIT ON POWER OFF OR OPEN
CIRCUIT IN A DISABLED TERMINATOR MODE
10
A
124
124
52.5
*
52.5
*
52.5
*
52.5
*
4.7
F
GND
1.05 mA*
DIGITAL
FILTER
100 ms to 310 ms
HIPD
SE
LOW VOLTAGE DIFFERENTIAL
SWITCHES UP ARE HIGH IMPEDANCE
SWITCHES DOWN ARE LOW
VOLTAGE DIFFERENTIAL
ENABLE
SWITCH
I2C MESSAGE
CONTROLS
DIFFERENTIAL
BIAS CURRENT
AND
DIFFERENTIAL
IMPEDANCE
ICBC
ICBD
ICAD6
ICAD0
1.05 mA*
1.05 mA*
1.05 mA*
1.3 V +/ 0.1 V
TERMPWR
2.7 V to 5.25 V
* DEFAULT CAN BE ADJUSTED BY I2C MESSAGES
PVDD
TERMPWR
TERMPWR
TERMPWR
15 mA
ISOURCE
5 mA
50
A
ISINK
200
A
7
8
16
49
43
50
51
52
54
10
1
2
79
80
12
13
14
15
UCC5696
SLVS406B JUNE 2002 REVISED JUNE 2003
7
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APPLICATION INFORMATION
The DIFF SENSE line is driven by the terminator and monitored by the terminator DIFF B input pin. DIFF B has
a digital filter and a 100-ms to 310-ms delay before the mode of the terminator is changed to reflect the new
DIFF B input level. A set of comparators that allow for ground shifts determines the bus status as follows: any
DIFF SENSE signal below 0.5 V is single ended, between 0.7 V and 1.9 V is LVD SCSI, and above 2.4 V is HVD
SCSI.
The UCC5696 is high-impedance in SE and HVD SCSI bus modes.
Layout is very critical for Ultra320 and Ultra640 systems. Multilayer boards need to adhere to the impedance
120-
standard, including connectors and feed-throughs. This is normally done on the outer layers with 4-mil
etch and 4-mil spacing between the runs within a pair, and a minimum of 8-mil spacing to the next pair. The
spacing between the pairs reduces potential cross-talk. Beware of feed-throughs and through-hole connectors,
each of which adds a lot of capacitance. The standard power and ground plane spacing yields about 1 pF to
each plane; each feed-through adds about 2.5 pF to 3.5 pF. Enlarging the clearance holes on both power and
ground planes can reduce the capacitance, and opening up the power and ground planes under the connector
can reduce the capacitance for through hole connector applications. Microstrip technology is normally too low
of impedance and should not be used. It is designed for 50-
not 120-
differential systems.
Capacitance balance is critical for Ultra640; the balance capacitance is 0.5 pF per line while the balance
between pairs is 2 pF. The components are designed with very tight balance, typically 0.1 pF between pins in
a pair and 0.3 pF between pairs. Layout balance is critical, feed-throughs and etch length must be balanced,
and preferably no feed-throughs would be used. Capacitance for devices should be measured in the typical
application. Materials and components above and below the circuit board effect the capacitance.
The differential impedance is adjustable to match the impedance of the backplane or cable system, adjusting
for the loading change when drives are added. The high frequency roll off of the system can reduce the size
of the single bit transition to less than the size of the reflected wave on a heavily loaded system. Adjusting the
terminator to match the impedance of the system, which changes as drives are added, minimizes the reflection
from the terminator. Ultra640 SCSI must have each segment of the bus adjusted to reduce errors, SCSI domain
validation (SDV) defines the margining of the segments.
System testing has shown that reducing the terminator impedances to slightly lower than the bus impedance
reduces isolated 0 and 1 bit errors and increases system performace for Ultra160, Ultra320 and Ultrra640
speeds.
In 3.3-V Termpwr systems, the UCC3912 or UCC3918 should be used to replace the diode and fuse function.
This reduces the voltage drop, allowing for the cable voltage drop for the terminators on the far end of the cable.
3.3-V battery systems have a 10% tolerance, the UCC3912 or UCC3918 has less than 150-mV drop under load,
allowing for 150 mV-drop in the cable system. All Texas Instrument LVD and multimode terminators are
designed for 3.3-V systems, operating down to 2.7 V.
In 5-V Termpwr systems the UCC3916, UCC3912 or UCC3918 can be used to replace the diode and fuse
function. These reduce the voltage drop and protect the systems better than the diode and fuse or polyfuse.
UCC5696
SLVS406B JUNE 2002 REVISED JUNE 2003
8
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APPLICATION INFORMATION
I
2
C interface
The two-wire serial interface is used to access the terminator and to independently adjust both the differential
impedance and the differential bias current. This interface consists of one clock line, (SCL), and one serial data
line, (SDA).
The access cycle consists of the following and is shown in Figure 2:
1.
A start condition
2.
A slave address cycle
3.
A data cycle
4.
A stop condition
Start Condition (S)
SCL
SDA
Stop Condition (P)
Figure 1. I
2
C Start and Stop Condition
The start and stop conditions are shown in Figure 1. The high-to-low transition of SDA while SCL is high defines
the start condition. The low-to-high transition of SDA while SCL is high, defines the stop condition. The start and
stop conditions are initiated by the master device.
Each cycle, data or address, consists of 8 bits of serial data followed by one acknowledge bit generated by the
receiving device. During the acknowledge clock pulse (the ninth clock) the transmitting device must release the
SDA line. The receiving device then pulls down the SDA line so that it remains stable LOW during the HIGH
period of the acknowledge clock pulse.
slave address
The slave address of the UCC5696 terminator has 8 bits consisting of 7 bits of address along with 1 bit, the LSB,
reserved for the read/write information (1 for read and 0 for write). The 7-bit address is fully programmable.
UCC5696
SLVS406B JUNE 2002 REVISED JUNE 2003
9
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APPLICATION INFORMATION
write/read
The UCC5696 operates using only a single byte transfer (a byte of address followed by a second byte for data).
Following a start condition and an address byte, the UCC5696 responds with an acknowledge by pulling the
SDA line low during the ninth clock cycle, if it is the terminator's address.
In a write cycle, after receiving a data byte, the UCC5696 pulls the SDA low for one clock cycle. A stop condition
is initiated by the transmitting device after the acknowledge clock pulse. See Figure 2 for an example of a write
cycle.
A6
A5
A4
A3
A2
A0 R/W ACK D7
D6
D5
D4
D3
D2
D1
D0
ACK
A1
SDA
Device Address and Read/Write
Data Byte
Stop
Condition
Not
Acknowledge
from Master
Acknowledge
from Receiver
Start Condition
Figure 2. Write Cycle
In a read cycle, following the initial acknowledge for address, the UCC5696 becomes a transmitting device and
the master device becomes the receiver. At the end of the data byte, the not acknowledge, A, condition is
initiated by the master by keeping the SDA signal high before it asserts the stop condition. See Figure 3 for an
example of a read cycle.
A6
A5
A4
A3
A2
A0 R/W ACK D7
D6
D5
D4
D3
D2
D1
D0 ACK
A1
SDA
Device Address and Read/Write
Data Byte
Stop
Condition
Not
Acknowledge
from Master
Acknowledge
from Receiver
Start Condition
Figure 3. Read Cycle
data
Bit 7 (MSB) to bit 4 of the data byte are used to control the differential bias current. Bit 3 to bit 0 are used to control
the differential impedance. At powerup both differential bias current and differential impedance are set to
1.05 mA and 105
,
respectively. Reference Table 1 and 2 for other current and impedance settings. All these
values are nominal.
UCC5696
SLVS406B JUNE 2002 REVISED JUNE 2003
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APPLICATION INFORMATION
Table 1. Differential Bias Current Settings True
DIFFERENTIAL IBIAS (mA)
BIT7
(MSB)
BIT6
BIT5
BIT4
0.70
0
0
0
0
0.75
0
0
0
1
0.80
0
0
1
0
0.85
0
0
1
1
0.90
0
1
0
0
0.95
0
1
0
1
1.00
0
1
1
0
1.05 (See Note)
0
1
1
1
1.10
1
0
0
0
1.15
1
0
0
1
1.20
1
0
1
0
1.25
1
0
1
1
1.30
1
1
0
0
1.35
1
1
0
1
1.40
1
1
1
0
1.45
1
1
1
1
NOTE: Default settings
Table 2. Differential Impedance Settings True
DIFFERENTIAL IMPEDANCE (
)
BIT3
BIT2
BIT1
BIT0
55
0
0
0
0
60
0
0
0
1
65
0
0
1
0
70
0
0
1
1
75
0
1
0
0
80
0
1
0
1
85
0
1
1
0
90
0
1
1
1
95
1
0
0
0
100
1
0
0
1
105 (See Note)
1
0
1
0
110
1
0
1
1
115
1
1
0
0
120
1
1
0
1
125
1
1
1
0
130
1
1
1
1
NOTE: Default settings
UCC5696
SLVS406B JUNE 2002 REVISED JUNE 2003
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APPLICATION INFORMATION
Table 3. Characteristics of the SDA and SCL I/O Stages for Standard/Fast-Mode
PARAMETER
SYMBOL
STANDARD MODE
FAST MODE
UNIT
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNIT
Termpwr voltage
VDD
2.7
5.25
2.7
5.25
V
Low-level input voltage
VIL
0.5
0.3 x VDD
0.5
0.3 x VDD
V
High-level input voltage
VIH
0.7 x VDD
0.7 x VDD
V
Hyst of schmitt-trigger input
VHYS
N/A
N/A
0.15
V
Low-level input at 3-mA sink
VOL
0
0.4
0
0.4
V
Pulse width of spikes which must be
suppressed by input filter
tSP
N/A
N/A
0
50
ns
Table 4. Timing Characteristics for I
2
C Interface
PARAMETER
SYMBOL
STANDARD MODE
FAST MODE
UNIT
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNIT
Clock frequency, SCL
fSCL
0
100
0
400
kHz
Pulse duration, SCL high
tW(H)
4
0.6
s
Pulse duration, SCL low
tW(L)
4.7
1.3
s
Rise time, SCL to SDA
tr
1000
300
ns
Fall time, SCL to SDA
tf
300
300
ns
setup time, SDA to SCL
tSU1
250
100
ns
Hold time, SCL to SDA
th1
0.30
3.45
0.30
0.90
s
Bus free time between stop and start
condition
tbuf
4.7
1.3
s
Setup time, SCL to start condition
tSU2
4.7
0.6
s
Hold time, start condition to SCL
th2
4
0.6
s
Setup time, SCL to stop condition
tSU2
4
0.6
s
tsu2
th2
tsu1
tW(H)
tW(L)
th1
tf
tr
tsu3
tbuf
SCL
SDA
Figure 4. SCL and SDA
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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