SN74ACT16373Q-EP
16-BIT D-TYPE TRANSPARENT LATCH
WITH 3-STATE OUTPUTS
SCAS678B MAY 2002 REVISED JULY 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Controlled Baseline
One Assembly/Test Site, One Fabrication
Site
D
Extended Temperature Performance of
40
C to 125
C
D
Enhanced Diminishing Manufacturing
Sources (DMS) Support
D
Enhanced Product Change Notification
D
Qualification Pedigree
D
Member of the Texas Instruments
Widebus
Family
D
Inputs Are TTL-Voltage Compatible
D
3-State Bus Driving True Outputs
D
Full Parallel Access for Loading
D
Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, highly
accelerated stress test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life.
description
The SN74ACT16373Q-EP is a 16-bit D-type
transparent latch with 3-state outputs, designed
specifically for driving highly capacitive or
relatively low-impedance loads. It is particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
This device can be used as two 8-bit latches or one 16-bit latch. The Q outputs of the latches follow the data
(D) inputs if the latch-enable (LE) input is taken high. When LE is taken low, the Q outputs are latched at the
levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the outputs in either a normal logic state (high or low
logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
in a bus-organized system, without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
Copyright
2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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48
47
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40
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27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1LE
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2LE
DL PACKAGE
(TOP VIEW)
Widebus is a trademark of Texas Instruments.
SN74ACT16373Q-EP
16-BIT D-TYPE TRANSPARENT LATCH
WITH 3-STATE OUTPUTS
SCAS678B MAY 2002 REVISED JULY 2002
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
40
C to 125
C
SSOP DL
Tape and reel
SN74ACT16373QDLREP
ACT16373QEP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each section)
INPUTS
OUTPUT
OE
LE
D
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic diagram (positive logic)
1OE
1LE
1D1
To Seven Other Channels
1Q1
2OE
2LE
2D1
2Q1
To Seven Other Channels
1
48
47
24
25
36
C1
1D
13
2
C1
1D
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
24 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
24 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
260 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at T
A
= 55
C (in still air) (see Note 2): DL package
1.2 W
. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150
C and a board trace length of 750 mils.
SN74ACT16373Q-EP
16-BIT D-TYPE TRANSPARENT LATCH
WITH 3-STATE OUTPUTS
SCAS678B MAY 2002 REVISED JULY 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
VCC
Supply voltage (see Note 4)
4.5
5.5
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
16
mA
IOL
Low-level output current
16
mA
D
t/
D
v
Input transition rise or fall rate
0
10
ns/V
TA
Operating free-air temperature
40
125
C
NOTES:
3. Unused inputs should be tied to VCC through a pullup resistor of approximately 5 k
W
or greater to prevent them from floating. Refer
to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4. All VCC and GND pins must be connected to the proper-voltage power supply.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
IOH = 50
m
A
4.5 V
4.4
4.4
IOH = 50
m
A
5.5 V
5.4
5.4
VOH
IOH = 16 mA
4.5 V
3.94
3.7
V
OH
IOH = 16 mA
5.5 V
4.94
4.7
IOH = 24 mA
5.5 V
3.85
IOL = 50
m
A
4.5 V
0.1
0.1
IOL = 50
m
A
5.5 V
0.1
0.1
VOL
IOL = 16 mA
4.5 V
0.36
0.5
V
OL
IOL = 16 mA
5.5 V
0.36
0.5
IOL = 24 mA
{
5.5 V
0.5
II
VI = VCC or GND
5.5 V
0.1
1
m
A
IOZ
VO = VCC or GND
5.5 V
0.5
10
m
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
160
m
A
D
ICC
One input at 3.4 V,
Other inputs at GND or VCC
5.5 V
0.9
1
mA
Ci
VI = VCC or GND
5 V
4.5
pF
Co
VI = VCC or GND
5 V
12
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL-voltage levels rather than 0 V to VCC.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
tw
Pulse duration, LE high
4
4
ns
tsu
Setup time, data before LE
1
1
ns
th
Hold time, data after LE
5
5
ns
SN74ACT16373Q-EP
16-BIT D-TYPE TRANSPARENT LATCH
WITH 3-STATE OUTPUTS
SCAS678B MAY 2002 REVISED JULY 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
D
Q
3.8
7.9
9.4
3.8
11.8
ns
tPHL
D
Q
3.1
8.2
9.7
3.1
13
ns
tPLH
LE
Q
4.6
9.3
10.8
4.6
13.7
ns
tPHL
LE
Q
4.5
9.1
10.5
4.5
13
ns
tPZH
OE
Q
3.1
8
9.5
3.1
13
ns
tPZL
OE
Q
3.8
9.4
11.1
3.8
15.1
ns
tPHZ
OE
Q
5.3
8.6
9.9
5.3
11
ns
tPLZ
OE
Q
4.3
7.4
8.7
4.3
9.8
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
C d
Power dissipation capacitance per latch
Outputs enabled
CL = 50 pF
f = 1 MHz
43
pF
Cpd
Power dissipation capacitance per latch
Outputs disabled
CL = 50 pF,
f = 1 MHz
4.5
pF
SN74ACT16373Q-EP
16-BIT D-TYPE TRANSPARENT LATCH
WITH 3-STATE OUTPUTS
SCAS678B MAY 2002 REVISED JULY 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
VCC
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
VCC
0 V
50% VCC
20% VCC
50% VCC
80% VCC
0 V
3 V
GND
Open
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
GND
TEST
S1
3 V
0 V
1.5 V
1.5 V
tw
VOLTAGE WAVEFORMS
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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