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TE
CH
tm
Preliminary
T14L1024A
TM Technology, Inc. reserves the right P. 1
Publication Date: SEP. 2002
to change products or specifications without notice.
Revision:0.F
SRAM
128K X 8 HIGH SPEED
CMOS STATIC RAM
FEATURES
Fast Address Access Times : 10/12/15ns
Single 3.3V 0.3V power supply
Low Power Consumption : 110/105/100mA
TTL I/O compatible
2.0V data retention mode
Automatic power-down when deselected
Available packages :
32-pin 300 mil DIP/SOJ & 32-pin SOP/TSOP-I
Industry Standard Pin Assignment

PIN CONFIGURATION
TSOP-I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A15
A14
A13
A12
WE
CE2
A11
VCC
NC
A10
A9
A8
A7
A6
A5
A4
OE
A16
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A1
A2
A3
GENERAL DESCRIPTION
The T14L1024A is a one-megabit density, fast
static random access memory organized as 131,072
words by 8 bits. It is designed for use in high
performance
memory applications such as main
memory storage and high speed communication
buffers. Fabricated using high performance CMOS
technology, access times down to 10ns are achieved.
Memory expansion by banking is easily
accomplished using the chip enable pins CE1 and
CE2. This device is packaged in a standard 32-pin
300 mil DIP/SOJ and 32-pin SOP/TSOP-I.
BLOCK DIAGRAM
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A16
Address Inputs
I/O0 - I/O7
Data Inputs/Outputs
/CE1,CE2
Chip Select Inputs
/WE Write
Enable
/OE Output
Enable
Vcc Power
Supply
Vss Ground
PART NUMBER EXAMPLES
PACKAGE SPEED
T14L1024A-10J SOJ 300mil 10ns
T14L1024A-10P TSOP-I 8x13.4mm 10ns
T14L1024A-10H TSOP-I 8x20mm 10ns
T14L1024A-10N DIP 300mil
10ns
T14L1024A-10D SOP
10ns
A8
A9
A7
A6
A5
A3
A4
A2
A1
A0
I/O0
I/O1
A10
NC
28
27
26
25
23
24
22
21
20
19
18
17
32
29
1
2
3
4
6
5
7
8
9
10
11
12
15
16
Vcc
A12
A13
A14
A15
A16
I/O7
I/O6
I/O5
A11
CE2
W E
OE
CE1
I/O2
Vss
30
31
13
14
I/O4
I/O3
DIP
/
SOJ
/
SOP
DECODER
A0
A16
CE2
WE
OE
I/O7
Vcc
DATA I/O
CORE
ARRAY
Vss
CE1
I/O0
.
.
.
.
.
.
.
TE
CH
tm
Preliminary
T14L1024A
TM Technology, Inc. reserves the right P. 2
Publication Date: SEP. 2002
to change products or specifications without notice.
Revision:0.F
DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
PARAMETER SYM
RATING
UNIT
Power Supply Voltage
Vcc
-0.5 to 4.6
V
Input Voltage
V
IN
-0.5 to Vcc+0.5
V
Output Voltage
V
OUT
-0.5 to Vcc+0.5
V
Operating Temperatrue
T
OPR
0 to +70
C
Storage Temperature
T
STG
-55 to +150
C
Power Dissipation
P
D
1.0 W
Short Circuit Output Current
I
OUT
50 mA
TRUTH TABLE
CE1
CE2
OE
WE
MODE I/O0-
I/O7 Vcc
H X X X Not
Selected
High-Z
I
SB,
I
SB1
X L X X Not
Selected High-Z
I
SB,
I
SB1
L H H H Output
Disable High-Z
Icc
L H L H
Read
Data
Out
Icc
L H X L
Write
Data
In
Icc
OPERATING CHARACTERISTICS
(Vcc = 3.3V
0.3V, Ta = 0 to 70
C)
PARAMETER SYM. TEST
CONDITIONS
MIN.
MAX.
UNIT
Power Supply Voltage
Vcc
3.0
3.6
V
Input Low Voltage
V
IL
-0.5
0.8
V
Input High Voltage
V
IH
2.1
Vcc+0.3
V
Input Leakage Current
I
LI
V
IN
=Vss to Vcc
- 5
uA
Output Leakage Current
I
LO
V
IN
=Vss to Vcc ,
CE1
= V
IH
or CE2
= V
IL
or OE = V
IH
or WE = V
IL
- 5
uA
Output Low Voltage
V
OL
I
OL
= 4.0 mA
- 0.4
V
Output High Voltage
V
OH
I
OH
=-2.0 mA
2.4
-
V
Operating Power
Icc
CE1
=
V
IL
10ns - 110 mA
Supply Current
CE2 = V
IH
;f=max
12ns - 105 mA
IO = 0mA
15ns
-
100
mA
Standby Power
I
SB
CE1
=
V
IH
, CE2 = V
IL
, IO = 0mA
- 25
mA
Supply Current
I
SB1
Vcc = max;
CE1
> Vcc-0.2V or CE2<
Vss+0.2V; f=0mhz; IO = 0mA
- 5
mA
Note: Typical characteristics are at Vcc = 3.3V, Ta = 25
C
TE
CH
tm
Preliminary
T14L1024A
TM Technology, Inc. reserves the right P. 3
Publication Date: SEP. 2002
to change products or specifications without notice.
Revision:0.F
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYM
MIN
TYP
MAX
UNIT
Supply Voltage
Vcc
Typ-0.3
3.3
Typ+0.3
V
Input Voltage, low
V
IL
-0.3
-
0.8
V
Input Voltage, high
V
IH
2.1
-
Vcc+0.3
V
Ambient Temperature
T
A
0
-
70
C
CAPACITANCE
PARAMETER SYMBOL
CONDITION
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
6
pF
Input/ Output Capacitance
C
I/O
V
OUT
= 0V
8 pF
Note: These parameters are sampled but not 100% tested.
AC TEST CONDITIONS
PARAMETER CONDITIONS
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3.0 ns
Input and Output Timing Reference Level
1.5V
Output Load
C
L
=30pF,
I
OH
/
I
OL
= -2mA/4mA

AC TEST LOADS AND WAVEFORM
RL=50 ohm
OUTPUT
Zo=50 ohm
30pF
R1 319 ohm
3.3V
OUTPUT
5pF
Including
Jig and
Scope
R2
353 ohm
(For T
CLZ
, T
OLZ
, T
CHZ
, T
OHZ
, T
WHZ
, T
OW
)
Vt=1.5V
TE
CH
tm
Preliminary
T14L1024A
TM Technology, Inc. reserves the right P. 4
Publication Date: SEP. 2002
to change products or specifications without notice.
Revision:0.F
AC CHARACTERISTICS
(
Vcc
=3.3V
0.3V, Vss = 0V, Ta = 0 to 70
C)
(1) READ CYCLE
T14L1024A-10 T14L1024A-12 T14L1024A-15
PARAMETER SYM.
MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
Read Cycle Time
t
RC
10 - 12 - 15 - ns
Address Access Time
t
AA
- 10 - 12 - 15
ns
Chip Enable Access Time
t
ACS
- 10 - 12 - 15
ns
Output Enable to Output Valid
t
AOE
- 6 - 7 - 7
ns
Chip Enable to Output in Low Z
t
CLZ*
3 - 3 - 3 - ns
Output Enable to Output in Low Z
t
OLZ*
0 - 0 - 0 - ns
Chip Disable to Output in High Z
t
CHZ*
- 5 - 6 - 7
ns
Output Disable to Output in High Z
t
OHZ*
- 5 - 6 - 7
ns
Output Hold from Address Change
t
OH
3 - 3 - 3 - ns
* These parameters are sampled but not 100% tested.

(2)WRITE CYCLE
T14L1024A-10 T14L1024A-12 T14L1024A-15
PARAMETER SYM.
MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
Write Cycle Time
t
WC
10 - 12 - 15 - ns
Chip Enable to End of Write
t
CW
8 - 10 - 11 - ns
Address Valid to End of Write
t
AW
8 - 10 - 11 - ns
Address Setup Time
t
AS
0 - 0 - 0 - ns
Write Pulse Width
t
WP
8 - 10 - 11 - ns
Write Recovery Time
t
WR
0 - 0 - 0 - ns
Data Valid to End of Write
t
DW
6 - 8 - 8 - ns
Data Hold from End of Write
t
DH
0 - 0 - 0 - ns
Write to Output in High Z
t
WHZ*
- 5 - 6 - 6
ns
Output Disable to Output in High Z
t
OHZ*
- 5 - 6 - 7
ns
Output Active from End of Write
t
OW
0 - 0 - 0 - ns
* These parameters are sampled but not 100% tested.
TE
CH
tm
Preliminary
T14L1024A
TM Technology, Inc. reserves the right P. 5
Publication Date: SEP. 2002
to change products or specifications without notice.
Revision:0.F
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
Address
D
out
t
O H
t
AA
t
R C
t
O H
READ CYCLE 2
(Chip Enable Controlled)
CE1
D
out
CE2
t
CLZ
t
A CS
t
O H Z
DON'T CARE
UNDEFINED
Address
t
AA
t
R C
t
O H
O E
t
CH Z
t
A O E
t
O LZ