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TE
CH
tm
T15N1024A
TM Technology Inc. reserves the right P. 1
Publication Date: FEB. 2003
to change products or specifications without notice.
Revision:E
SRAM
128K X 8 LOW POWER
CMOS STATIC RAM
FEATURES
Low-power consumption
- Active: 40mA at 55ns (Max.)
- CMOS Stand-by: 10uA (Max.)
55/70/100 ns access time
Equal access and cycle time
Single +2.4V to 3.6V Power Supply
TTL compatible , Tri-state output
Common I/O capability
Automatic power-down when deselected
Available in 32-pin SOP ,TSOP-I(8x20mm),
TSOP-I(8x13.4mm) ,48-pin CSP packages
Operating temperature :
Commercial : 0 ~ +70
C
Industrial : -40 ~ +85
C
PART NUMBER EXAMPLES
PART NO.
PACKAGE
CODE
Operating
Temperature
T15N1024A-55D
T15N1024A-70H
T15N1024A-100P
T15N1024A-100C
D=SOP
H=TSOP-I(8x20)
P=TSOP-I(8x13.4)
C=CSP
0 ~ +70
C
T15N1024A-55DI
T15N1024A-70HI
T15N1024A-100PI
T15N1024A-100CI
D=SOP
H=TSOP-I(8x20)
P=TSOP-I(8x13.4)
C=CSP
-40 ~ +85
C
GENERAL DESCRIPTION
The T15N1024A is a very Low Power CMOS
Static RAM organized as 131,072 words by 8 bits.
That operates on a wide voltage range from 2.4V
to 3.6V power supply, Fabricated using high
performance CMOS technology, Inputs and
three-state outputs are TTL compatible and allow
for direct interfacing with common system bus
structures. Data retention is guaranteed at a power
supply voltage as low as 1.5V.
BLOCK DIAGRAM
DECODER
A0
A16
I/O8
Vcc
.
.
.
.
.
.
DATA I/O
CORE
ARRAY
Vss
I/O1
WE
OE
CE1
CONTROL
CIRCUIT
CE2
TE
CH
tm
T15N1024A
TM Technology Inc. reserves the right P. 2
Publication Date: FEB. 2003
to change products or specifications without notice.
Revision:E
PIN CONFIGURATIONS
SOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
VDD
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O8
I/O7
I/O6
I/O5
I/O4
T S O P -I
(8x20m m )
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A 11
A 9
A 8
A 13
W E
C E 2
A 15
V D D
N C
A 16
A 14
A 12
A 7
A 6
A 5
A 4
O E
A 10
C E 1
I/O 8
I/O 7
I/O 6
I/O 5
I/O 4
V S S
I/O 3
I/O 2
I/O 1
A 0
A 1
A 2
A 3
T S O P -I
(8x13.4m m )
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A 11
A 9
A 8
A 13
W E
C E 2
A 15
V D D
N C
A 16
A 14
A 12
A 7
A 6
A 5
A 4
O E
A 10
C E 1
I/O 8
I/O 7
I/O 6
I/O 5
I/O 4
V S S
I/O 3
I/O 2
I/O 1
A 0
A 1
A 2
A 3
A0
A1
I/O5
VDD
VSS
I/O6
I/O7
I/O8
A9
A10
NC
OE
NC
CE1
A16
A11
A12
A15
A13
A14
I/O4
I/O3
A5
A8
VDD
VSS
A2
I/O2
I/O1
CE2
A3
A6
A7
A4
WE
NC
A
6
5
4
3
2
1
H
G
F
E
D
C
B
48-CSP
TOP VIEW
PIN DESCRIPTIONS
SYMBOL DESCRIPTIONS
SYMBOL DESCRIPTIONS
A0 ~ A16 Address inputs
OE
Output enable input
I/O0~I/O8 Data inputs/outputs
V
DD
Power
supply
CE1
,
CE2 Chip enable
V
SS
Ground
WE
Write enable input
NC No
connection
TE
CH
tm
T15N1024A
TM Technology Inc. reserves the right P. 3
Publication Date: FEB. 2003
to change products or specifications without notice.
Revision:E
ABSOLUTE MAXIMUM RATINGS*
PARAMETER SYM
MIN.
MAX.
UNIT
Voltage on Any Pin Relative to Gnd
V
R
-0.5 +4.6
V
V
Power Dissipation
P
D
- 0.7 W
Storage Temperature
T
STG
-55 +150
C
commercial 0
+70
Operating
Temperature
industrial
Ta
-40 +85
C

*Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to
the device. This is a stress rating only and function operation of the device at these or any other
conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.


TRUTH TABLE
CE 1
CE2
WE
OE
DATA MODE
H X X X
High-Z
Standby
X L X X
High-Z
Standby
L H H L
Data
Out
Active,
Read
L H H H
High-Z
Active,
Output
Disable
L H L X
Data
In
Active,
Write
*Note: X = Don't Care, L = Low, H = High
TE
CH
tm
T15N1024A
TM Technology Inc. reserves the right P. 4
Publication Date: FEB. 2003
to change products or specifications without notice.
Revision:E
OPERATING CHARACTERISTICS
(Vcc = 2.4 to 3.6V, Gnd = 0V, Ta =
0 ~ +70
C
/-40
C to 85
C)
-55 -70 -100
PARAMETER SYM. TEST
CONDITIONS
Min Max Min Max Min Max
UNIT
Input Leakage
Current
I
LI
Vcc = Max,
V
IN
= Gnd to Vcc
- 1 - 1 - 1 uA
Output Leakage
Current
I
LO
CE1
= V
IH
or CE2= V
IL
or OE = V
IH
or WE = V
IL
V
OUT
= Gnd to Vcc
- 1 - 1 - 1 uA
Operating Power
Supply Current
I
CC
CE1
= V
IL
,CE2= V
IH,
WE
=V
IH,
OE
= V
IH
,
V
IN
= V
IH
or V
IL,
I
OUT
=0mA
- 2 - 2 - 2 mA
I
CC1
Cycle time=1us,
100% duty, I
OUT
=0mA,
CE1
0.2V,
CE2
V
CC
-0.2V,
V
IN
0.2V
- 3 - 3 - 3 mA
Average Operating
Current
I
CC2
Cycle time=min,
100% duty, I
OUT
=0mA,
CE1
= V
IL
,CE2= V
IH ,
V
IN
= V
IH
or V
IL
- 40 - 35 - 25 mA
Standby Power
Supply Current
(TTL Level)
I
SB
CE1
=
V
IH
CE2= V
IL
- 0.5 - 0.5 - 0.5 mA
Standby Power
Supply Current
(CMOS Level)
I
SB1
CE1
Vcc-0.2V,
CE2
V
CC
-0.2V
or CE2
0.2V
V
IN
0.2V or
V
IN
Vcc-0.2V
- 10 - 10 - 10
u
A
Output Low Voltage
V
OL
I
OL
= 1.0mA
- 0.4 - 0.4 - 0.4 V
Output High Voltage
V
OH
I
OH
= -0.5 mA
2.1 - 2.1 - 2.1 - V
TE
CH
tm
T15N1024A
TM Technology Inc. reserves the right P. 5
Publication Date: FEB. 2003
to change products or specifications without notice.
Revision:E
RECOMMENDED OPERATING CONDITIONS
(Ta =
0 ~ +70
C
/-40
C to 85
C**)
PARAMETER SYM MIN
MAX
UNIT
Vcc 2.4 3.6 V
Supply Voltage
Gnd 0.0 0.0 V
V
IH
1.6 Vcc+0.2 V
Input Voltage
V
IL
-0.3 0.4 V

CAPACITANCE
(f = 1 MHz, Ta = 25
C,)
PARAMETER SYMBOL
CONDITION
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
6 pF
Input/ Output Capacitance
C
I/O
V
IN
=
V
OUT
= 0V
8 pF
Note: This parameter is guaranteed by device characterization and is not production tested.
AC TEST CONDITIONS
PARAMETER CONDITIONS
Input Pulse Levels
0.2V to 2.1V
Input Rise and Fall Times
3.0 ns
Input and Output Timing Reference Level
1.4V
C
L
=30pF+1TTL Load(55ns/70ns)
Output Load
C
L
=100pF+1TTL Load(Load for 100ns)
AC TEST LOADS AND WAVEFORM
DQ
Z
0
= 50 ohm
50 ohm
30 pF
Vt =1.4V
Fig.A * Including Scope and Jig Capacitance
TTL
C
L
*
Fig.B Output Load Equivalent
R
L
C
L