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Электронный компонент: T15N1M16A-70JI

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TE
CH
tm
T15N1M16A
TM Technology Inc. reserves the right P. 1
Publication Date: JUL . 2002
to change products or specifications without notice.
Revision: A
SRAM
64K X 16 LOW POWER
CMOS STATIC RAM
FEATURES
Fast access time : 55/70/100 ns
Single +2.4 to 3.6V Power Supply
Low power supply current :
- Operating :30mA(max)
- Standby : 10uA
TTL compatible , Tri-state output
Common I/O capability
Automatic power-down when deselected
Full static operation, no clock or refresh required
Available packages type :
- 44-PIN SOJ (400 mil)
- 44-PIN TSOP-II (400 mil)
- 48-PIN CSP
Operating temperature :
- 0 ~ +70
C
- -40 ~ +85
C
PART NUMBER EXAMPLES
PART NO.
PACKAGE
CODE
Operating
Temperature
T15N1M16A-70J
T15N1M16A-70S
T15N1M16A-70C
J=SOJ
S=TSOP-II
C= CSP
0 ~ +70
C
T15N1M16A-70JI
T15N1M16A-70SI
T15N1M16A-70CI
J=SOJ
S=TSOP-II
C= CSP
-40 ~ +85
C
GENERAL DESCRIPTION
The T15N1M16A is a low power CMOS Static
RAM organized as 65,536 words by 16 bits. That
operates on a wide voltage range from +2.4 to 3.6V
power supply, Fabricated using high performance
CMOS technology, Inputs and three-state outputs
are TTL compatible and allow for direct interfacing
with common system bus structures. Data retention
is guaranteed at a power supply voltage as low as
1.5V.

BLOCK DIAGRAM
DECODER
A0
A15
I/O16
Vcc
.
.
.
.
.
DATA I/O
CORE
ARRAY
Vss
I/O1
WE
OE
CE
CONTROL
CIRCUIT
UB
LB
TE
CH
tm
T15N1M16A
TM Technology Inc. reserves the right P. 2
Publication Date: JUL . 2002
to change products or specifications without notice.
Revision: A
PIN CONFIGURATIONS
SOJ
&
TSOP-II
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
NC
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC

48-Ball CSP TOP VIEW (Ball Down)
L B
O E
I/ O 9
V C C
V S S
I/ O 1 0
I/ O 1 5
I/ O 1 6
N C
A 8
A 1 4
N C
A 1 5
A 1 2
A 1 3
A 9
A 1 0
W E
A 1 1
N C
I/ O 8
I/ O 7
A 6
N C
V C C
V S S
U B
I/ O 3
I/ O 1
A 0
A 1
A 2
C E
A 4
A 3
A 5
A
6
5
4
3
2
1
H
G
F
E
D
C
B
I/ O 1 1
I/ O 1 2
I/ O 1 3
I/ O 1 4
N C
N C
A 7
N C
I/ O 2
I/ O 4
I/ O 5
I/ O 6
PIN DESCRIPTIONS
SYMBOL DESCRIPTIONS
SYMBOL DESCRIPTIONS
A0 ~ A15 Address inputs
LB
Lower byte (I/O 1~8)
I/O1~I/O16 Data inputs/outputs
UB
Upper byte (I/O 9~16)
CE
Chip enable
VCC
Power supply
WE
Write enable input
V
SS
Ground
OE
Output enable input
NC No
connection
TE
CH
tm
T15N1M16A
TM Technology Inc. reserves the right P. 3
Publication Date: JUL . 2002
to change products or specifications without notice.
Revision: A
ABSOLUTE MAXIMUM RATINGS*
PARAMETER SYM
MIN.
MAX.
UNIT
Voltage on Any Pin Relative to VSS
V
R
-0.5 +4.6
V
V
Power Dissipation
P
D
- 0.7 W
Storage Temperature
T
STG
-55 +150
C
Temperature Under Bias
I
BIAS
0 / -40
+70 / +85
C

*Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to
the device. This is a stress rating only and function operation of the device at these or any other
conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.


TRUTH TABLE
CE
OE
WE
LB
UB
I/O 1~8
I/O 9~16
MODE
Power
H X* X* X* X* High-Z
High-Z
Deselected
Standby
X* X* X* H H High-Z
High-Z
Deselected
Standby
L H H L X* High-Z High-Z Output
Disabled
Active
L H H X* L High-Z High-Z Output
Disabled
Active
L L H L H Data
Out High-Z Lower
Byte
Read
Active
L
L
H
H
L
High-Z
Data Out
Upper Byte Read
Active
L L H L L Data
Out Data
Out
Word
Read
Active
L
X*
L
L
H
Data In
High-Z
Lower Byte Write
Active
L
X*
L
H
L
High-Z
Data In
Upper Byte Write
Active
L
X*
L
L
L
Data In
Data In
Word Write
Active
*Note: X = Don't Care (Must be low or high state), L = Low, H = High
RECOMMENDED OPERATING CONDITIONS
(Ta = 0
C to +70
C / -40
C ~ +85
C *)
PARAMETER SYM
MIN
TYP
MAX
UNIT
Vcc 2.4 - 3.6 V
Supply Voltage
V
SS
0.0 0.0 0.0
V
V
IH
2.0 - Vcc+0.3 V
Input Voltage
V
IL
-0.5* - 0.4
V
*
V
IL
min = -1.0V for pulse width less than
t
RC
/2
TE
CH
tm
T15N1M16A
TM Technology Inc. reserves the right P. 4
Publication Date: JUL . 2002
to change products or specifications without notice.
Revision: A
OPERATING CHARACTERISTICS
(Vcc =
+2.4 to 3.6V
,
V
SS
= 0V, Ta = 0
C to +70
C / -40
C to +85
C)
-55 -70 -100
PARAMETER SYM. TEST
CONDITIONS
Min Max Min Max Min Min
UNIT
Input Leakage
Current
I
LI
Vcc = Max,
VIN = V
SS
to Vcc
-1 1 -1 1 -1 1
uA
Output Leakage
Current
I
LO
CE
= VIH
or
OE
= VIH
or
WE
= VIL
VIO = V
SS
to Vcc
-1 1 -1 1 -1 1
uA
Operating Power
Supply Current
I
CC
CE
= VIL,
VIN = VIH or VIL,
IOUT=0mA
Cycle time=min,
100% duty
- 30 - 25 - 20
mA
Standby Power
Supply Current
(TTL Level)
I
SB
CE
=
V
IH
or
LB
=
UB
=
V
IH
other input= VIL or
V
IH
- 0.3 - 0.3 - 0.3
mA
Standby Power
Supply Current
(CMOS Level)
I
SB1
CE
Vcc-0.2V or
LB
=
UB
Vcc-0.2V,
VIN
0.2V or
VIN
Vcc-0.2V
- 10 - 10 - 10
uA
Output Low
Voltage
V
OL
I
OL
= 2.1mA
- 0.4 - 0.4 - 0.4
V
Output High
Voltage
V
OH
I
OH
= -1 mA
2.2 - 2.2 - 2.2 - V
TE
CH
tm
T15N1M16A
TM Technology Inc. reserves the right P. 5
Publication Date: JUL . 2002
to change products or specifications without notice.
Revision: A
CAPACITANCE
(f = 1 MHz, Ta = 25
C,)
PARAMETER SYMBOL
CONDITION
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
8 pF
Input/ Output Capacitance
C
I/O
V
IN
=
V
OUT
= 0V
10 pF
Note: This parameter is guaranteed by device characterization and is not production tested.
AC TEST CONDITIONS
PARAMETER CONDITIONS
Input Pulse Levels
0.4V to 2.0V
Input Rise and Fall Times
5.0 ns
Input and Output Timing Reference Level
1.4V
Output Load
C
L
=30pF+1TTL Load
AC TEST LOADS AND WAVEFORM
DQ
Z
0
= 50 ohm
50 ohm
30 pF
Vt =1.4V
Fig.A * Including Scope and Jig Capacitance
TTL
C
L
*
Fig.B Output Load Equivalent
R
L
C
L