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Электронный компонент: T15V2M16B

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TE
CH
tm
T15V2M16B
TM Technology Inc. reserves the right P. 1
Publication Date: NOV. 2002
to change products or specifications without notice.
Revision:A
SRAM
128K X 16 LOW POWER
CMOS STATIC RAM
FEATURES
Access time : 45/55/70/100 ns
Low-power consumption
- Active: 5mA (I
CC1
)
- Stand-by: (CMOS input/output)
Max.. 15 uA for 55/70/100ns
Max.. 40 uA for 45ns
Equal access and cycle time
Single +2.7V to 3.6V Power Supply
TTL compatible , Tri-state output
Common I/O capability
Automatic power-down when deselected
Available in 44-PIN TSOP-II and 48-pin CSP
packages
Operating temperature :
- -10 ~ +70
C
- -40 ~ +85
C
PART NUMBER EXAMPLES
PART NUMBER
PACKAGE Temperature
T15V2M16B-55S
TSOP-II
-10 ~ +70
C
T15V2M16B-70C
CSP
-10 ~ +70
C
T15V2M16B-55SI
TSOP-II
-40 ~ +85
C
T15V2M16B-70CI
CSP
-40 ~ +85
C
GENERAL DESCRIPTION
The T15V2M16B is a very Low Power CMOS
Static RAM organized as 131,072 words by 16
bits . This device is fabricated by high
performance CMOS technology. It can be operated
under wide power supply voltage range from
+2.7V to +3.6V.
The T15V2M16B inputs and three-state
outputs are TTL compatible and allow for direct
interfacing with common system bus structures.
Data retention is guaranteed at a power supply
voltage as low as 2V.

BLOCK DIAGRAM
DECODER
A0
A16
I/O16
Vcc
DATA I/O
CORE
ARRAY
Vss
I/O1
WE
OE
CE
CONTROL
CIRCUIT
UB
LB
.
.
.
.
.
.
TE
CH
tm
T15V2M16B
TM Technology Inc. reserves the right P. 2
Publication Date: NOV. 2002
to change products or specifications without notice.
Revision:A
PIN CONFIGURATIONS
TSOP-II
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A16
A15
A14
A13
A12
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
LB
OE
I/O9
VCC
VSS
I/O10
I/O15
I/O16
NC
A8
A14
NC
A15
A12
A13
A9
A10
WE
A11
NC
I/O8
I/O7
A6
NC
VCC
VSS
UB
I/O3
I/O1
A0
A1
A2
CE
A4
A3
A5
A
6
5
4
3
2
1
H
G
F
E
D
C
B
I/O11
I/O12
I/O13
I/O14
NC
NC
A7
A16
I/O2
I/O4
I/O5
I/O6
48-Ball CSP TOP VIEW (Ball Down)

PIN DESCRIPTIONS
SYMBOL DESCRIPTIONS
SYMBOL DESCRIPTIONS
A0 ~ A16 Address inputs
LB
Lower byte (I/O 1~8)
I/O1~I/O16 Data inputs/outputs
UB
Upper byte (I/O 9~16)
CE
Chip enable
VCC
Power supply
WE
Write enable input
V
SS
Ground
OE
Output enable input
NC
No connection
TE
CH
tm
T15V2M16B
TM Technology Inc. reserves the right P. 3
Publication Date: NOV. 2002
to change products or specifications without notice.
Revision:A
ABSOLUTE MAXIMUM RATINGS*
PARAMETER SYM
MIN.
MAX.
UNIT
Voltage on Any Pin Relative to VSS
V
R
-0.2 +4.6
V
V
Power Dissipation
P
D
- 1.0 W
Storage Temperature
T
STG
-55 +150
C
Temperature Under Bias
I
BIAS
-10 / -40
+70 / +85
C

*Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to
the device. This is a stress rating only and function operation of the device at these or any other
conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.


TRUTH TABLE
CE
OE
WE
LB
UB
I/O 1~8
I/O 9~16
MODE
Power
H X* X* X* X* High-Z
High-Z
Deselected
Standby
X* X* X* H H High-Z
High-Z
Deselected
Standby
L H H L X* High-Z High-Z Output
Disabled
Active
L H H X* L High-Z High-Z Output
Disabled
Active
L L H L H Data
Out High-Z Lower
Byte
Read
Active
L
L
H
H
L
High-Z
Data Out
Upper Byte Read
Active
L L H L L Data
Out Data
Out
Word
Read
Active
L
X*
L
L
H
Data In
High-Z
Lower Byte Write
Active
L
X*
L
H
L
High-Z
Data In
Upper Byte Write
Active
L
X*
L
L
L
Data In
Data In
Word Write
Active
*Note: X = Don't Care (Must be low or high state), L = Low, H = High
TE
CH
tm
T15V2M16B
TM Technology Inc. reserves the right P. 4
Publication Date: NOV. 2002
to change products or specifications without notice.
Revision:A
RECOMMENDED OPERATING CONDITIONS
-
(Ta =
-10 ~ +70
C /
-40
C ~ 85
C)
PARAMETER SYM
MIN
TYP
MAX
UNIT
Vcc 2.7 3.0 3.6
V
Supply Voltage
V
SS
0.0 0.0 0.0
V
V
IH
0.7Vcc - Vcc+0.3 V
Input Voltage
V
IL
-0.2 - 0.6 V
OPERATING CHARACTERISTICS
-
(Vcc = 2.7 to 3.6V,
V
SS
= 0V, Ta =
-10 ~ +70
C /
-40
C ~ 85
C)
-45 -55 -70 -100
UNIT
PARAMETER SYM. TEST
CONDITIONS
Min Max Min Max Min Max Min Max
Input Leakage
Current
I
LI
Vcc = Max,
V
IN
= V
SS
to Vcc
- 1 - 1 - 1 - 1 uA
Output Leakage
Current
I
LO
CE
= V
IH
or OE = V
IH
or WE = V
IL
V
IO
= V
SS
to Vcc
- 1 - 1 - 1 - 1 uA
Operating Power
Supply Current
I
CC
CE
= V
IL
,
WE
=V
IH,
OE
= V
IH
,
V
IN
= V
IH
or V
IL,
I
OUT
=0mA
- 3 - 3 - 3 - 3 mA
I
CC1
Cycle time=1us,
100% duty, I
IO
=0mA,
CE
0.2V,
V
IN
V
CC
-0.2V
or V
IN
0.2V
- 5 - 5 - 5 - 5 mA
Average Operating
Current
I
CC2
Cycle time=min,
100% duty, I
IO
=0mA,
CE
= V
IL,
V
IN
= V
IH
or V
IL
- 45 - 40 - 35 - 25 mA
Standby Power
Supply Current
(TTL Level)
I
SB
CE
=
V
IH
or
LB
=
UB
=
V
IH
other input= V
IL
or
V
IH
- 0.3 - 0.3 - 0.3 - 0.3 mA
Standby Power
Supply Current
(CMOS Level)
I
SB1
CE
Vcc-0.2V or
LB
=
UB
Vcc-0.2V,
V
IN
0.2V or
V
IN
Vcc-0.2V
- 40 - 15 - 15 - 15 uA
Output Low Voltage
V
OL
I
OL
= 2.1mA
- 0.4 - 0.4 - 0.4 - 0.4 V
Output High Voltage
V
OH
I
OH
= -1.0 mA
2.2 - 2.2 - 2.2 - 2.2 - V
TE
CH
tm
T15V2M16B
TM Technology Inc. reserves the right P. 5
Publication Date: NOV. 2002
to change products or specifications without notice.
Revision:A
CAPACITANCE
(f = 1 MHz, Ta = 25
C,)
PARAMETER SYMBOL
CONDITION
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
8
pF
Input/ Output Capacitance
C
I/O
V
IN
=
V
OUT
= 0V
10 pF
Note: This parameter is guaranteed by device characterization and is not production tested.
AC TEST CONDITIONS
PARAMETER CONDITIONS
Input Pulse Levels
0.6V to 0.7Vcc
Input Rise and Fall Times
3.0 ns
Input and Output Timing Reference Level
1.4V
C
L
=30pF+1TTL Load(45/55/70ns)
Output Load
C
L
=100pF+1TTL Load(Load for 100ns)
AC TEST LOADS AND WAVEFORM
DQ
Z
0
= 50 ohm
50 ohm
30 pF
Vt =1.4V
Fig.A * Including Scope and Jig Capacitance
TTL
C
L
*
Fig.B Output Load Equivalent
R
L
C
L