TE
CH
tm
T224162B
Taiwan Memory Technology, Inc. reserves the right
P. 1
Publication Date: AUG. 2000
to change products or specifications without notice.
Revision:L
DRAM
256K x 16 DYNAMIC
RAM
EDO PAGE MODE
FEATURES
Industry-standard x 16 pinouts and timing
functions.
Single 5V (
10%) power supply.
All device pins are TTL- compatible.
512-cycle refresh in 8ms.
Refresh modes: RAS only, CAS BEFORE
RAS
(CBR) and HIDDEN.
Extended data-out (EDO) PAGE MODE
access cycle.
BYTE WRITE and BYTE READ access
cycles.
OPTION
TIMING
EDO
MARKING
22ns
125 MHz
-22
25ns
100 MHz
-25
28ns
100 MHz
-28
35ns
83 MHz
-35
45ns
60 MHz
-45
50ns 50 MHz -50
PACKAGE
MARKING
SOJ J
TSOP(II) S
GENERAL DESCRIPTION
The T224162B is a randomly accessed solid state
memory containing 4,194,304 bits organized in a x16
configuration. The T224162B has both BYTE
WRITE and WORD WRITE access cycles via two
CAS pins. It offers Fast Page mode with Extended
Data Output.
The T224162B
CAS
function and timing are
determined by the first CAS to transition low and
by the last to transition back high. Use only one of
the two CAS and leave the other staying high during
WRITE will result in a BYTE WRITE.
CASL
transiting low in a WRITE cycle will write data into
the lower byte (IO1~IO8), and CASH transiting low
will write data into the upper byte (IO9~16).
PIN ASSIGNMENT ( Top View )
I/01
Vcc
I/02
I/03
I/04
I/05
Vcc
I/06
I/07
I/08
NC
NC
NC
A0
A1
Vcc
A2
A3
WE
RAS
40
39
38
37
35
36
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
6
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/016
Vss
I/015
I/014
I/013
I/012
Vss
I/011
I/010
I/09
NC
A8
A7
A6
VSS
A5
A4
CASL
CASH
OE
SOJ
I/01
Vcc
I/02
I/03
I/04
I/05
Vcc
I/06
I/07
I/08
NC
NC
NC
A0
A1
Vcc
A2
A3
WE
RAS
40
39
38
37
35
36
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
6
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/016
Vss
I/015
I/014
I/013
I/012
Vss
I/011
I/010
I/09
NC
A8
A7
A6
VSS
A5
A4
CASL
CASH
OE
TSOP(II)
TE
CH
tm
T224162B
Taiwan Memory Technology, Inc. reserves the right
P. 2
Publication Date:AUG. 2000
to change products or specifications without notice.
Revision:L
FUNCTIONAL BLOCK DIAGRAM
NO.2 CLOCK
GENERATOR
COLUMN.
ADDRESS
BUFFER
REFRESH
CONTROLLER
REFRESH
COUNTER
ROW.
ADDRESS
BUFFERS(9)
NO.1 CLOCK
GENERATOR
CONTROL
LOGIC
DATA-IN BUFFER
DATA-OUT
BUFFER
COLUMN
DECODER
ROW
DECODER
512 x 512 x 16
MEMORY
ARRAY
SENSE AMPLIFIERS
VO GATING
16
512 x 16
512
A0
A1
A2
A3
A4
A5
A6
A7
A8
512
RAS
CAS
DQ01
.
.
DQ16
OE
16
8
8
9
9
9
9
9
CASH
CASL
WE
Vcc
Vss
PIN DESCRIPTIONS
PIN NO.
SYM.
TYPE
DESCRIPTION
16~19,22~26
A0-A8
Input
Address Input
14
RAS
Input
Row Address Strobe
28
CASH
Input
Column Address Strobe /Upper Byte Control
29
CASL
Input
Column Address Strobe /Lower Byte Control
13
WE
Input
Write Enable
27
OE
Input
Output Enable
2~5,6~10,31~34,36~39
I/O1 - I/O16 Input/ Output Data Input/ Output
1,6,20
Vcc
Supply
Power, 5V
21,35,40
Vss
Ground
Ground
11,12,15,30
NC
-
No Connect
TE
CH
tm
T224162B
Taiwan Memory Technology, Inc. reserves the right
P. 3
Publication Date: AUG. 2000
to change products or specifications without notice.
Revision:L
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any pin Relative to VSS..... -1V to +7V
Operating Temperature, Ta (ambient) ..0
C to +70
C
Storage Temperature (plastic)........ -55
C to +150
C
Power Dissipation ..........................................
1.0W
Short Circuit Output Current......................... 50mA
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other
conditions above those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS
(0
C
Ta
70
C; VCC = 5V
10 % unless otherwise noted)
DESCRIPTION
CONDITIONS
SYM.
MIN
MAX
UNITS NOTES
Supply Voltage
Vcc
4.5
5.5
V
1
Supply Voltage
Vss
0
0
V
Input High (Logic) voltage
VIH
2.4
Vcc+1
V
1
Input Low (Logic) voltage
VIL
-1.0
0.8
V
1
Input Leakage Current
0V
VIN
7V
ILI
-10
10
uA
Output Leakage Current
0V
VOUT
7V
Output(s) disabled
ILO
-10
10
uA
Output High Voltage
IOH = -5 mA
VOH
2.4
Vcc
V
Output Low Voltage
IOL = 4.2 mA
VOL
0
0.4
V
Note: 1.All Voltages referenced to Vss
MAX
DESCRIPTION
CONDITIONS
SYM. -22 -25 -28 -35 -45 -50 UNITS NOTES
Operating Current
RAS ,CAS cycling , tRC = min Icc1 190 180 170 150 130 110 mA 1,2
TTL interface,
RAS
,
CAS =VIH, DOUT=High-Z
4 4 4 4 4 4 mA
Standby Current
CMOS interface,
RAS
,
CAS
>
Vcc-0.2V
Icc2
2 2 2 2 2 2 mA
RAS -only refresh
Current
tRC = min
Icc3 190 180 170 150 130 110 mA
2
Standby Current
RAS =VIH, CAS=VIL
Icc5 5 5 5 5 5 5 mA
1
CAS
Before
RAS
Refresh Current
tRC = min
Icc6 190 180 170 150 130 110 mA
EDO Page Mode Current tPC = min
Icc7 190 180 170 150 130 110 mA 1,3
Note: 1. Icc depends on output load condition when the device is selected.
Icc max is specified at the output open condition.
2. Address can be changed twice or less while RAS = VIL.
3. Address can be changed once or less while
CAS
= VIH.
TE
CH
tm
T224162B
Taiwan Memory Technology, Inc. reserves the right
P. 4
Publication Date:AUG. 2000
to change products or specifications without notice.
Revision:L
CAPACITANCE
(Ta =25
C, Vcc =5V
10 %)
Parameter
Symbol
Typ
Max
Unit
Notes
Input Capacitance (address)
CI1
-
5
pF
1
Input Capacitance (clocks)
CI2
-
7
pF
1
Output Capacitance (data-in, data-out)
CI/O
-
10
pF
1
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
AC ELECTRICAL CHARACTERISTICS
(note 14)
(Ta =0 to 70
C, Vcc=5V
10 %, Vss=0V)
Input timing reference levels: 0.8V, 2.4V
Test Conditions (note 29)
Output Load: 2TTL gate + CL (50pF)
-22
-25
-28
-35
-45
-50
AC CHARACTERISTICS
PARAMETER
SYM
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
UNIT
Notes
Read or Write Cycle Time
tRC
42
45
48
65
85
100
ns
Read Write Cycle Time
tRWC 62
65
70
95
115
135
ns
EDO-Page-Mode Read or
Write Cycle Time
tPC
8
10
10
12
16
20
ns 22
EDO-Page-Mode Read-
Write Cycle Time
tPCM 30
32
34
40
46
57
ns 22
Access Time From RAS
tRAC
22
25
28
35
45
50 ns 4
Access Time From
CAS
tCAC
7
7
7
9
11
13 ns 5,20
Access Time From OE
tOAC
8
8
8
9
11
13 ns 13,20
Access Time From Column
Address
tAA
11
12
13
15
19
23 ns
Access Time From CAS
Precharge
tACP
13
14
15
18
22
26 ns 20
RAS
Pulse Width
tRAS 22 10K 25 10K 28 10K 35 10K 45 10K 50 10K
ns
RAS Pulse Width
(EDO Page Mode)
tRASC 22 100K 25 100K 28 100K 35 100K 45 100K 50 100K
ns
RAS Hold Time
tRSH 7
7
7
9
11
13
ns 27
RAS Precharge Time
tRP
15
15
17
25
35
37
ns
CAS Pulse Width
tCAS 4 10K 4 10K 4 10K 4 10K 6 10K 8 10K
ns 26
CAS Hold Time
tCSH 19
20
22
30
40
50
ns 19
CAS Precharge Time
(EDO Page Mode)
tCP
3
3
3
3
5
6
ns 23
RAS
to
CAS
Delay Time
tRCD 9 15 10 17 10 19 10 26 10 34 19 37
ns 7,18
CAS to RAS Precharge
Time
tCRP 3
3
3
3
5
5
ns 19
TE
CH
tm
T224162B
Taiwan Memory Technology, Inc. reserves the right P. 5
Publication Date:AUG. 2000
to change products or specifications without notice.
Revision:L
AC ELECTRICAL CHARACTERISTICS
(
continued
)
-22
-25
-28
-35
-45
- 50
AC CHARACTERISTICS
PARAMETER
SYM
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
UNIT
Notes
Row Address Setup Time
tASR 0
0
0
0
0
0
ns
Row Address Hold Time
tRAH 5
5
5
5
5
5
ns
RAS
to Column Address
Delay Time
tRAD 8 11 8 12 8 13 8 20 8 26 10 29 ns
8
Column Address Setup Time
tASC 0
0
0
0
0
0
ns
18
Column Address Hold Time
tCAH 4
4
4
4
6
7
ns
18
Column Address Hold Time
(Reference to RAS )
tAR
17
19
21
30
40
45
ns
Column Address to RAS
Lead Time
tRAL 11
12
13
15
19
23
ns
Read Command Setup Time
tRCS
0
0
0
0
0
0
ns
15,18
Read Command Hold Time
Reference to CAS
tRCH 0
0
0
0
0
0
ns
9,15,
19
Read Command Hold Time
Reference to RAS
tRRH 0
0
0
0
0
0
ns
9
CAS
to Output in Low-Z
tCLZ
3
3
3
3
3
3
ns
20
Output Buffer Turn-off
Delay From CAS or RAS
tOFF1 3
3
3
3
15
3
15
3
15
ns
10,17,
20
Output Buffer Turn-off to
OE
tOFF2
8
8
8
8
8
8
ns
17,28
Write Command Setup Time
tWCS 0
0
0
0
0
0
ns
11,15,
18
Write Command Hold Time
tWCH 4
4
4
4
6
7
ns
15,27
Write Command Hold Time
(Reference to RAS )
tWCR 19
19
21
30
46
51
ns
15
Write Command Pulse
Width
tWP
4
4
4
4
6
8
ns
15
Write Command to RAS
Lead Time
tRWL 6
6
6
7
9
10
ns
15
Write Command to CAS
Lead Time
tCWL 5
5
5
7
9
11
ns
15,19
Data-in Setup Time
tDS
0
0
0
0
0
0
ns
12,20
Data-in Hold Time
tDH
4
4
4
4
6
7
ns
12,20
Data-in Hold Time
(Reference to
RAS
)
tDHR 19
19
21
30
40
45
ns
RAS to WE Delay Time
tRWD 31
34
37
51
61
70
ns
11
AC ELECTRICAL CHARACTERISTICS
(
continued
)
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