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Электронный компонент: T35L3232B

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TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
P. 1
Publication Date: FEB. 2000
to change products or specifications without notice.
Revision:0.A
SYNCHRONOUS
BURST SRAM
32K x 32 SRAM
Pipeline and Flow-Through Burst Mode
FEATURES
E FT pin for user configurable pipeline or
flow-through operation.
E Fast Access times:
- Pipeline 3.8 / 4 / 4.5 ns
- Flow-through 9 / 10 / 11ns
ESingle 3.3V +0.3V/-0.165V power supply
ECommon data inputs and data outputs
EIndividual BYTE WRITE ENABLE and
GLOBAL WRITE control
E Three chip enables for depth expansion and
address pipelining
E Clock-controlled and registered address, data
I/Os and control signals
EInternally self-timed WRITE CYCLE
EBurst control pins ( interleaved or linear burst
sequence)
EHigh 30pF output drive capability at rated
access time
ESNOOZE MODE for reduced power standby
E Burst Sequence :
- Interleaved (MODE=NC or VCC)
- Linear (MODE=GND)
OPTIONS
MARKING
-3.8
-4
-4.5
Access
time
3.8ns
4ns
4.5ns
Pipeline
3-1-1-1
Cycle
time
6.6ns
7.5ns
8.5ns
Access
time
9ns
10ns
11ns
Flow-
through
2-1-1-1
Cycle
time
10.5ns
15ns
15ns
Package
100-pin QFP
Q
100-pin TQFP
T
Part Number Examples
PART NO.
Pkg.
T35L3232B-3.8Q
Q
T35L3232B-4T
T
GENERAL DESCRIPTION
The Taiwan Memory Technology Synchronous
Burst RAM family employs high-speed, low power
CMOS design using advanced triple-layer polysilicon,
double-layer metal technology. Each memory cell
consists of four transistors and two high valued resistors.
The T35L3232B SRAM integrates 32,768 x 32
bits SRAM cells with advanced synchronous peripheral
circuitry and a 2-bit counter for internal burst operation.
All synchronous inputs are gated by registers controlled
by a positive-edge-triggered clock input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining
chip enable (
CE
), depth-
expansion chip enables (
CE2
and CE2), burst control
inputs (
ADSC
,
ADSP
, and
ADV
), write enables
(
BW1
,
BW2
,
BW3
,
BW4
, and
BWE
), and
global write (
GW
).
Asynchronous inputs include the output enable
(
OE
), Snooze enable (ZZ) and burst mode control
(MODE). The data outputs (Q), enabled by
OE
, are
also asynchronous.
Addresses and chip enables are registered with
either address status processor (
ADSP
) or address
status controller (
ADSC
) input pins. Subsequent burst
addresses can be internally generated as controlled by
the burst advance pin (
ADV
).
Address and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles
can be one to four bytes wide as controlled by the write
control inputs. Individual byte write
allows individual byte to be written.
BW1
controls
DQ1-DQ8.
BW2
controls DQ9-DQ16.
BW3
controls DQ17-DQ 24.
BW4
controls DQ25-DQ32.
BW1
,
BW2
,
BW3
, and
BW4
can be active only
with
BWE
being LOW.
GW
being LOW causes
all bytes to be written.
WRITE pass-through
capability allows written data available at the output for
the immediately next READ cycle. This device also
incorporates pipelined enable circuit for easy depth
expansion without penalizing system performance.
TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
P. 2
Publication Date: FEB. 2000
to change products or specifications without notice.
Revision:0.A
FUNCTIONAL BLOCK DIAGRAM
Note:
The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin
descriptions and timing diagrams for detailed information.
BYTE 4
WRITE REGISTER
ENABLE
REGISTER
BYTE 1
WRITE REGISTER
BYTE 3
WRITE REGISTER
BYTE 2
WRITE REGISTER
ADDRESS
REGISTER
BINARY
COUNTER
& LOGIC
CLR
Q 0
15
15
13
15
A 0
A 1
A1'
A0'
32K x 8 x 4
MEMORY
ARRAY
SENSE
AMPS
INPUT
REGISTERS
8
8
8
8
8
8
8
8
32
32
32
DQ1
E
E
E
DQ32
4
A0-A14
MODE
ADV
CLK
ADSC
ADSP
B W 4
B W 3
B W 2
B W 1
C E
CE2
CE2
O E
G W
B W E
Q 1
OUTPUT
BUFFERS
BYTE 1
WRITE DRIVER
BYTE 2
WRITE DRIVER
BYTE 3
WRITE DRIVER
BYTE 4
WRITE DRIVER
FT
TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
P. 3
Publication Date: FEB. 2000
to change products or specifications without notice.
Revision:0.A
PIN ASSIGNMENT (Top View)
N C
DQ17
DQ18
V C C Q
V S S Q
DQ19
DQ20
DQ21
DQ22
V S S Q
V C C Q
DQ23
DQ24
F T
V C C
N C
V S S
DQ25
DQ26
V C C Q
V S S Q
DQ27
DQ28
DQ29
DQ30
V S S Q
V C C Q
DQ31
DQ32
N C
N C
D Q 1
D Q 2
V C C Q
V S S Q
D Q 3
D Q 4
D Q 5
D Q 6
V S S Q
V C C Q
D Q 7
D Q 8
Z Z
V C C
N C
V S S
D Q 9
DQ10
V C C Q
V S S Q
DQ11
DQ12
DQ13
DQ14
V S S Q
V C C Q
DQ15
DQ16
N C
1
1 1
1 0
9
8
7
6
5
4
3
2
1 8
1 7
1 6
1 5
1 4
1 3
1 2
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
3 0
2 9
3 1
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
5 0
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
7 0
6 9
6 8
6 7
6 6
6 5
6 4
6 3
6 2
6 1
8 0
7 9
7 8
7 7
7 6
7 5
7 4
7 3
7 2
7 1
9 5
9 6
8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1
9 0
9 1
9 2
9 3
9 4
8 9
100 9 9 9 8 9 7
A7
A6
BWE
GW
CLK
VSS
VCC
CE2
BW1
BW2
BW3
BW4
CE2
CE
ADV
ADSP
ADSC
OE
A9
A8
NC
VCC
NC
NC
A10
A0
NC
VSS
A11
A12
A13
A14
NC
NC
A1
A2
A3
MODE
A4
A5
100-pin QFP
or
100-pin TQFP
TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
P. 12
Publication Date: FEB. 2000
to change products or specifications without notice.
Revision:0.A
PIPELINE READ TIMING
High-Z
BURST READ
C LK
ADSC
AD SP
AD D RE S S
G W , B W E ,
B W 1 - B W 4
t KC
t KH t KL
t ADSS t ADSH
DON'T CARE
UNDEFINED
t ADSS t ADSH
t AS t AH
t WS t WH
t CES t CEH
t AAS t AAH
t OEQ
t KQX
tOELZ
tOEHZ
t KQ
t KQHZ
t KQ
t KQLZ
Sing le READ
(NOTE3)
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2+1)
Burst wraps around
to its inital state.
ADV suspends burst.
Burst continued with
new base address.
Q(A2)
A3
A2
A1
(NOTE1)
Deselect cycle.
CE
( N O T E 2 )
ADV
O E
Q
Q(A3)
t KQX
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2.
CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW
and CE2 is HIGH. When
CE is HIGH, CE2 is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence.
OE
does not cause Q to be driven until after the following clock rising edge.
TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
P. 13
Publication Date: FEB. 2000
to change products or specifications without notice.
Revision:0.A
FLOW-THROUGH READ TIMING
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2. CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW
and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE
does not cause Q to be driven until after the following clock rising edge.
4. Output are disabled tKQHZ after diselect.
High-Z
BUR ST R EAD
CLK
AD S C
A D S P
AD D RE S S
G W , B W E ,
B W 1 - B W 4
t K C
t K H t KL
t AD S S t AD S H
DON'T CARE
UNDEFINED
t AD S S t AD S H
t AS t AH
t W S t W H
t CE S t CE H
t A AS t A AH
t OEQ
t K QX
tOELZ
tOEHZ
t KQ
t KQHZ
t KQ
t KQLZ
Single R E AD
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2+1)
Burst wra ps aro und to
i ts inita l s ta te .
AD V s us pe nds burs t.
Q(A2)
A2
A 1
(NOTE1)
CE
( N O T E 2 )
A D V
O E
Q
Des elec t Cy cle
(NO TE 4)
Q(A2+2)
TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
P. 14
Publication Date: FEB. 2000
to change products or specifications without notice.
Revision:0.A
WRITE TIMING
BURST WRITE
C LK
ADS C
High-Z
AD S P
AD D RE S S
B W E ,
B W 1 - B W 4
t KC
t KH t KL
t ADSS t ADSH
DON'T CARE
UNDEFINED
t AS t AH
t WS t WH
t CES t CEH
t AAS t AAH
tOEHZ
t DS t DH
Single WRITE
(NOTE3)
D(A1)
D(A2)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3+1)
D(A3)
A3
A2
A1
(NOTE1)
CE
( N O T E 2 )
ADV
O E
D
ADSC extends burst.
t ADSS t ADSH
t ADSS t ADSH
G W
t WS t WH
D(A2+1)
D(A3+2)
BURST READ
Extended BURST WRITE
Q
ADV suspnds burst.
(NOTE4)
(NOTE5)
BYT E WRIT E signals are
ignored for first cycle when
ADSP initialtes burst.
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2. CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW , CE2 is
LOW and CE2 is HIGH. When CE is HIGH , CE2 is HIGH and CE2 is LOW.
3. OE must be HIGH before the input data setup and hold HIGH throughout the data hold time.
This prevents input/output data contention for the time period to the byte write enable inputs being
sampled.
4.
ADV
must be HIGH to permit a WRITE to the loaded address.
5. Full width WRITE can be initiated by GW LOW or GW HIGH and BWE , BW1- BW4
LOW.
TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
P. 15
Publication Date: FEB. 2000
to change products or specifications without notice.
Revision:0.A
PIPELINE READ/WRITE TIMING
A4
High-Z
BURST READ
C LK
ADS C
AD S P
A D D RE S S
B W E
B W 1 - B W 4
t KC
t KH t KL
t ADSS t ADSH
DON'T CARE
UNDEFINED
t AS t AH
t WS t WH
t CES t CEH
t DH
t KQ
tOELZ
tOEHZ
t DS
t KQ
t KQLZ
Single WRITE
Q(A1)
Q(A2)
Q(A3)
Q(A4)
Q(A4+1)
Q(A4+3)
Q(A4+2)
A5
A3
A1
(NOTE1)
CE
( N O T E 2 )
ADV
O E
D
A2
A6
Q
High-Z
D(A3)
D(A5)
D(A6)
Back-to-Back READs
Pass-through
READ
Back-to-Back
WRITEs
Note: 1. Q(A4) refers to output from address A4. Q (A4 + 1) refers to output from the next internal burst
address following A4.
2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is
LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an
ADSP, ADSC or ADV
cycle is performed.
4. GW is HIGH.
5. Back-to-back READs may be controlled by either ADSP or ADSC.
TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
P. 16
Publication Date: FEB. 2000
to change products or specifications without notice.
Revision:0.A
FLOW-THROUGH READ/WRITE TIMING
Note: 1. Q(A4) refers to output from address A4. Q (A4 + 1) refers to output from the next internal burst
address following A4.
2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is
LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an
ADSP, ADSC or ADV
cycle is performed.
4. GW is HIGH.
5. Back-to-back READs may be controlled by either ADSP or ADSC.
A 4
BUR ST R EAD
CLK
AD S C
A D S P
AD D RE S S
B W E
B W 1 - B W 4
( N O T E 4 )
t K C
t K H t KL
t AD S S t AD S H
DON'T CARE
UNDEFINED
t AS t AH
t W S t W H
t CE S t CE H
t D H
t KQ
tOELZ
tOEHZ
t D S
Si ngle W R ITE
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+3)
Q (A4+2)
A 5
A 3
A 1
(NOTE1)
CE
( N O T E 2 )
A D V
O E
D
A 2
A 6
Q
High-Z
D(A3)
D(A5)
D(A6)
Ba ck-t o -B ac k R EADs
Back-to -Ba ck
W RITEs
TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
P.17
Publication Date: FEB. 2000
to change products or specifications without notice.
Revision:0.A
PACKAGE DIMENSIONS
100-LEAD QFP SSRAM (14 x 20 mm)
SYMBOL
DIMENSIONS IN INCHES
DIMENTION IN MM
A
0.130(MAX)
3.302(MAX)
A1
0.1120.005
2.8450.127
A2
0.004(MIN)
0.102(MIN)
b
0.012+0.004-0.002
0.300+0.102-0.051
D
0.5510.005
14.0000.127
E
0.7870.005
20.0000.127
e
0.0260.006
0.6500.152
HD'
0.6770.008
17.2000.203
HE'
0.9130.008
23.2000.203
L'
0.0320.008
0.8000.203
L1'
0.0630.008
1.6000.203
t
0.006+0.004-0.002
0.150+0.102-0.051
y
0.004(MAX)
0.102(MAX)
c
0C~12C
0C~12C
TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
P.18
Publication Date: FEB. 2000
to change products or specifications without notice.
Revision:0.A
PACKAGE DIMENSIONS
100-LEAD TQFP SSRAM (14 x 20 mm)
SYMBOL
DIMENSIONS IN INCHES
DIMENTION IN MM
A
0.063(MAX)
1.600(MAX)
A1
0.0550.005
1.4000.050
A2
0.002(MIN)
0.050(MIN)
b
0.013+0.002-0.004
0.320+0.060-0.100
D
0.5510.004
14.0000.100
E
0.7870.004
20.0000.100
e
0.0260.006
0.6500.152
HD'
0.6300.004
16.0000.100
HE'
0.8660.004
22.0000.100
L'
0.0240.006
0.6000.150
L1'
0.0390.006
1.0000.150
t
0.0060.002
0.150+0.050-0.060
y
0.003(MAX)
0.080(MAX)
c
0C~7C
0C~7C
TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
P. 4
Publication Date: FEB. 2000
to change products or specifications without notice.
Revision:0.A
PIN DESCRIPTIONS
PINS
SYM.
TYPE
DESCRIPTION
32-37, 44-48,
81, 82, 99,
100,
A0-A14
Input-
Synchronous
Addresses: These inputs are registered and must meet the setup and
hold times around the rising edge of CLK. The burst counter
generates internal addresses associated with A0 and A1, during
burst cycle and wait cycle.
93-96
BW1
BW2
BW3
BW4
Input-
Synchronous
Byte Writes: A byte write is LOW for a WRITE cyle and HIGH for
a READ cycle. BW1 controls DQ1-DQ8. BW2 controls DQ9-
DQ16.
BW3 controls DQ17-DQ24. BW4 controls DQ25-DQ32.
Data I/O are high impedance if either of these inputs are LOW ,
conditioned by
BWE
being LOW.
87
BWE
Input-
Synchronous
Write Enable: This active LOW input gates byte write operations
and must meet the setup and hold times around the rising edge of
CLK.
88
GW
Input-
Synchronous
Global Write: This active LOW input allows a full 32-bit WRITE to
occur independent of the
BWE and BWn lines and must meet
the setup and hold times around the rising edge of CLK.
89
CLK
Input-
Synchronous
Clock: This signal registers the addresses, data, chip enables,
writecontrol and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around the
clock's rising edge.
98
CE
Input-
Synchronous
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions internal use of
ADSP
. This input is
sampled only when a new external address is loaded.
92
CE2
Input-
Synchronous
Synchronous Chip Enable: This active LOW input is used to enable
the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.
97
CE2
Input-
Synchronous
Synchronous Chip Enable: This active HIGH input is used to enable
the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.
86
OE
Input
Output enable: This active LOW asynchronous input enables the
data output drivers.
83
ADV
Input-
Synchronous
Address Advance: This active LOW input is used to control the
internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
84
ADSP
Input-
Synchronous
Address Status Processor: This active LOW input, along with
CE
being LOW, causes a new external address to be registered and a
READ cycle is initiated using the new address.
TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
P. 5
Publication Date: FEB. 2000
to change products or specifications without notice.
Revision:0.A
PIN DESCRIPTIONS
(continued)
QFP PINS
SYM.
TYPE
DESCRIPTION
85
ADSC
Input-
Synchronous
Address Status Controller:This active LOW input causes
device to be deselected or selected along with new external
address to be registered. A READ or WRITE cycle is
initiated depending upon write control inputs.
14
FT
Input-
Static
A LOW on this pin selects in flow-through mode. A NC or
HIGH on this pin selects in pipeline mode.
31
MODE
Input-
Static
Mode: This input selects the burst sequence. A LOW on this
pin selects LINEAR BURST. A NC or HIGH on this pin
selects INTERLEAVED BURST. Do not alter input state
while device is operating.
64
ZZ
Input
Snooze Enable: This active HIGH asynchronous input causes
the device to enter a low-power standby mode in which all
data in the memory arry is retained.
2, 3, 6-9, 12, 13,
18, 19, 22-25,
28, 29, 52, 53,
56-59, 62, 63,
68, 69, 72-75,
78, 79,
DQ1-
DQ32
Input/
Output
Data Inputs/Outputs: First Byte is DQ1-DQ8. Second Byte is
DQ9-DQ16. Third Byte is DQ17-DQ24. Fourth Byte is DQ25-
DQ32. Input data must meet setup and hold times around the
rising edge of CLK.
15,41,65,91
VCC
Supply
Power Supply: 3.3V +10%/-5%
17,40,67,90
VSS
Ground
Ground: GND
4,11,20,27,54,
61,70,77
VCCQ
I/O Supply
Output Buffer Supply: 3.3V +10%/-5%
5,10,21,26,55,
60,71,76
VSSQ
I/O Ground Output Buffer Ground: GND
1,16,30,38,
39,42,43,49,
50, 51, 66,80
NC
-
No Connect: These signals are not internally conntected.
TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
P. 6
Publication Date: FEB. 2000
to change products or specifications without notice.
Revision:0.A
INTERLEAVED BURST ADDRESS TABLE (MODE = NC/VCC)
First Address
(external)
Second Address
(internal)
Third Address
(internal)
Fourth Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
LINEAR BURST ADDRESS TABLE (MODE = GND)
First Address
(external)
Second Address
(internal)
Third Address
(internal)
Fourth Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
PARTIAL TRUTH TABLE FOR READ/WRITE
Function
GW
BWE
BW1
BW2
BW3
BW4
READ
H
H
X
X
X
X
READ
H
L
H
H
H
H
WRITE one byte
H
L
L
H
H
H
WRITE all byte
H
L
L
L
L
L
WRITE all byte
L
X
X
X
X
X
TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
P.7
Publication Date: FEB. 2000
to change products or specifications without notice.
Revision:0.A
TRUTH TABLE
OPERATION
ADDRESS
USED
CE CE2 CE2 ZZ ADSP ADSC ADV WRITE OE CLK DQ
Deselected Cycle, Power Down
None
H
X
X
L
X
L
X
X
X
L-H High-Z
Deselected Cycle, Power Down
None
L
X
L
L
L
X
X
X
X
L-H High-Z
Deselected Cycle, Power Down
None
L
H
X
L
L
X
X
X
X
L-H High-Z
Deselected Cycle, Power Down
None
L
X
L
L
H
L
X
X
X
L-H High-Z
Deselected Cycle, Power Down
None
L
H
X
L
H
L
X
X
X
L-H High-Z
Snooze Cycle, Power Down
None
X
X
X
H
X
X
X
X
X
X
High-Z
READ Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
H
L-H High-Z
WRITE Cycle, Begin Burst
External
L
L
H
L
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
H
L-H High-Z
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H High-Z
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H High-Z
WRITE Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
WRITE Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H High-Z
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H High-Z
WRITE Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Note: 1. X means "don't care." H means logic HIGH. L means logic LOW.
WRITE = L means any one
or more byte write enable signals
(
BW1
,
BW2
,
BW3
or
BW4
)
and
BWE
are LOW, or
GW
equals LOW. WRITE = H means all byte write signal are HIGH.
2.
BW1
= enables write to DQ1-DQ8.
BW2
= enables write to DQ9-DQ16.
BW3
= enables write
to DQ17-DQ24.
BW4
=enables write to DQ25-DQ32.
3. All inputs except
OE
and ZZ must meet setup and hold times around the rising edge ( LOW
to HIGH) of CLK.
4. Suspending burst generates wait cycle.
5. For a write operation following a read operation.
OE
must be HIGH before the input data
required setup time plus High-Z time for
OE
and staying HIGH throughout the input data
hold time.
6. This device contains circuitry that will ensure the outputs will be High-Z during power-up.
7.
ADSP
= LOW along with chip being selected always initiates an internal READ cycle at the L-H
edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H
edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
P.8
Publication Date: FEB. 2000
to change products or specifications without notice.
Revision:0.A
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS.
............-0.5V to +4.6V
I/O Supply Voltage VccQ ........... Vss -0.5V to Vcc
VIN......................................... -0.5V to Vcc +0.5V
Storage Temperature (plastic)...... -55
C to +150
C
Junction Temperature ............................... +150
C
Power Dissipation ........................................ 1.0W
Short Circuit Output Current...................... 100mA
*Stresses greater than those listed under
"Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress
rating only and functional operation of the device
at these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods
may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS
(0
C
Ta
70
C; VCC = 3.3V +10%/-5% unless otherwise noted)
DESCRIPTION
CONDITIONS
SYM.
MIN
MAX
UNITS
NOTES
Input High (Logic)
voltage
VIH
2
VCCQ + 0.3
V
1, 2
Input Low (Logic)
voltage
VIL
-0.3
0.8
V
1, 2
Input Leakage Current
0V
VIN
VCC
ILI
-2
2
A
14
Output Leakage Current Output(s) disabled, 0V
VOUT
VCC
ILO
-2
2
A
Output High Voltage
IOH = -4.0 mA
VOH
2.4
V
1, 11
Output Low Voltage
IOL = 8.0 mA
VOL
0.4
V
1, 11
Supply Voltage
Vcc
3.1
3.6
V
1
MAX.
DESCRIPTION
CONDITIONS
SYM. TYP
-3.8
-4
-4.5 UNITS NOTES
Power Supply
Current : Operating
Device selected; all inputs
VIL or
VIH; cycle time
tKC MIN; VCC
= MAX; outputs open
ICC TBD 250
200
150
mA
3, 12, 13
Power Supply
Current: Idle
Device selected;
ADSC
,
ADSP
,
ADV
,
GW
,
BWE
VIH; all other
inputs
VIL or
VIH; VCC = MAX;
cycle time
tKC MIN: outputs open
ISB1 TBD
60
60
60
mA
12, 13
CMOS Standby
Device deselected; VCC = MAX; all
inputs
VSS + 0.2 or
VCC - 0.2;
all inputs static; CLK frequency =0
ISB2 TBD
10
10
10
mA
12, 13
TTL Standby
Device deselected; all inputs
VIL
or
VIH; all inputs static; VCC =
MAX;CLK frequency = 0
ISB3 TBD
25
25
25
mA
12, 13
Clock Running
Device deselected; all inputs
VIL
or
VIH; VCC =MAX; CLK cycle
time
tKCMIN
ISB4 TBD
60
60
60
mA
12, 13
TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
P.9
Publication Date: FEB. 2000
to change products or specifications without notice.
Revision:0.A
AC ELECTRICAL CHARACTERISTICS
(Note 5)
(0
C
TA
70
C;VCC=3.3V +0.3V/-0.165V)
-3.8
-4
-4.5
DESCRIPTION
SYM.
MIN MAX MIN MAX MIN MAX
UNITS
NOTES
Clock(pipeline)
Clock cycle time
tKC
6.6
7.5
8.5
ns
Clock to output valid
tKQ
3.8
4
4.5
Clock to output invalid
tKQX
1.5
2
2
ns
Clock to output in Low-Z
tKQLZ
1.5
2
2
ns
Clock(flow-through)
Clock cycle time
tKC
10.5
15
15
ns
Clock to output valid
tKQ
9.0
10
11
Clock to output invalid
tKQX
3
3
3
ns
Clock to output in Low-Z
tKQLZ
3
3
3
ns
Output Times
Clock HIGH time
tKH
1.8
1.9
2.0
ns
Clock LOW time
tKL
1.8
1.9
2.0
ns
6, 7
Clock to output in High-Z
tKQHZ
5
5
5
ns
6, 7
OE to output valid
tOEQ
5
5
5
ns
9
OE to output in Low-Z
tOELZ
0
0
0
ns
6, 7
OE to output in High-Z
tOEHZ
5
5
5
ns
6, 7
Setup Times
Address
tAS
1.7
2.0
2.0
ns
8, 10
Address Status( ADSC , ADSP )
tADSS 1.7
2.0
2.0
ns
8, 10
Address Advance ( ADV )
tAAS
1.7
2.0
2.0
ns
8, 10
Byte Write Enables
( BW1~ BW4 , BWE , GW )
tWS
1.7
2.0
2.0
ns
8, 10
Data-in
tDS
1.7
2.0
2.0
ns
8, 10
Chip Enables( CE , CE2 ,CE2)
tCES
1.7
2.0
2.0
ns
8, 10
Hold Times
Address
tAH
0.5
0.5
0.5
ns
8, 10
Address Status( ADSC , ADSP )
tADSH 0.5
0.5
0.5
ns
8, 10
Address Advance ( ADV )
tAAH
0.5
0.5
0.5
ns
8, 10
Byte Write Enables
( BW1~ BW4 , BWE , GW )
tWH
0.5
0.5
0.5
ns
8, 10
Data-in
tDH
0.5
0.5
0.5
ns
8, 10
Chip Enables( CE , CE2 ,CE2)
tCEH
0.5
0.5
0.5
ns
8, 10
TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
P.10
Publication Date: FEB. 2000
to change products or specifications without notice.
Revision:0.A
CAPACITANCE
DESCRIPTION
CONDITIONS
SYM.
TYP
MAX
UNITS NOTES
Input Capacitance
CI
3
4
pF
4
Input/ Output
Capacitance(DQ)
TA = 25
C; f = 1 MHz
VCC = 3.3V
CO
6
7
pF
4
THERMAL CONSIDERATION
DESCRIPTION
CONDITIONS
SYM. QFP TYP UNITS NOTES
Thermal Resistance - Junction to Ambient
JA
20
C/W
Thermal Resistance - Junction to Case
Still air, soldered on
4.25x1.125 inch 4-layer
PCB
JB
1
C/W
AC TEST CONDITIONS
Input pulse levels
0V to 3.0V
Input rise and fall times
1.5ns
Input timing reference levels
1.5V
Output reference levels
1.5V
Output load
See Figures 1 and
2
Notes:
1. All voltages referenced to VSS (GND).
2. Overshoot: VIH
+3.6 V for t
tKC/2.
Undershoot: VIL
-1.0 V for t
tKC/2.
3. Icc is given with no output current. Icc increases
with greater output loading and faster cycle
times.
4. This parameter is sampled.
5. Test conditions as specified with the output
loading as shown in Fig. 1 unless otherwise
noted.
6. Output loading is specified with CL = 5 pF as in
Fig. 2.
7. At any given temperature and voltage condition,
tKQHZ is less than tKQLZ and tOEHZ is less
than tOELZ.
8. A READ cycle is defined by byte write enables
all HIGH or
ADSP
LOW along with chip
enables being active for the required setup and
hold times. A WRITE cycle is defined by at one
byte or all byte WRITE per READ/WRITE
TRUTH TABLE.
9.
OE
is a "don't care" when a byte write enable
is sampled LOW.
10.This is a synchronous device. All synchronous
inputs must meet specified setup and hold time,
except for "don't care" as defined in the truth
table.
11.AC I/O curves are available upon request.
12."Device Deselected means the device is in
POWER-DOWN mode as defined in the truth
table. "Device Selected" means the device is
active.
13.Typical values are measured at 3.3V, 25
C and
20ns cycle time.
14.MODE pin has an internal pull-up and exhibits
an input leakage current of
10
A.
OUTPUT LOADS
TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
P.11
Publication Date: FEB. 2000
to change products or specifications without notice.
Revision:0.A
D Q
3.3V
317
o h m
351
o h m
5 pF
Z
0
= 50 ohm
5 0
o h m
Vt = 1.5V
D Q
Fig. 1 output load equivalent
Fig. 2 output load equivalent
TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
P.12
Publication Date: FEB. 2000
to change products or specifications without notice.
Revision:0.A
SNOOZE MODE
SNOOZE MODE is a low current, "power
down" mode in which the device is deselected and
current is reduced to I
ZZ.
The duration of
SNOOZE MODE is dictated by the length of time
the ZZ pin is in a HIGH state. After entering
SNOOZE MODE, the clock and all other inputs
are ignored.
The ZZ pin (pin 64) is an
asynchronous, active HIGH input that causes the
device to enter SNOOZE MODE. When the ZZ
pin becomes a logic HIGH, I
ZZ
is guaranteed after
the setup time tZZ is met. Any access pending
when entering SNOOZE MODE is not guaranteed
to successfully complete. Therefore, SNOOZE
MODE must not be initiated until valid pending
operations are completed.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Current during
SNOOZE MODE
ZZ
V
IH
I
ZZ
5
mA
ZZ HIGH to
SNOOZE MODE time
tZZ
2(tKC)
ns
4
SNOOZE MODE
Operation Recovery Time
tRZZ
2(tKC)
ns
4
SNOOZE MODE WAVEFORM
C LK
Z Z
tRZZ
tZZ
I
Z Z
I
SUPPLY
DON'T CARE
CE
I
SUPPLY
Note:
1. The
CE
signal shown above refers to a TRUE state on all chip selects for the device.
2. All other inputs held to static CMOS levels (VIN
Vss + 0.2 V or
Vcc -0.2 V).