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Электронный компонент: T431616A-7CI

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TE
CH
tm
T431616A
Taiwan Memory Technology, Inc. reserves the right P. 1
Publication Date: DEC. 2000
to change products or specifications without notice. Revision:
C
SDRAM
1M x 16 SDRAM
512K x 16bit x 2Banks Synchronous DRAM
FEATURES
3.3V power supply
Clock cycle time : 6 / 7 / 8 / 10 ns
Dual banks operation
LVTTL compatible with multiplexed address
All inputs are sampled at the positive going
edge of system clock
Burst Read Single-bit Write operation
DQM for masking
Auto refresh and self refresh
32ms refresh period (2K cycle)
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1 , 2 , 4 , 8 & full page)
- Burst Type (Sequential & Interleave)
Available package type in 50 pin TSOP(II)
and 60-pin CSP.
Operating temperature :
- -5 ~ +70
C
-
-40 ~ +85
C

PART NUMBER EXAMPLES
GRNERAL DESCRIPTION
The T431616A is 16,777,216 bits synchronous
high data rate Dynamic RAM organized as
2 x 524,288 words by 16 bits , fabricated with high
performance CMOS technology . Synchronous
design allows precise cycle control with the use of
system clock I/O transactions are possible on every
clock cycle . Range of operating frequencies ,
programmable burst length and programmable
latencies allow the same device to be useful for a
variety of high bandwidth , high performance
memory system applications.
PART NO.
CLOCK
CYCLE TIME
MAX
FREQUENCY
PACKAGE
OPERATING
TEMPERATURE
T431616A-7S
7ns
143 MHz
TSOP-II
-5 ~ +70
C
T431616A-7C
7ns
143 MHz
CSP
-5 ~ +70
C
T431616A-7SI
7ns
143 MHz
TSOP-II
-40 ~ +85
C
T431616A-7CI
7ns
143 MHz
CSP
-40 ~ +85
C
TE
CH
tm
T431616A
Taiwan Memory Technology, Inc. reserves the right P. 2
Publication Date: DEC. 2000
to change products or specifications without notice. Revision:
C
PIN ARRANGEMENT


(TSOP-II
Top View)
DQ1
V
DD
46
45
44
43
41
42
40
36
35
34
33
32
31
30
29
1
2
3
4
6
5
7
8
9
11
15
16
17
18
19
20
V
DDQ
DQ11
DQ10
A8
A7
A9
10
21
22
47
48
49
50
V
SSQ
DQ2
A0
A1
DQ15
DQ14
V
SSQ
Vss
23
24
25
28
27
26
DQ3
DQ0
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
RAS
CS
BA
A10/AP
A2
A3
V
DD
V
SSQ
DQ13
DQ12
DQ9
UDQM
N.C
CLK
CKE
Vss
A6
A5
A4
12
13
14
39
38
37
DQ7
V
DDQ
LDQM
DQ8
V
DDQ
N.C/RFU
WE
CAS
50PINTSOP(II)
(400mil x 825mil)
(0.8 mm PIN PITCH)



(CSP Bottom View)
R
P N M L
J
H G
E
F
K
A
B
C
D
1
2
3
4
5
6
7
VDD
A1
A10/AP
N.C
N.C
N.C
A0
A2
A3
A4
A5
A6
A7
A8
A9
BA
VSS
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
CKE
CLK
VDD
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ15
DQ14
VSS
DQ13
DQ12
DQ11
DQ10
DQ9
DQ0
VDDQ
VSSQ
VDDQ
VSSQ
VSSQ
VSSQ
LDQM
WE
CAS
CS
RAS
DQ8
UDQM
VDDQ
VDDQ
TE
CH
tm
T431616A
Taiwan Memory Technology, Inc. reserves the right P. 3
Publication Date: DEC. 2000
to change products or specifications without notice. Revision:
C
BLOCK DIAGRAM
Data Input Register
I/O
C
o
n
t
ro
l
O
u
t
put
B
u
f
f
er
512K x 16
512K x 16
Se
ns
e
A
M
P
Column Decoder
Latency & Burst Length
Programming Register
Bank Select
Ro
w
Bu
f
f
e
e
r
Re
f
r
e
s
h
Co
u
n
t
e
r
R
o
w
D
eco
der
A
d
dr
es
s
R
e
gi
s
t
er
Co
l
.
Bu
f
f
e
r
Timing Register
DQi
LDQM
LW E
LDQM
LW CBR
LCAS
LW E
LCBR
LRAS
L(U)DQM
RAS
CS
CKE
CLK
LCBR
LRA
S
ADD
CLK
LCKE
CAS
W E



















TE
CH
tm
T431616A
Taiwan Memory Technology, Inc. reserves the right P. 4
Publication Date: DEC. 2000
to change products or specifications without notice. Revision:
C
PIN DESCRIPTION
PIN
NAME
INPUT FUNCTION
CLK System
Clock
Active on the positive going edge to sample all input.
CS
Chip Select
Disables or enables device operation by masking or enabling all input
except CLK,CKE and L(U)DQM
CKE Clock
Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A10/AP
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10,column address : CA0 ~ CA7
BA
Bank Select Address
Selects bank to be activated during row address latch time.
Select bank for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK
with
RAS
low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column addresses on the positive going edge of the CLK
with
CAS low.
Enables column access .
WE
Write Enable
Enables write operation and row precharge.
Latches data in starting from
CAS
,
WE
active.
L(U)DQM
Data Input/Output
Mask
Makes data output Hi-Z,
t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ0 ~ DQ15
Data Input/Output
Data inputs/outputs are multiplexed on the same pins.
V
DD
/V
SS
Power
Supply/Ground
Power and ground for the input buffers and the core logic.
V
DDQ
/V
SSQ
Data Output
Power/Ground
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
N.C/RFU
No
Connection/Reserved
for Future Use
This pin is recommended to be left No Connection on the device.
TE
CH
tm
T431616A
Taiwan Memory Technology, Inc. reserves the right P. 5
Publication Date: DEC. 2000
to change products or specifications without notice. Revision:
C
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on Any Pin Relative To Vss
V
IN
,V
OUT
-1.0 to 4.6
V
Supply Voltage Relative To Vss
V
DD
,V
DDQ
-1.0
to
4.6
V
Short circuit Output Current
Iout 50 mA
Power Dissipation
P
D
1 W
Operating Temperature
TOPR
-5 to +70 / -40 to +85
C
Storage Temperature
Tstg
-55 to +125
C
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
= -5 to +70 C / -40 to +85 C , Voltage referenced to V
SS
=0V)
Parameter Symbol
Min.
Typ
Max.
Unit
Notes
Supply Voltage
V
DD
,V
DDQ
3.0
3.3
3.6
V
Input High Voltage
V
IH
2.0 3.0
V
DD
+0.3V V
1
Input Low Voltage
V
IL
-0.3 0 0.8 V 2
Output logic high voltage
V
OH
2.4 -
- V
I
OH
=-2mA
Output logic low voltage
V
OL
- - 0.4 V
I
OL
=2mA
Input leakage current
I
IL
-5 - 5 uA
3
Output leakage current
I
OL
-5 - 5 uA 4
Note : 1. V
IH
(max) = 4.6V AC for pulse width
10ns acceptable.
2. V
IL
(min) = -1.0V AC for pulse width
10ns acceptable.
3. Any input 0V
V
IN
V
DD
+ 0.3V , all other pin are not under test = 0V.
4. Dout = disable, 0V
V
OUT
V
DD .

CAPACITANCE
(T
A
=25
C
,V
DD
=3.3V, f = 1MHz)
Pin Symbol
Min
Max
Unit
CLOCK C
CLK
2.5 4.0 pF
ADDRESS C
ADD
2.5 5.0 pF
DQ0 ~ DQ15
C
OUT
4.0 6.5 pF
RAS,CAS,WE,CS,CKE,LDQM,
UDQM
C
IN
2.5 5.0
pF