Preliminary T67H0002A

Taiwan Memory Technology, Inc. reserves the right

Publication Date:Nov. 2001

to change products or specifications without notice

-P1

T67H0002Av0.A

T67H0002A

258 Output TFT-LCD Gate Driver IC

Features

l Gate Driver LSI for ActiveMatrix LCD.

l 258 outputs for 3 output level.

l Enables High-Voltage Output Level Max. to

VEE+40V.

l Negative Output Voltage is Enabled by a

Level-Shift Circuit.

l On-Chip Bidirectional Shift Registers.

l CMOS-LSI Structure.

Part Number Examples

Part NO.

Pkg.

Description

T67H0002A-Y

TCP

Tape Carrier Package

General Description

The T67H0002A is a gate driver LSI that
drives an active matrix LCD panel and
implements a multi-pin configuration,
low power consumption and high voltage.
Furthermore, the level-shift circuit applies
positive and negative power supplies. It
also compatible with several SXGA/XGA
panels.

Preliminary T67H0002A

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Publication Date:Nov. 2001

to change products or specifications without notice

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T67H0002Av0..A

Block diagram

BF : Output Buffer

LS : Level Shifter

SR : Shift Register

IOLS : IN/OUT Level Shifter

STV1B

XAO

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT256

OUT257

OUT258

VCOM

VSS

VEE

VDD

CPV

L/R

STV1A

XOE

STV2B

STV2A

I/O Level Shift

Preliminary T67H0002A

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Publication Date:Nov. 2001

to change products or specifications without notice

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T67H0002Av0..A

Pin Configurations (TCP type)

T 6 7 H 0 0 0 2 A

O
U
T

O
U
T
2

O
U
T
3

O
U
T
4

O
U
T
5

O
U
T
6

O
U
T
2
5
3

O
U
T
2
5
4

O
U
T
2
5
5

O
U
T
2
5
6

O
U
T

2
5
7

O
U
T

2
5
8

V
E
E

V
L

V
C
O
M

S
T
V
1
A

S
T
V
1
B

V
S
S

C
P
V

V
D
D

X
O
E

X
A
O

O
S

S
T
V

V
C
O
M

V
L

V
E
E

.....................

Preliminary T67H0002A

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Publication Date:Nov. 2001

to change products or specifications without notice

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T67H0002Av0..A

Pin Descriptions

SYMBOL

I/O FUNCTION

CPV

Vertical shift clock input for shift register.

Data shifted are synchronous with the rising edge of this pin.

XOE

Output clear enable pin.

XOE=L: The output pins are held low(VL). However, the shift registers are not
cleared. XOE is asynchronous to CPV.

L/R

Shift direction switching pin.

When L/R = H:

STV2A,B àOUT258àOUT257.....àOUT2àOUT1àSTV1A,B

When L/R = L:

STV1 A,B à OUT 1à OUT 2..... à OUT257 à OUT258 à STV2 A,B

STV1 A,B

STV2 A,B

I/O

Shift Data I/O pin.

These pins are used to input/output data to/from a shift register.

During input, data are captured in sync
With the leading edge of CPV .During output, data are output in sync

With its trailing edge.

When L/R = L: STV1A, B are used as shift data input pins, while STV2A,B, output

pins and as next stage input signal.

When L/R = H, STV2A, B are used as shift data input pins, while STV1A,B, output
pins and as next stage input signal.

VCOM output voltage elimination pin.

While OS=H: On CPV=H duration, if output level is VCOM, the level will be fixed
on VEE. The output is not used if the output voltage is not VCOM.

XAO

All of output enable pin:

XAO=L: The liquid -crystal control output is held VCOM, However, the shift. Reg-

isters are not cleared XAO is asynchronous with CPV

OUT
1 ~258

Liquid-crystal control output pins. Shift register data are output after level transferred

VCOM

Power supply for LCD driver output High.

VDD

Logic GND supply pin.

VSS

Logic system power supply pin, connected to 0 V.

Power supply for LCD driver output low.

VEE

GND

Preliminary T67H0002A

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to change products or specifications without notice

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T67H0002Av0..A

Operation Description

The liquid-crystal control outputs(OUT1-258)Output 3 selective signal ,depending on
the input signals(STV1A,B and STV2A,B,CPV,XOE,XAO,OS).A right data shift
(OUT1àOUT258)or a left data shift (OUT258àOUT1)can be selected by means of the
shift direction switching pin(L/R).when the L/R pin is L ,the Vertical shift
data(STV1A,B)are captured at the leading edge of the shift clock(CPV),after which they
are output to the liquid-crystal control output OUT1.Furthermore .the OUT1 output data
are shifted to OUT2 at the leading edge of the next CPV ,and the data newly fetched from
STV1A,B are output to OUT1,In this manner ,they are shifted successively in sync with
the leading edge of CPV ,and the OUT258 data are output to STV2A,B in sync with the
trailing edge of CPV .When the L/R pin is H ,the vertical shift data(STV2A,B)are
captured at the leading edge of the shift clock(CPV),after which they are output to the
liquid-crystal control output OUT258. Furthermore, the OUT258 output data are shifted
to OUT257 at the leading edge of the next CPV, and the data newly fetched from STV2,
B are output to OUT258 .In this manner, they are shifted successively in sync with the
leading edge of CPV ,and the OUT1 data are output to STV1A,B in sync with the trailing
edge of CPV.

XOE/OS/XAO Function:

XOE is normally H, if XOE is L, LCD output voltage is changed to VLL.

OS is normally L, if OS is H, and LCD output voltage is VCOM.
It changed to VEE during CPV is H,

But the function in no used if LCD output is not VCOM.

XAO is normally H, if XAO is L, LCD output voltage is changed to VCOM.
XOE/OS/XAO priority is (1) XAO (2) XOE (3) OS

Preliminary T67H0002A

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Publication Date:Nov. 2001

to change products or specifications without notice

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T67H0002Av0..A

Operation Mode :L/R=L,OS=L

CPV

STV1A

(STV2A)

STV1B

(STV2B)

VCOM

VEE

VCOM

VEE

OUT1

(OUT258)

OUT2

(OUT257)

VCOM

VEE

VCOM

VEE

OUT3

(OUT256)

OUT4

(OUT255)

OUT257

(OUT2)

OUT258

(OUT1)

VCOM

VEE

VCOM

VEE

STV2A

(STV1A)

STV2B

(STV1B)

VCOM

VEE

OUT1

(OUT258)

OUT2

(OUT257)

VCOM

VEE

OUT3

(OUT256)

VCOM

VEE

*Note: if have( ) for L/R=H,O/S=L

Preliminary T67H0002A

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Publication Date:Nov. 2001

to change products or specifications without notice

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T67H0002Av0..A

STV1A,B/STV2A,B Shift Register Truth Table

STV1A,2A

STV1B,2B

(OUT1~257: L/R=H)

(OUT2~258: L/R=L)

VCOM

VEE

STV1A,2A

STV1B,2B

(OUT258: L/R=H)

(OUT1: L/R=L)

VEE

X: Don't care

VOLTAGE BIASING

Liquid-Crystal Control Output
The T67H0002A supplies negative voltage output for liquid-crystal control output.

VCOM-VEE=40V max.
VL-VEE=0~10V.
VCOM-VSS=17~28V.

For the input signals ( CPV , XOE , XAO , L/R, STV1A,B , STV2A,B ), input the level of VSS to VDD.

The next -stage data output pins(STV1A,B, STV2A,B) output the level for next stage.

H=VDD

L=VSS

VCOM

VDD

VSS

VEE

OUPUT

INPUT

Preliminary T67H0002A

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Publication Date:Nov. 2001

to change products or specifications without notice

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T67H0002Av0..A

ABSOLUTE MAXIMUM RATINGS (VSS = 0 V)

PARAMETER

SYMBOL

RATING

UNIT

Supply voltage(1)

VDD

-0.3 ~ +7.0

Supply voltage(2)

VCOM

-0.3 ~ 42.0

Supply voltage(3)

VEE

-20.0 ~ +0.3

Supply voltage(4)

VEE-0.3 ~ VEE+11.0

Supply voltage(5)

VCOM-VEE

-0.3 ~ 42.0

Input voltage

VIN

-0.3 ~ VDD+0.3

Storage temperature

TSTR

-55 ~ +125

ºC

CAUTIONS

If the absolute maximum rating is exceeded momentarily, the quality of this product may be degraded.

It is desirable to use this product within the range of the absolute maximum ratings.

The power supplying order is as follows.

ON: VDDà Control Inputà VEE àVCOM

OFF: VCOMàControl Input àVEEàVDD

Recommended Operation Ratings (VSS = 0 V)

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

Supply voltage(1)

VDD

3.0

3.3

3.6

Supply voltage(2)

VCOM

Supply voltage(3)

VEE

-15

-5

Supply voltage(4)

VL-VEE

10.0

Supply voltage(5)

VCOM-VEE

Operation frequency

fCPV

100

KHz

Operating temperature

-20

+75

ºC

Time

Voltage

VEE (VL)

VDD

VCOM

Logic signal

Preliminary T67H0002A

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Publication Date:Nov. 2001

to change products or specifications without notice

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T67H0002Av0..A

ELECTRICAL CHARACTERISTICS

DC Characteristics

PARAMETER SYMBOL CONDITIONS

MIN.

TYP.

MAX.

UNIT

APPLICABLE

PINS

Input "Low"

voltage

VSS

0.3xVDD

INPUT PINS

Input "High"

voltage

0.7xVDD

VDD

INPUT PINS

Output "Low"

voltage

IOL = 40uA

VSS

Vss+0.4

STV1A,B

Output "High"

voltage

IOH = 40uA

VDD-0.4

VDD

STV2A,B

VCOM=

Output resis-

tance

(NOTES2)

VEE+0.5V

400

1000

Ohm

OUT 1~258

VCOM=

Output resis-

tance

OL2

(NOTES2)

VL+0.5V

400

1000

Ohm

OUT 1~258

VCOM=

Output resis-

tance

VCOM-0.5V

500

1000

Ohm

OUT 1~258

Input leakage

current

VIL=VSS

-5

INPUT PINS

Except XAO

Input leakage

current

VIH=VDD

-5

All INPUT

PINS

Output resis-

tance

VIL = VSS

200

Kohm

XAO

Supply current

(1)

NOTE(1)

1000

Supply current

(2)

COM

100

NOTES :

The OUTPUT are NO LOAD ,The input VIH=VDD , VIL=VSS , fCPV=50KHz .

1/768 duty form LCD operation current.

VCOM=+25V ,VL=0V ,VEE=-10V

Preliminary T67H0002A

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Publication Date:Nov. 2001

to change products or specifications without notice

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T67H0002Av0..A

AC Characteristics

PARAMETER

SYMBOL

CONDITIONS

MIN. TYP. MAX

UNIT

Operation frequency

fCPV

100

KHz

CPVH

CPV pulse width

CPVL

/XOE enable time

WOE

Data setup time

tsu

700

Data hold time

thd

700

Output delay time (1)

PD1

CL= 20 pF

800

Output delay time (2)

PD2

CL= 300 pF

1000

Output delay time (3)

PD3

CL= 300 pF

1000

Output delay time (4)

PD4

CL= 300 pF

1000

Output delay time (5)

PD5

CL= 300 pF

1000

Time rise

Time fall

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T67H0002Av0..A

Timing Chart (L/R=L)

tr tf : vibration 10%~90%

t C P V H

t C P V L

S T V 2 A . B

S T V 1 A , B

C P V

5 0 %

t P D 1

t H D

t S U

C P V

90%

10%

VCOM

VEE

O U T 1

~ 2 5 8

t P D 2

t P D 3

t W O E

10%

90%

5 0 %

X O E

VCOM

O U T 1

~ 2 5 8

VEE

( O S = " H " )

C P V

10%

90%

50%

90%

5 0 %

VCOM

VEE

VCOM

X A O

O U T 1

~ 2 5 8

O U T 1

~ 2 5 8

t P D 5

t P D 4

t C P V H

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