2 Channel Voltage Detectors
Series
169
2
General Description
Features
Applications
V
IN
V
IN2
V
DET1
V
SS
V
IN1
V
DET2
R
R=100k
V
DET1
CMOS, V
DET2
N-ch Open drain
Typical Application Circuit
Typical Performance
Characteristic
SUPPLY CURRENT vs. INPUT VOLTAGE
GMemory battery back-up circuitry
GMicroprocessor reset circuits
GPower failure detection
GSystem power-on reset circuits
GSystem battery life monitors and re-charge voltage monitors
GDelay circuitry
NCMOS Low Power Consumption
N2 Voltage Detectors Built-in
NDetect Voltage Accuracy : 2%
NDetect Voltage Range
: 1.5V ~ 5.0V
NSOT-25 Package
The XC612 series consist of 2 voltage detectors, in 1 mini-molded, SOT-
25 package.
The series provides accuracy and low power consumption through
CMOS processing and laser trimming and consists of a highly accurate
voltage reference source, 2 comparators, hysteresis and output driver
circuits.
The input (V
IN1
) for voltage detector 1 (V
D1
) dually functions as the power
supply pin for both detector 1 (V
D1
) and detector 2 (V
D2
).
Highly accurate
: Set-up voltage accuracy 2%
Low-power consumption
: Typ.2.0
A (V
IN1
=V
IN2
=2.0V, quiescent state)
Detect voltage
: 1.5V ~ 5.0V programmable in
0.1V steps. Detector's voltages
can be set-up independently
Conditionaly,
XC612N : V
DET1
>V
DET2
XC612D, XC612E : V
DET1
V
DET2
,
V
DET1
<V
DET2
Operating Voltage Range : 1.
0V ~ 10.0V
Temperature characteristics : 100ppm/C
Output configuration
: N-channel open drain
Small package
: SOT-25 (150mW) mini-mold
* CMOS Output is under development
0
1.0
2.0
3.0
4.0
5.0
6.0
0
2
4
6
8
10
25
Ta=80
-30
Supply Current: Iss (
A)
Input Voltage: V
IN1
(V)
(V
IN1
V
IN2
)
02S_05XC612 02.09.12 14:15 169
XC612
Series
170
2
Pin Configuration
Pin Assignment
Product Classification
GSelection Guide
GOrdering Information
SOT-25
TOP VIEW
5
4
V
DET2
V
DET1
IN2
V
IN1
V
SS
1
3
2
PIN NUMBER
1
PIN NAME
FUNCTION
2
4
5
Detector 1 input,
Power Supply.
Voltage Detector 1 output
Voltage Detector 2 Input
Voltage Detector 2 Output
3
Ground
V
DET1
V
IN2
V
DET2
V
IN1
V
SS
Type
V
DET1
V
DET2
XC612N
N-ch Open drain
N-ch Open drain
XC612D
N-ch Open drain
CMOS
XC612E
CMOS
N-ch Open drain
a b c d e
XC612 x x x x x x x
e.g.33=3.3V
50=5.0V
DESIGNATOR
a
d
e
b
c
DESCRIPTION
DESIGNATOR
DESCRIPTION
Output Configuration:
N=N-Channel Open Drain
D=V
DET1
N-ch Open Drain, V
DET2
CMOS
E=V
DET1
CMOS, V
DET2
N-ch Open Drain
Detect Voltage (V
DET1
)
e.g.25=2.5V
38=3.8V
Detect Voltage (V
DET2
)
Package Type:
M=SOT-25
Device Orientation
R=Embossed Tape (Orientation of Device: Right)
L=Embossed Tape (Orientation of Device: Left)
02S_05XC612 02.09.12 14:15 170
XC612
Series
171
2
Marking
Packaging Information
GSOT-25
0.4
0.95
1.90.2
2.90.2
+0.1
-0.05
1.10.1
00.1
0.15
0.2min
+0.1
-0.05
2.80.2
1.6
+0.2
-0.1
SOT-25
(TOP VIEW)
DESIGNATOR
N
D
E
CONFIGURATION
V
DET1
N-ch Open drain
N-ch Open drain
CMOS
V
DET2
N-ch Open drain
CMOS
N-ch Open drain
PRODUCT NAME
XC612N****M*
XC612D****M*
XC612E****M*
q Represents the output configuration
we Represents the entry order.
r Denotes the production lot number
0 to 9, A to Z repeated. (G.I.J.O.Q.W excepted)
02S_05XC612 02.09.12 14:15 171
XC612
Series
172
2
Block Diagram
V
IN1
V
IN2
V
DET1
V
DET2
Vref
V
SS
XC612N Series
V
IN1
V
IN2
V
DET1
V
DET2
Vref
V
SS
XC612D Series
V
IN1
V
IN2
V
DET1
V
DET2
Vref
V
SS
XC612E Series
02S_05XC612 02.09.12 14:15 172
XC612
Series
173
2
Absolute Maximum Ratings
PARAMETER
Input Voltage V
IN1
Input Voltage V
IN2
Output Voltage V
DET1
(N-ch Open drain)
Output Voltage V
DET1
(CMOS)
Output Current V
DET1
Output Voltage V
DET2
(N-ch Open drain)
Output Voltage V
DET2
(CMOS)
Output Current V
DET2
Power Dissipation
Operating Ambient Temperature
Storage Temperature
SYMBOL
V
IN1
V
IN2
V
VDET1
V
VDET1
I
VDET1
V
VDET2
V
VDET2
I
VDET2
Pd
Topr
Tstg
UNITS
V
V
V
V
mA
V
V
mA
mW
CONDITIONS
12
12
V
SS
-0.312
V
SS
-0.3V
IN1
0.3
50
V
SS
-0.312
V
SS
-0.3V
IN1
0.3
50
150
-3080
-40125
Ta25
02S_05XC612 02.09.12 14:15 173
XC612
Series
174
2
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Detect Voltage
V
DET1
V
DF1
Voltage when V
DET1
changes from
H to L following a reduction of V
IN1
V
DF1
x 0.98
V
DF1
V
DF1
x 1.02
V
Detect Voltage
V
DET2
V
DF2
Voltage when V
DET2
changes from
H to L following a reduction of V
IN2
V
DF2
x 0.98
V
DF1
x 1.02
V
DF2
V
Hysteresis Range 1
V
HYS1
Voltage (V
DR1
) - V
DF1
when V
DET1
changes
from L to H following an increase of V
IN1
V
DF1
(T)
x 0.08
V
DF1
(T)
x 0.05
V
DF1
(T)
x 0.02
V
DF2
(T)
x 0.08
V
DF
2(T)
x 0.05
V
DF2
(T)
x 0.02
Hysteresis Range 2
V
HYS2
Voltage (V
DR2
) - V
DF2
when V
DET2
changes
from L to H following an increase of V
IN2
Supply Current
(Input Current V
IN1
)
I
SS
3.90
4.50
5.10
5.70
6.30
1.35
1.50
1.95
2.40
3.00
V
IN1
=1.5V
2.0V
3.0V
4.0V
5.0V
1.30
1.50
1.70
1.90
2.10
0.45
0.50
0.65
0.80
1.00
V
IN1
=1.5V
2.0V
3.0V
4.0V
5.0V
A
Input Current V
IN2
I
IN2
A
Operating Voltage
V
IN1
V
DF
(T) = 1.5V to 6.0V
10
1.5
V
Output Current
*
I
VDET
N-ch
P-ch
V
DS
= 0.5V
2.2
7.7
10.1
11.5
13.0
-10.0
-2.0
0.3
3.0
5.0
6.0
7.0
V
IN1
=1.0V
V
IN1
=2.0V
V
IN1
=3.0V
V
IN1
=4.0V
V
IN1
=5.0V
V
DS
= -2.1V
V
IN1
=8.0V
(CMOS)
mA
Temperature Characteristics
*
30:
Topr 80:
100
-
ppm/:
Transient Delay Time
*
(Release Voltage
Output Conversion)
tDLY
0.2
ms
(V
DR
V
OUT
conversion)
CIRCUIT
1
1
1
V
1
2
2
-
3
-
5
V
DF
Topr
V
DF
1. V
DF1
(T), V
DF2
(T) : User specified detect voltage.
2. Release voltage (V
DR
) = V
DF
+V
HYS
3. Those parameters marked with an asterisk apply to both V
DET1
and V
DET2
.
4. Input Voltage : please ensure that V
IN1
> V
IN2
(Input voltage of XC612D and XC612E series : please ensure that V
IN1
V
IN2
, V
IN1
< V
IN2
.)
5. V
IN1
pin serve both I
SS
and power supply pin so that V
IN2
operates V
IN1
as a power supply source. For normal operation of V
IN2
, operating voltage
higher than the minimum is needed to be applied to power supply pin V
IN1
.
6. For CMOS output products, high level output voltage which is generated when the transient response is released becomes input voltage of V
IN
.
Electrical Characteristics
02S_05XC612 02.09.12 14:15 174
Operating Explanation
GTiming Chart (Pull up voltage =Input voltage V
IN1
)
GOperational Notes (N-ch Open drain)
Timing Chart A (V
IN1
=voltages above release voltage, V
IN2
=sweep voltage)
Because a voltage higher than the minimum operating voltage is applied to the voltage input pin (V
IN
), ground voltage will be output at the
output pin (V
DET
) during stage 3. (Stages 1, 2, 4, 5 are the same as in B below).
Timing Chart B (V
IN1
=V
IN2
)
q When a voltage greater than the release voltage (V
DR
) is applied to the voltage input pin (V
IN1
, V
IN2
), input voltage (V
IN1
, V
IN2
) will gradually
fall.
When a voltage greater than the detect voltage (V
DF
) is applied to the voltage input pin (V
IN1
, V
IN2
), a state of high impedance will exist at
the output pin (V
DET1
, V
DET2
), so should the pin be pulled up, voltage will be equal to pull up voltage.
w When input voltage (V
IN1
, V
IN2
) falls below detect voltage (V
DF
), output voltage (V
DET1
, V
DET2
) will be equal to ground level (V
SS
).
e Should input voltage (V
IN1
, V
IN2
) fall below the minimum operational voltage (V
MIN
), output will become unstable. Should V
IN2
fall below V
MIN
,
voltage at the output pin (V
DET2
) will be equal to ground level (V
SS
) if the power supply (V
IN1
) is within the operating voltage range.
*In general the output pin is pulled up so output will be equal to pull up voltage.
r Should input voltage (V
IN1
, V
IN2
) rise above ground voltage (V
SS
), output voltage (V
DET1
, V
DET2
) will equal ground level until the release
voltage level (V
DR
) is reached.
t When input voltage (V
IN1
, V
IN2
) rises above release voltage, the output pin's (V
DET1
, V
DET2
) voltage will be equal to the voltage dependent on
pull up.
Note : The difference between release voltage (V
DR
) and detect voltage (V
DF
) is the Hysteresis Range y.
A
B
Input VoltageV
IN1
Release VoltageV
DR1
Detect VoltageV
DF1
Min. Operating VoltageV
MIN
Ground VoltageV
SS
Input VoltageV
IN2
Release VoltageV
DR2
Detect VoltageV
DF2
Min. Operating VoltageV
MIN
Ground VoltageV
SS
Min. Operating VoltageV
MIN
Ground VoltageV
SS
Output VoltageV
DET1
Output VoltageV
DET2
Min. Operating VoltageV
MIN
Ground VoltageV
SS
1
3
4
5
A
2
1
3
4
5
B
2
6
6
6
6
XC612
Series
175
2
02S_05XC612 02.09.12 14:15 175
XC612
Series
176
2
XC612N Series
XC612N Series
IN
(includes through current)
voltage drop
1. Voltage detector 2's input voltage (V
IN2
)
An input protect diode is connected from input detector 2's input (V
IN2
) to input detector 1's input. Therefore, should
the voltage applied to V
IN2
exceed V
IN1
, current will flow through V
IN1
via the diode. (refer to diagram1)
2. Oscillation as a result of through current
Since the XC612 series are CMOS ICs, through current will flow when the IC's internal circuit switching operates
(during release and detect operations). Consequently, oscillation is liable to occur as a result of drops in voltage at
the through current's resistor (R
IN
) during release voltage operations. (refer to diagram 2)
Since hysteresis exists during detect operations, oscillation is unlikely to occur.
1. Please use this IC within the specified maximum absolute ratings.
2. Please ensure that input voltage V
IN2
is less than V
IN1
+ 0.3V. (refer to N.B. 1 below)
3. With a resistor connected between the V
IN1
pin and the input, oscillation is liable to occur as a result of through current at
the time of release. (refer to N.B. 2 below)
4. With a resistor connected between the V
IN1
pin and the input, detect and release voltage will rise as a result of the IC's sup-
ply current flowing through the V
IN1
pin.
5. In order to stabilise the IC's operations, please ensure that the V
IN1
pin's input frequency's rise and fall times are more than
5
sec/V.
6. Should the power supply voltage V
IN1
exceed 6V, voltage detector 2's detect voltage (V
DF2
) and the release voltage (V
DR2
)
will shift somewhat.
7. For CMOS output products, high level output voltage which is generated when the transient response is released becomes
input voltage of V
IN
.
N.B.
Diagram 1. Voltage detector 2's input voltage V
IN2
Diagram 2. Through current oscillation
V
DET1
V
DET2
V
IN1
V
IN2
R
IN
I
SS
*
V
IN1
V
IN2
R
IN
V
SS
I
SS*
GN.B.
Directions for use
GNotes on Use
02S_05XC612 02.09.12 14:15 176
XC612
Series
177
2
Test Circuits
Circuit 1.
V
IN
V
DET2
V
DET1
V
IN1
V
SS
V
IN2
V
V
R
100k
V
DF1
,V
DF2
V
HYS1
,V
HYS2
V
DF1
,V
DF2
V
HYS1
,V
HYS2
Circuit 2.
V
IN
V
DET2
V
DET1
V
IN1
I
SS
V
SS
V
IN2
I
IN2
A
A
Circuit 3.
V
IN
V
IN2
V
DET1
V
SS
V
IN1
V
DET2
V
DS
I
VDET
* A resistor is not needed if the product is CMOS output type.
XC612N Series
V
IN
V
IN2
V
DET1
V
SS
V
IN1
V
DET2
V
DS
V
DS
I
VDET
I
VDET
XC612D Series
02S_05XC612 02.09.12 14:15 177
XC612
Series
178
2
Circuit 4.
V
IN
V
DR
V
DET
Time
Time
tDLY
V
DET2
V
DET1
V
IN1
V
SS
V
IN2
100k
R
waveform
measurement
waveform
measurement
V
IN
V
IN2
V
DET1
V
SS
V
IN1
V
DET2
V
DS
V
DS
I
VDET
I
VDET
XC612E Series
02S_05XC612 02.09.12 14:15 178
Typical Performance Characteristics
3.4
3.5
3.6
3.7
3.8
3.9
-40
-20
0
20
40
60
80
3.0
3.1
3.2
3.3
3.4
3.5
-40
-20
0
20
40
60
80
0
1.0
2.0
3.0
4.0
5.0
6.0
0
2
4
6
8
10
25
Ta=80
-30
0
1.0
2.0
3.0
4.0
5.0
6.0
0
2
4
6
8
10
25
Ta=80
-30
Note : Unless otherwise stated, pull up resistance = 100k
with N-ch open drain output types.
(1) SUPPLY CURRENT vs. INPUT VOLTAGE
(2) DETECT & RELEASE VOLTAGE vs. AMBIENT TEMPERATURE
Input Voltage: V
IN2
(V)
Input Current: I
IN2
(
A)
Supply Current: Iss (
A)
Input Voltage: V
IN1
(V)
V
DR
V
DF
Ambient Temp.: Topr (
:
)
Ambient Temp.: Topr (
:
)
V
DR
V
DF
(V
IN1
10V)
(V
IN1
V
IN2
)
(V
DF1
3.6V)
(V
DF2
3.2V)
0
1
2
3
4
5
0
1
2
3
4
5
Topr = 80
25
-30
0
1
2
3
4
5
0
1
2
3
4
5
Topr = 80
25
-30
(3) OUTPUT VOLTAGE vs. INPUT VOLTAGE
(V
DF1
3.6V)
(V
DF2
3.2V)
Input Voltage: V
IN2
(V)
Output Voltage: V
DET2
(V)
Output Voltage: V
DET
1 (V)
Input Voltage: V
IN1
(V)
Detect, Release Voltage
: V
DF1
, V
DR1
(V)
Detect, Release Voltage
: V
DF2
, V
DR2
(V)
XC612
Series
179
2
02S_05XC612 02.09.12 14:15 179
XC612
Series
180
2
0
5
10
15
20
25
30
35
40
45
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
2.5V
2.0V
1.5V
V
IN
=3.5V
3.0
0
100
200
300
400
500
600
700
0
0.2
0.4
0.6
0.8
1.0
0.7V
0
5
10
15
20
25
30
35
40
45
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
DS
(V)
2.5V
2.0V
1.5V
V
IN
=3.0V
0
100
200
300
400
500
600
700
0
0.2
0.4
0.6
0.8
1.0
0.7V
(4) N-CH DRIVER OUTPUT CURRENT vs. V
DS
(V
DF2
3.2V)
(V
DF1
3.6V)
(V
DF1
3.6V)
V
DS
(V)
Output Current: I
VDET1
(mA)
Output Current: I
VET2
(mA)
Output Current: I
VET2
(
A)
V
DS
(V)
V
DS
(V)
Output Current: I
VET1
(
A)
V
IN
=0.8V
V
IN
=0.8V
(V
DF2
3.2V )
0
2
4
6
8
10
12
14
16
18
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Topr=-30
80
25
0
2
4
6
8
10
12
14
16
18
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Topr=-30
80
25
(5) N-CH DRIVER OUTPUT CURRENT vs. INPUT VOLTAGE
(V
DF2
3.2V)
(V
DF1
3.6V)
Output Current: I
VET1
(mA)
Input Voltage: V
IN1
(V)
Output Current: I
VDET2
(mA)
Input Voltage: V
IN2
(V)
V
DS
=0.5V
V
DS
=0.5V
02S_05XC612 02.09.12 14:15 180
XC612
Series
181
2
Typical Application Circuits
GWindow comparator circuit (Example covers N-channel open drain product's circuits.)
V
IN
V
OUT
V
DF1
V
DF2
V
SS
Time
Time
V
SS
V
IN1
V
OUT
V
IN
R
R
V
SS
V
SS
V
SS
V
DET1
V
IN2
V
DET2
V
IN1
V
DD
V
IN
R
R
1
R
2
V
SS
V
OUT
V
SS
V
SS
V
DET1
V
IN2
V
DET2
Notes on resistors R1 and R2's (1), (2) functions :
Detect voltage = { (R1 + R2)
R2} V
DF2
(1)
N.B. V
DF2
= detect voltage VD2
Please set-up so that
Hysteresis (V
HYS2
) = { (R1 + R2)
} V
HYS2
(2)
Note : Please ensure that input voltage 2 (V
IN2
) is less than V
IN1
+ 0.3V
V
IN1
V
DD
R
R
D
D
C
D
V
SS
V
SS
V
SS
V
DET1
V
IN2
V
DET2
Note : Delay operates at both times of release
and detect operations.
GDetect voltages above respective established voltages circuit (Example covers N-channel open drain product's circuits.)
GVoltage detect circuit with delay built-in (Example covers N-channel open drain product's circuits.)
02S_05XC612 02.09.12 14:15 181
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