TA1360AFG

2003-01-21

TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic

TA1360AFG

YCbCr/YPbPr Signal and Sync Processor for Digital TV, Progressive Scan TV and Double

Scan TV

The TA1360AFG integrates an analog component signal

(YCbCr/YPbPr) processor and sync processor in a 80-pin QFP
plastic package. The IC is ideal for digital TVs, progressive TVs,
and double scan TVs.

The luminance block and the color difference block incorporate

the high performance signal processing circuits. The sync
processor block supports 525I/60, 625I/50, 525P/60, 625P/50,
1125I/50, 1125I/60, 750P/60, (750P/50), PAL100 Hz, NTSC120 Hz,
and SVGA/60(VESA).

The TA1360AFG incorporates the I

C bus. The device can

control various functions via the bus line.

Features

Luminance Block

Black stretch circuit and DC restoration rate correction circuit

Dynamic correction circuit (gray scale correction)

SRT (LTI)

Y group delay correction (shoot balance correction)

High-bright color circuit

Color detail enhancer (CDE)

White pulse limiter (WPL)

VSM output

Color difference Block

Fresh color correction

Dynamic Y/C correction circuit

Color SRT (CTI)

Color circuit

Green stretch

Blue stretch

Text Block

OSD blending SW

ACB (only black level)

Two analog RGB inputs

Synchronization Block

Horizontal sync (15.75 k, 28.125 k, 31.5 k, 33.75 k, 37.9 k, 45 kHz)

Vertical sync (525I/P, 625I/P, 750P, 1125I/P, PAL 100 Hz/NTSC 120 Hz

2- and 3-level sync separator circuit

HD/VD input (positive and negative polarities)

Copy guard

Vertical blanking

Weight: 1.6 g (typ.)

TA1360AFG

2003-01-21

Block Diagram

DAC2

(ACB PLUSE)

H-FREQ SW2

AFC FILTER

H CURVE

CORRECTION

/
D

HORIZONTAL

PHASE

CBUS

DECODER

FREQUENCY

CLAMP

H DUTY

GND

I
N

/
D

GND

VP OUT

PbPr/YCbCr

YUV CONVERT

H CURVE

CORRECTION

SYNC

SEPA

HD IN SW

INTEGRAL

VD IN SW

RGB OUT

H C/D

HVCO

H-AFC

FBP/BLK

H-RAMP

× f

V C/D

FREQUENCY

ACB

PULSE

POLARITY

CLAMP

PULSE

EXT

V-BLK

H-BLK

V-BLK

V-CLP

DRIVE

CLAMP

BLK

CUT OFF

RGB

BRIGHTNESS

CLAMP

RGB

CONTRAST

MIXER SW/

BLUE BACK

RGB

MATRIX

CLAMP

WP BLUE

HALF TONE

/C MUTE

COLOR

G-Y

MATRIX

RELATIVE

PHASE/

AMPLITUDE

H-BPP

V-BPP

UNI-COLOR

COLOR

CLAMP

PULSE

EXT

CP/BPP

SYNC OUT

BPP

EXT

BPP

GREEN

STRETCH

TINT

Y/C LEVEL

COMP

CONVERTER

FRESH

COLOR

CLAMP

I
N

BLACK

STRETCH

BLACK PEAK

DETECT

DARK

DET

BLACK LEVEL

CORECTION

DYNAMIC

DC REST

SHARPNESS

DELAY LINE

APL

DETECT

GROUP

DELAY

CORRECTION

SRT

WPL

CLAMP

UNI-

COLOR

SUB-

CONTRAST

WPS

HALF TONE

/Y MUTE

HI-BRIGHT

COLOR

Yout-

COLOR

PEAK

DETECT

SHARPNESS

CONTROL

Y DETAIL

CONTROL

CDE

BRIGHTNESS

ABCL

AMP

VSM

MUTE

VSM AMP

HPF

OSD
AMP

CLAMP

OSD

ACL SW

DARK AREA
DET FILTER

BPH FILTER

APL FILTER

ABCL IN

COLOR
LIMITER

ANALOG
OSD G IN

ANALOG
OSD R IN

VSM OUT

ANALOG
OSD B IN

(ANALOG OSD)

I
N

/
H

S/H

B IN

LOG

RGB

)

/P-

/
B

Y/C V

RGB GND

Y/C GND

RGB V

SCL

SDA

CP OUT

SCP IN

HVCO

H-OUT

FBP IN

VP OUT

SYNC IN

VD IN

HD IN

R OUT

G OUT

B OUT

CP2

CP1

DAC2

DAC1

CP2

S/H

CP1

68 67 66

B-Y

G-Y

R-Y

LIGHT

DET

DL/

COLOR SRT

VSM FILTER

BLUE

STRETCH

CP2

DAC1

(SYNC OUT)

H-FREQ SW1 55

LIGHT AREA
DET FILTER

TA1360AFG

2003-01-21

Pin Assignment

(ANALOG OSD)

R S/H

G S/H

B S/H

RGB GND

R OUT

G OUT

B OUT

RGB V

ANALOG OSD R IN

ANALOG OSD G IN

ANALOG OSD B IN

DAC2 (ACB PULSE)

ANALOG R IN

LIGHT AREA

DET FILTER

Y2 IN

COLOR LIMITER

VSM FILTER

H-FREQ SW1

SYNC IN

VD IN

HD IN

SCP IN

CP OUT

DEF/DAC V

AFC FILTER

HVCO

H-FREQUENCY

SW2

I
N

BPH

REA

I
LT

APL

Y/C

VSM

ABC

/P-

/
B

LOG

)

FBP

/
D

GND

H-OUT

(
SYNC

OUT

)

GND

(ANALOG RGB)

COURV

CORRE

I
O

Y/C

GND

TA1360AFG

TA1360AFG

2003-01-21

Pin Functions

No.

Pin Name

Function

Interface Circuit

Input Signal/Output Signal

(analog OSD)

Switches internal RGB and OSD
input signals.

The blend ratio of internal RGB
and OSD signals can be adjusted
according to applying voltage to
pins Y

1 and Y

VSM output is muted when Y

1 or

2 pin is set to High.

2 Y

Blend ratio

Int RGB:

OSD RGB

10:0

7:3

5:5

0:10

0 to 0.5 V

: Internal

1.1 V to 1.7 V : VSM Mute

2.9 V to 9 V : OSD, VSM Mute

(analog RGB)

Switches internal RGB and
external analog RGB input.

VSM output is muted when analog
RGB is selected.

0 to 0.5 V : Internal

1.5 V to 9 V : Analog RGB, VSM

Mute

This pin is not used.

Connect to GND.

R S/H

G S/H

B S/H

S/H (sample-and-hold) pin.

In ACB Mode, connect 2.2-

µF

capacitor. In CUT-OFF Mode,
connect 0.01-

µF capacitor.

This pin is not used.

Connect to GND.

Inputs feedback signal from CRT.
(BLK level should be 0 to 3 V.)

When ACB function is not used,
connect this pin to RGB V

pin.

or RGB V

This pin is not used.

Connect to GND.

RGB GND

GND pin for text/RGB block

This pin is not used.

Connect to GND.

1 Vp-p (typ.) R

0~3 V

1 k

4
6
7

500

1 k

5 k

300

TA1360AFG

2003-01-21

No.

Pin Name

Function

Interface Circuit

Input Signal/Output Signal

R OUT

G OUT

B OUT

Outputs R/G/B signal.

Recommended output amplitude:
100 IRE

= 2.3 Vp-p

100 IRE: 2.3 Vp-p

Conditions:

UNI-COLOR

= max

SUB-CONT

= Cent

Y IN

= 0.7 Vp-p

This pin is not used.

Connect to GND.

RGB V

pin for text/RGB block.

See "Maximum Ratings" about the
supply voltage.

This pin is not used.

Connect to GND.

ANALOG OSD
R IN

ANALOG OSD
G IN

ANALOG OSD
B IN

Inputs analog OSD signal via
clamp capacitor.

100 IRE: 0.7 Vp-p (not including
sync)

This pin is not used.

Connect to GND.

DAC2
(ACB pulse)

Outputs 1-bit DAC or pulse over
ACB period.

Open-collector output.

DC or ACB PULSE

ANALOG R IN

ANALOG G IN

ANALOG B IN

Inputs analog R/G/B signal via
clamp capacitor.

100 IRE: 0.7 Vp-p (not including
sync)

L GND

GND pin for I

L block

1 k

24
25
26

1 k

500

1 k

18
19
21

1 k

12
13
14

200

100

TA1360AFG

2003-01-21

No.

Pin Name

Function

Interface Circuit

Input Signal/Output Signal

SDA

SDA pin for I

C BUS

This pin is not used.

Connect to GND.

SCL

SCL pin for I

C BUS

L V

pin for I

L block. Connects 2

V (typ.).

Supply power via zener diode
through resistor from pin 45. (See
"Application Circuit")

This pin is not used.

Connect to GND.

DAC1
(SYNC OUT)

Outputs 1-bit DAC or separated
SYNC.

Open-collector output.

DC or SYNC OUT

VP OUT

Outputs vertical pulse.

Applying current to this pin,
performs external blanking by
OR-ing with internal blanking.

Note: Changing H-position varies

VP output width. Use the
start phase only for VP
output.

VP output:

V-BLK input current: 780

µA to 1 mA

This pin is not used.

Connect to GND.

200

5 V

0 V

Start phase

500

5 k

SCL

5 k

SDA

ACK

TA1360AFG

2003-01-21

No.

Pin Name

Function

Interface Circuit

Input Signal/Output Signal

H-OUT

Horizontal output pin.
Open-collector output.

DEF/DAC GND

GND pin for DEF/DAC block

FBP IN

Inputs FBP for horizontal AFC.

Sets H-BLK width.

H CURVE
CORRECTION

Adjusts screen curve at high
voltage fluctuation. Input AC
component of high voltage
fluctuation.

When not used, connect 0.01-

µF

capacitor between this pin and
GND.

H-FREQ SW2

Switches horizontal frequency
(Switch 2).

Leave this pin open when
horizontal frequency is switched
by Bus controlling. Controlling this
pin prevails over Bus control.
(Refer to Table 1: Bus control
function.)

When this IC is used for CRT,
frequency of horizontal output (pin
37) is controlled according to
voltage of this pin. DC voltage that
is generated by dividing resistor of
DEF V

(pin 45) should be used

to control this pin.

At BUS control (horizontal
frequency) : output voltage value

28 k/15 kHz

: DC 9 V

31 kHz

: DC 6 V

33 kHz

: DC 3 V

37 k/45 kHz

: DC 0 V

At pin 22 control, horizontal
frequency and input voltage value

0 to 1.0 V

: 37 k/45 kHz

2.0 V to 4.0 V

: 33 kHz

5.0 V to 7.0 V

: 31 kHz

8.0 V to 9.0 V

: 28 k/15 kHz

HVCO

Connects ceramic oscillator for
horizontal oscillation.

Use Murata
"CSBLA503KECZF30".

This pin is not used.

Connect to GND.

5 k

1 k

30 k

4.5 V

7.5 V

1.5 V

1 k

130

6.5 V

500

20 k

max: 9 V

H-AFC threshold
: 5.3 V

BLK threshold
: 2.3 V

10 k

1 k

TA1360AFG

2003-01-21

No.

Pin Name

Function

Interface Circuit

Input Signal/Output Signal

AFC FILTER

Connects filter for detecting AFC.

DEF/DAC V

pin for DEF/DAC block.

See "Maximum Ratings" about the
supply voltage.

This pin is not used.

Connect to GND.

CP OUT

Outputs internal clamp pulse
(CP).

This pin is not used.

Connect to GND.

SCP IN

Inputs SCP from up converter.
Input signals are clamp pulse
(CP) and black peak detection
stop pulse (BPP).

2.2 V to 2.8 V : BPP

4.2 V to 9 V : CP

HD IN

Inputs horizontal sync HD signal.
Inputs positive- or
negative-polarity signals.

This pin is not used.

Connect to GND.

VD IN

Inputs vertical sync VD signal.
Inputs positive- or
negative-polarity signals.

1 k

Threshold
: 0.75 V

0 V

Threshold
: 0.75 V

0 V

5 V

0 V

200

300

30 k

VCO

1 k

Threshold
: 0.75 V

0 V

Threshold
: 0.75 V

0 V

5 k

TA1360AFG

2003-01-21

No.

Pin Name

Function

Interface Circuit

Input Signal/Output Signal

SYNC IN

Inputs Y signal with sync signal
via clamp capacitor.

White 100%: 1 V

p-p

This pin is not used.

Connect to GND.

H-FREQ SW1

Switches horizontal frequency
(Switch 1).

Leave this pin open when
horizontal frequency is switched
by Bus controlling.

Controlling this pin prevails over
Bus control. (Refer to Table 1:
Bus control function.)

When this IC is used for CRT,
connect this pin to DEF V

(pin

45) or DEF GND (pin 38). If it is
not necessary to control this pin
on CRT, connect this pin directly
to DEF VCC or DEF GND on the
PCB.

DEF V

or DEF GND

This pin is not used.

Connect to GND.

VSM FILTER

Connects VSM output filter.

Please connect 0.01-

µF capacitor

between this pin and GND.

COLOR LIMITER

Connects filter for detecting color
limit.

This pin is not used.

Connect to GND.

1 k

200

5 k

TA1360AFG

2003-01-21

No.

Pin Name

Function

Interface Circuit

Input Signal/Output Signal

Inputs C

signal via clamp

capacitor.

700 mVp-p700 mVp-p at 100% color
bar for C

Inputs C

signal via clamp

capacitor.

700 mVp-p at 100% color bar for
C

Y2 IN

Inputs Y2 signal via clamp
capacitor.

1 Vp-p (including sync) at 100%
color bar

This pin is not used.

Connect to GND.

LIGHT AREA
DET FILTER

Connects filter for detecting light
area.

Voltage of this pin controls
dynamic

circuit gain for light

area.

Y/C GND

GND pin for Y/C block

Inputs C

signal via clamp

capacitor.

700 mVp-p700 mVp-p at 100% color
bar for C

Inputs C

signal via clamp

capacitor.

700 mVp-p at 100% color bar for
C

Y1 IN

Inputs Y1 signal via clamp
capacitor.

1 Vp-p (including sync) at 100%
color bar

This pin is not used.

Connect to GND.

1 k

5 k

66
67
68

100

5 k

1 k

5 k

60
61
63

TA1360AFG

2003-01-21

No.

Pin Name

Function

Interface Circuit

Input Signal/Output Signal

BPH FILTER

Connects filter for detecting black
peak.

Voltage of this pin controls black
stretch gain.

Leaving Y open and setting the
test circuit SW 2

= C enable to

monitor H/V-BPP
(black-stretch-stop pulse) width.

DARK AREA DET
FILTER

Connects filter for detecting dark
area.

Voltage of this pin controls
dynamic

circuit gain for dark

area.

This pin is not used.

Connect to GND.

APL FILTER

Connects filter for correcting DC
restoration rate.

Leaving this pin open enables to
monitor Y signal after black
stretch and dynamic

Y/C V

pin for Y/C block.

See "Maximum Ratings" about the
supply voltage.

This pin is not used.

Connect to GND.

VSM OUT

Outputs Y signal for VSM that
passed through HPF circuit (first
differential circuit).

Output signals are muted
according to pins 1, 2, and 80.

See pin 57.

ABCL IN

Inputs ABL and ACL signals.

Sets gain and start point of ABL
and dynamic ABL signal
according to bus controlling.

200

100

5 k

1 k

30 k

5 k

1 k

40 k

1 k

TA1360AFG

2003-01-21

Bus Control Map

Write Data

Slave Address: 88H

Sub-Add

D7 D6 D5 D4 D3 D2 D1 D0 Preset

00 H-FREQ1

H-DUTY

YUV-SW

DAC1

DAC2

SYNC-SW

H-FREQ2

1000

0000

01 HORIZONTAL

POSITION

CLP-PHS

1000

0000

02 ACB-MODE

SCP-SW

HBP-PHS1

SYNC

SEP-LEVEL TEST 1000

0000

03 V-BLK

PHASE VERTICAL

FREQUENCY

1000

0000

COMPRESSION-BLK PHASE-1

COMPRESSION-BLK PHASE-2

1000

0000

05 P-MODE1

UNI-COLOR

1000

0000

06 BRIGHTNESS

1000

0000

07 OSD-ACL

COLOR

1000

0000

08 TINT

HBP-PHS2

1000

0000

09 PICTURE

SHARPNESS

BLS

1000

0000

0A RGB

BRIGHTNESS

DCRR-SW

1000

0000

HI BRT

RGB CONTRAST

1000

0000

0C SUB

CONTRAST WPS

YUV

MODE

Y-OUT

1000 0000

0D DRIVE

GAIN1 DR-R

1000

0000

0E DRIVE

GAIN2

DR-B/G

1000

0000

R CUT OFF

1000

0000

G CUT OFF

1000

0000

11 B

CUT

OFF

1000

0000

12 R-Y/B-Y

GAIN

R-Y/B-Y

PHASE

1000

0000

13 G-Y/B-Y

GAIN

G-Y/B-Y

PHASE

1000

0000

COLOR SRT TRAN

C FREQ

GREEN STRETCH

COLOR

CLT

1000

0000

C.D.E.

Y/C GAIN COMP

BL STRETCH GAIN

FLESH

H-SHIFT

1000

0000

VSM PHASE

VSM GAIN

APACON PEAK FREQ 1000

0000

DC REST POINT

DC REST RATE

DC REST LIMIT

1000

0000

BLACK STRETCH POINT

APL VS BSP

B.L.C.

B.D.L

BS-AREA

1000

0000

19 SRT-GAIN

WPL-LEVEL

1000

0000

D-ABL POINT

D-ABL GAIN

BL STRETCH POINT

P-MODE2

1000

0000

ABL POINT

ABL GAIN

RGB OUT MODE

1000

0000

1C DYNC

GAIN

BS-CHAR1

STATIC

GAIN-1

STATIC

GAIN-2 1000

0000

1D OSD

BRIGHT

OSD

CONTRAST

Y/C-DL1

DYNC

AREA

1000

0000

Y DETAIL CONTROL

BS-CHAR2

WP BLUE POINT

1000 0000

Y GROUP DELAY CORRECTION

Y/C-DL2

WP BLUE GAIN

1000

0000

Read Data

Slave Address: 89H

D7 D6 D5 D4 D3 D2 D1 D0

0 POR

IK-IN

RGB-OUT

YUV-IN

H-OUT

VP-OUT

RGB-IN

SYNC-IN

TA1360AFG

2003-01-21

Bus Control Features

Write Mode

Resister Name

Description

Preset Value

H-FREQ1/2

Switches horizontal oscillation frequency. (See the appendix 1)

33.75 kHz

H-DUTY

Switches horizontal output duty.

0: 41% 1: 47%

41%

YUV-SW

Switches YUV input.

0: INPUT-1 (Y1/C

) 1: INPUT-2 (Y2/C

)

INPUT-1

DAC 1

Switches DAC controlling output.

0: OPEN (high) 1: ON (low)

Controls 1-bit DAC of open-collector when TEST is 00.

Outputs H/C-SYNC from pin 34 when TEST is 01.

OPEN

DAC 2

Switches DAC controlling output.

0: ON (low), 1: OPEN (high)

Controls 1-bit DAC of open-collector when TEST is 00.

Outputs ACB reference pulse from pin 23 when TEST is 01.

SYNC-SW

Switches sync input.

0: Selects HD/VD input. 1: Selects SYNC input.

HD/VD

HORIZONTAL POSITION

Adjusts horizontal picture position (phase).

0000000:

12.5% 1111111:

12.5%

Note: VP output width (pin 35) varies with a change of horizontal position.

CENTER

CLP-PHS

Switches clamp pulse phase.

0: 0.7-

s (2.5%) width, 1.1-

s (3.8%) delay from HD stop phase.

1: 0.7-

s (2.4%) width, 0.2-

s (0.7%) delay from HD stop phase

when no signal, 0.8-

s (2.7%) width that is 1.2-

s (4.2%) delay from FBP start

phase.

Also switches CP phase of CP-OUT (pin 47).

1.1-

s delay

ACB MODE

Sets ACB mode; Sets converged reference level.

00: ACB OFF (cutoff BUS control), 01: ACB ON (5 IRE),

10: ACB ON (10 IRE) 11: ACB ON (20 IRE)

ACB ON

(10 IRE)

SCP-SW

SCP (sand castle pulse) Switches modes.

0: Internal Mode 1: External input Mode

Internal Mode

HBP-PHS1/2

Switches phase of black-stretch-detection stop pulse.

HBP-PHS1

0 and HBP-PHS2

0: FBP

HBP-PHS1

0 and HBP-PHS2

1: FBP

HBP-PHS1

1 and HBP-PHS2

0: FBP

13%

HBP-PHS1

1 and HBP-PHS2

1: FBP

18%

Leaving Y open and setting the test circuit SW2 to C enable to monitor H/V-BPP
(black-stretch-detection stop pulse) width through pin 70.

SYNC SEP-LEVEL

Switches Sync SEP-level.

00: 16% 01: 24% 10: 32% 11: 40% (At 1125I/60)

16%

TEST

Test Mode:

Controls 1-bit DAC of open-collector when TEST is 00.

Outputs H/C-SYNC from pin 34, and ACB reference pulse from pin 23 when TEST
is 01.

Do not set TEST to 10/11 for that is shipment TEST Mode.

TA1360AFG

2003-01-21

Resister Name

Description

Preset Value

V-BLK PHASE

Switches vertical BLK stop phase.

00000: 16 H~ 11110: 46 H (1 H/STEP)

11111: Internal H/V-BLK OFF

Please set ACB Mode to OFF when internal H/V-BLK is OFF (11111).

32 H

V-FREQUENCY

Vertical free-run frequency: Sets V pull-in range. (See Appendix 2.)

1281 H

COMPRESSION-BLK
PHASE-1/2

Compression BLK phase: Sets BLK for upper and lower parts of screen. (See
Appendix 3.)

CENTER, OFF

P-MODE1/2

Picture Mode: Sets picture mute, halftone, blue background, and Y mute. (See
Appendix 4.)

P-MUTE 1

UNI-COLOR

Unicolor adjustment:

0000000:

16dB~ 1111111: 0dB

min

BRIGHTNESS

Brightness adjustment:

00000000:

40 IRE 11111111:

40 IRE

CENTER

OSD-ACL

OSD-ACL;

0: OFF 1: ON

COLOR

Color adjustment:

0000000: COLOR MUTE,

0000001:

20dB or more 1111111:

4dB

C-MUTE

TINT

Tint adjustment:

0000000:

32 deg~ 1111111:

32 deg

0 deg

PICTURE-SHARPNESS

Sharpness adjustment:

0000000:

10dB or more 1000000:

10dB

1111111:

17.5dB (at peak FREQ)

CENTER

BLS

Blue stretch

correction: B-axis correction

0: OFF 1: ON

OFF

RGB-BRIGHTNESS

RGB brightness:

0000000;

20 IRE~ 1111111;

20 IRE

CENTER

DCRR-SW

Switches DC restoration rate.

0: 100% or higher 1: 100%or lower

100% or higher

HI BRT

High-bright color:

0: OFF 1: ON

RGB-CONTRAST

RGB contrast:

0000000:

16.5dB 1111111: 0dB

min

SUB-CONTRAST

Sub-contrast:

00000:

3.3dB 11111:

2.5dB

CENTER

WPS

WPS level:

0: 110 IRE 1: 130 IRE

110 IRE

YUV MODE

Y/color-difference input Mode:

0: Y/Cb/Cr, 1: Y/Pb/Pr

(Remarks) Y/Cb/Cr: ITU-R BT 601

Y/Pb/Pr: ITU-R BT 709 (1125/60/2:1)

Y/Cb/Cr

Y-out

-out gamma control:

0: OFF 1: ON

OFF

DRIVE GAIN1/2

Drive gain 1/2;

0000000:

5dB 1111111:

3dB

CENTER

DR-R
DR-B/G

Switches RGB drive gain base. (See Appendix 5.)

TA1360AFG

2003-01-21

Resister Name

Description

Preset Value

R/G/B CUT OFF

R/G/B cutoff:

1) At ACB-OFF RGB-OUT

00000000: 1.9 V 11111111: 2.9 V

2) At ACB-ON SENS-IN

00000000: 0.5 Vp-p 11111111: 1.5 Vp-p

CENTER

R-Y/B-Y GAIN

Switches R-Y/B-Y relative amplitude:

0000: min (0.45) 1111: max (0.9)

CENTER

R-Y/B-Y PHASE

Switches R-Y/B-Y relative phase:

0000: min (90 deg) 1111: max (111.5 deg)

min

G-Y/B-Y GAIN

Switches G-Y/B-Y relative amplitude:

0000: min (0.25) 1111: max (0.48)

CENTER

G-Y/B-Y PHASE

Switches G-Y/B-Y relative phase:

0000: min (232 deg) 1111: max (254 deg)

min

COLOR SRT TRAN

Color SRT transient: Color-difference transient improvement

00: C-SRT OFF~ 11: max

CENTER

C FREQ

Color SRT peak frequency:

0: 4.5 MHz 1: 5.8 MHz

4.5 MHz

GREEN STRETCH

Green stretch:

00: OFF~ 11: max (

3dB)

OFF

COLOR

Color

correction point

00: OFF, 01: 0.23 Vp-p, 10: 0.40 Vp-p, 11: 0.58 Vp-p

OFF

CLT

Color limiter level:

0: 1.65 Vp-p, 1: 2 Vp-p

1.65 Vp-p

CDE

Color detail enhancer:

00: min 11: max

CENTER

Y/C GAIN COMP

Dynamic Y/C compensation: Operated when luminance level is made up
according to dynamic Y

00: OFF~ 11: max

OFF

BL STRETCH GAIN

Blue stretch gain: B-axis correction

00: OFF 11: max (

6.4dB)

OFF

FLESH

Flesh color: Skin tone color correction

0: OFF 1: ON (Lead-in angle:

33.7 deg)

OFF

H-SHIFT

Shifts a center of horizontal picture position (phase):

0: OFF 1: ONFBP shifts 6.7% against HD

OFF

VSM-PHASE

VSM phase:

000:

37.5 ns 101: normal 111:

15 ns

CENTER

VSM GAIN

VSM gain:

000: OFF 001: 0 dB~ 111:

16dB (VSM gain is limitted 1.4 Vp-p)

OFF

APACON PEAK f

APACON peak frequency:

00: 13.5 MHz 01: 9.5 MHz 10: 7.2 MHz 11: 4.5 MHz

13.5 MHz

DC REST POINT

DC restoration rate correction point:

000: 0% 111: 49%

CENTER

DC REST RATE

DC restoration correction rate:

000: 100% 111: 135% (70%)

min

DC REST LIMIT

DC restoration rate correction limit point:

00: 67% 01: 77 10: 80% 11: 80%

min

TA1360AFG

2003-01-21

Resister Name

Description

Preset Value

BLACK STRETCH POINT

Black stretch start point 1:

000: OFF 001: 25 IRE~ 111: 55 IRE

CENTER

APL VS BSP

Black stretch start point 2:

00: 0 IRE 11: 46 IRE up (at APL 100%)

0 IRE

B.L.C

Black level automatic correction: Up to 6.5 IRE. (Black stretch takes priority.)

0: OFF 1: ON

OFF

B.D.L.

Switches black detection level:

0: 3 IRE 1: 0 IRE

3 IRE

BS-AREA

Black stretch area reinforcement:

0: ON 1: OFF

SRT-GAIN

SRT gain; Y transient improvement (LTI)

00000: min 11111: max

CENTER

WPL-LEVEL

White letters improvement amplitude;

000: min (21 IRE) ~ 110: max (102 IRE) 111: OFF

min

D-ABL POINT

Dynamic ABL detection voltage

00: min 11: max

CENTER

D-ABL GAIN

Dynamic ABL sensitivity

00: min 11: max

min

BL STRETCH POINT

Blue stretch point; B-axis correction

00: min (28 IRE) 11: max (60 IRE)

min

ABL POINT

ABL detection voltage

000: min 111: max

CENTER

ABL GAIN

ABL sensitivity

000: min 111: max

min

RGB-OUT MODE

RGB output mode; RGB output mode SW for test and adjustment

00: Normal 01: R only 10: G only 11: B only

Normal

DYNC

GAIN

Dynamic Y

gain vs dark area; dynamic

-correction according to dark area.

00:min~
11: max (Maximum gain is

6dB included Static Y

gain for dark area.)

CENTER

BS-CHAR1/2

Black stretch characteristic swich

BS-CHAR1

0 and BS-CHAR2

0: OFF

BS-CHAR1

0 and BS-CHAR2

1: min

BS-CHAR1

1 and BS-CHAR2

0: mid

BS-CHAR1

1 and BS-CHAR2

1: max

OFF

STATIC

GAIN-1

Static Y

dark area gain;

correction for dark area

000: OFF 001: min (

5dB) ~ 11: max (

2.4dB)

Note: When STATIC

GAIN-1 is 000(OFF), set DYNC

GAIN to min (00),

STATIC

GAIN-2 to OFF (11), and DYNC

AREA to min (000).

OFF

STATIC

GAIN-2

Static Y

light area gain;

correction for light area

00: max (

8.8dB)~ 11: OFF

When 00~10 is set, light area static Y

and light dynamic Y

according to light area

is operated.

max

OSD BRIGHT

OSD brightness:

00: 5 IRE 01: 0 IRE 10:

5 IRE 11:

10 IRE

5 IRE

OSD-CONTRAST

OSD contrast:

00: min (

9.5dB) 11: max (0dB)

min

TA1360AFG

2003-01-21

Resister Name

Description

Preset Value

Y/C DL1/2

Adjusts Y/C phase; adjusts the phase Y before passing through matrix circuit.

Y/C DL2

0 and Y/C DL1

10 ns, Y/C DL2

0 and Y/C DL1

5 ns

Y/C DL2

1 and Y/C DL1

0: 0 ns, Y/C DL2

1 and Y/C DL1

5 ns

10 ns

DYNC

AREA

Dynamic

dark area detection sensitivity; switches detection sensitivity of dynamic

of dark area.

000: min~ 111: max

min

Y DETAIL CONTROL

Controls Y detail; corrects sharpness of 5.0-MHz peak frequency.

0000:min (trap) 1111: max

6dB

CENTER

WP BLUE POINT

White peak blue point;

000: OFF 001: min (42 IRE) ~ 111: max (106 IRE)

OFF

Y-GROUP DELAY
CORRECTION

Y group delay correction; shoot balance correction.

0000: Pre-shoot gain is lowered. (Overshoot gain is raised.)

1111: Overshoot gain is lowered. (Pre-shoot gain is raised.)

CENTER

WP BLUE GAIN

White peak blue gain.

000: min (

3dB) 111: max (

10dB)

min

TA1360AFG

2003-01-21

Appendix 1: Horizontal Frequency

Pin Voltages (V)

Bus Data

Pin 55

Pin 41

00-D0

00-D7

00-D6

H-Frequency (kHz)

DEF V

(8.0~9.0)

0 0 0

28.125

6.0 (5.0~7.0)

31.5

3.0 (2.0~4.0)

33.75

DEF GND

(0~1.0)

DEF GND

(0~1.0)

0 1 1

37.9

DEF V

(8.0~9.0)

1 0 0

15.75

6.0 (5.0~7.0)

31.5

3.0 (2.0~4.0)

33.75

DEF V

(8.0~9.0)

DEF GND

(0~1.0)

1 1 1

Note 1: Controlling pins prevails over BUS control. When the TA1360F is used for CRT, control horizontal oscillation

frequency by pins 41 and 55. (See the pin descriptions for details.)

Note 2: Horizontal output frequency may not be switched at once but may takes two steps if switching pins 41 and

55 is controlled at the same time. Switching horizontal output frequency may cause deterioration of the
horizontal transistor. Thus, be sure to take account of applications, included software.

Appendix 2; Vertical Frequency

V-BPP

Data V

Pull-in

Range

Start Phase

Stop Phase

Example of Format/V (H)-Frequency

000

48~1281 H

1100 H

1125P/30 Hz (33.75 kHz)

001 48~849

730

750P/60 Hz (45 kHz)

(750P/50Hz(37.5 kHz))

010 48~725

600

625P/50 Hz (31.5 kHz)

SVGA/60 Hz(37.9 kHz)

011 48~660

545

1125I/50 Hz (28.125 kHz)

1125I/60 Hz (33.75 kHz)

100

48~613 H

500 H

525P/60 Hz (31.5 kHz)

101 48~363

290

PAL/SECAM/50 Hz (15.625 kHz),

100 Hz (31.5 kHz)

110 48~307

240

V-BLK P.

(C.BLK P.)

20 H

NTSC/60 Hz (15.734 kHz),

120 Hz (31.5 kHz)

111 VP-OUT

TA1360AFG

2003-01-21

Appendix 3; Compression-BLK Phase

V-Frequency Phase-1

(start

phase)

* Phase-2

(stop

phase)

000

1088 H~1116 H

001 720

H~748

010 592

H~620

011 528

H~556

100 488

H~516

101 280

H~308

110 224

H~252

50~78 H

(0000: C-BLK2 OFF)

111 C-BLK

OFF

*: C-BLK1

1111: C-BLK1 OFF

Appendix 4; P-Mode

05-D7 1A-D1 1A-D0 MODE

Description

0 0 0

NORMAL

P-Mute and halftone the main signal by pin Y

Insert analog RGB-IN by Ys3, and OSD-IN by Ys1/Ys2.

Analog RGB-IN

P-Mute

0 0 1 Y-MUTE

Full-screen-mute process is executed on Y of main signal by BUS.

Insert analog RGB-IN by Ys3, and OSD-IN by Ys1/Ys2.

Analog RGB-IN

P-Mute

0 1 0 Y

Full-screen-halftone process is executed on main signal by BUS.

Insert P-Mute by pin Y

, and analog RGB-IN by Ys3.

Ys1/Ys2 blends OSD-IN and main halftone signal.

Analog RGB-IN

P-Mute

0 1 1 BB

Blue background process is executed on main signal by BUS.

Insert P-Mute by pin Y

, analog RGB-IN by Ys3, and OSD-IN by Ys1/Ys2

Analog RGB-IN

P-Mute

1 0 0

P-MUTE

Full-screen-mute process is executed on main signal by BUS.

Insert analog RGB-IN by Ys3, and OSD-IN by Ys1/Ys2.

Analog RGB-IN

P-Mute

1 0 1 Y

Full-screen-halftone process is executed on main signal by BUS.

Insert P-Mute by pin Y

, and analog RGB-IN by Ys3.

Ys1/Ys2 blends OSD-IN and main halftone signal

P-Mute

Analog RGB-IN

1 1 0

P-MUTE

Full-screen-mute process is executed on main signal and analog RGB-IN by
BUS.

Insert OSD-IN by Ys1/Ys2.

P-Mute

Analog RGB-IN

1 1 1

NORMAL

P-Mute and halftone process is executed on the main signal by pin Y

Analog RGB-IN is inserted by Ys3, and OSD-IN by Ys1/Ys2.

P-Mute

Analog RGB-IN

Output priority; (000)~(100): Main signal

P-MUTE

RGB-IN

OSD-IN

(101)~(111): Main signal

RGB-IN

P-MUTE

OSD-IN

TA1360AFG

2003-01-21

Appendix 5; DR-R, DR-B/G

DR-R

DR-B/G

Reference Axis

Drive Gain1

Drive Gain2

0 0

0 1

1 0

1 1

Read Function

Signal Function

POR

Power-on reset:

0: RESISTER PRESET 1: Normal

After power on, 0 is returned at first read; 1, at second and subsequent reads.

IK-IN

Detects IK input; detects input through pin 8.

0: NG (no signal) 1: OK (signal detected)

RGB-OUT

Detects RGB-OUT self-check; detects output of pins 12, 13, 14.

0: NG (no signal) 1: OK (signal detected)

Detects signal when all three outputs hsve signals. Small signals are not detected.

YUV-IN

Detects YUV-IN self-check; detects input of pins 60, 61 63 or pins 66, 67, 68.

0: NG (no signal) 1: OK (signal detected)

Detects signal when all three inputs are AC signals. Small signals or signals like DC voltage are not
detected.

H-OUT

Detects H-OUT self-check; detects output of pin 37.

0: NG (no signal) 1: OK (signal detected)

VP-OUT

Detects VP-OUT self-check; detects output of pin 35.

0: NG (no signal) 1: OK (signal detected)

RGB-IN

Detects RGB-IN self-check; detects input of pins 24, 25, 26.

0: NG (no signal) 1: OK (signal detected)

Detects signal when all three inputs are AC signals. Small signals or signals like DC voltage are not
detected.

SYNC-IN

Detects SYNC-IN self-check; detects input of pin 53.

0: NG (no signal), 1: OK (signal detected)

TA1360AFG

2003-01-21

Data Transmit Format 1

Data Transmit Format 2

Data Receive Format

To receive data, the master transmitter changes to the receiver immediately after the first acknowledgement.

The slave receiver changes to the transmitter.

The stop condition is always created by the master.
Details are provided in the Philips I

C specifications.

Optional Data Transmit Format

In this way, sub addresses are automatically incremented from the specified sub address and data are set.
Purchase of TOSHIBA I

C components conveys a license under the Philips I

C Patent Rights to use these

components in an I

C system, provided that the system conforms to the I

C Standard Specification as defined by

Philips.

Slave address

0 A

Transmit data 1

Sub address

Transmit data n

Sub address

A P

Slave address

1 A

Receive data 2

Transmit data 1

A P

7 bit

MSB

8 bit

MSB

Slave address

Transmit data n

Transmit data 1

A P

7 bit

MSB

8 bit

MSB

Sub address

7 bit

MSB

A 1

8 bit

MSB

Slave address

0 A

Transmit data

Sub address

A P

7 bit

MSB

S: Start condition

8 bit

MSB

A: Acknowledgement

9 bit

MSB

P: Stop condition

TA1360AFG

2003-01-21

Maximum Ratings

(Ta

=
=
=
=

25°C)

Characteristics Symbol Rating Unit

Supply voltage

CCmax

12 V

Input pin signal voltage

inmax

Vp-p

Power dissipation

(Note 3)

2604

Power dissipation reduction rate
depending on temperature

ja 20.8

mW/°C

Operating temperature

opr

20 to 65

20 to 70

°C

Storage temperature

stg

55 to 150

°C

min 8.7 8.5

typ. 9.0 8.8

Supply voltage (pins 16, 45 and 75)

max 9.3 9.1

Note 3: See the following Figure A. (With device mounted on a PCB whose dimensions are 114.3 mm

76.2 mm

1.6 mm and whose surface is 20% copper. Mount the device on a PCB of at least these dimensions and
whose surface is at least 20% copper.)
When using in

25 to 70°C of operating temperature, set the IC's power supply voltage (pins 16, 45, 75) to

8.8 V (

0.3 V).

When designing a set, make sure that the IC can radiate heat because the TA1360AFG has low thermal
capacity. Note that the power dissipation varies greatly according to conditions of a board.

Figure A Power Dissipation Reduction Curve

2604

150

25 65

1771

o
w

e
r

di

ssi

pati

on P

(mW

)

Ambient temperature Ta (°C)

1667

TA1360AFG

2003-01-21

Note 4: Power supply sequence

At power-on, power should be supplied to the power supply pins according to the following sequence:

1. Pin 31 (I

L VDD)

2. Pin 45 (DEF/DAC V

)

3. Pins 16 and 75 (YC V

/RGB V

)

Supply power to pin 37 via zener diode through resistor from pin 45. (See "Application Circuit".)
BUS preset value is become undefined and caused malfunction of the IC unless supplying power to all
supply pins or follow the power supply sequence described above. When the frequency of horizontal output
(pin 37) became undefined, horizontal transistor may be damaged. When the TA1360F is used for CRT,
control horizontal oscillation frequency by pins 41 and 55.

Figure B

Timing chart that indicates the timing from power-on

till horizontal output. (At Ta

=
=
=
=

25 C

°
°
°
°

)

L V

Logic operation 1.3 V (typ.)

POR release voltage (BUS operation) 4.6 V (typ.)

Horizontal output 6.0 V (typ.)

V DEF/DAC

TA1360AFG

2003-01-21

Operating Conditions

Characteristics Description

Min

Typ.

Max

Unit

opr

20 to 65°C

(Note 5)

8.7

9.0

9.3

Pin 16, 45, 75

opr

20 to 70°C

(Note 5)

8.5

8.8

9.1

Supply voltage (V

)

1.8 2.0 2.2

Y input level

Pins 63, 68: 100% color bar, including sync (Picture
period amplitude, 0.7 Vp-p)

1.0

Color-difference input level

Pins 60, 61 66, 67: 100% color bar, not including sync

0.7

Vp-p

HD/VD input level

Pins 50, 52

2.0

5.0

SYNC input level

Pin 53: 100% color bar, including sync

0.9

1.0

1.1

Vp-p

CP 4.2

5.0

SCP input level

Pin 49

BPP

2.2 2.5 2.8

At 28 k/31 k/33 k/37 kHz

1.0

Pin 55

At 15 k/31 k/33 k/45 kHz

8.0

28.125 kHz or 15.75 kHz

8.0

31.5

kHz

5.0 6.0 7.0

33.75

kHz

2.0 3.0 4.0

Horizontal frequency switching
voltage

Pin 41

37.9 kHz or 45 kHz

1.0

H-AFC 6.5

7.0

FBP input level

Pin 39

H-BLK

3.0 3.5 4.0

FBP input width

Pin 39

0.16

0.3 H

H-OUT input current

Pin 37

9.0 15.0

DAC input current

Pins 23, 34

0.3 1.0

SCL/SDA pull-up voltage

Pins 28, 30

3.3

5.0

SDA input current

Pin 28

2 mA

Analog RGB input level

Pins 24, 25, 26: White 100%

0.7

Analog OSD input level

Pins 18, 19, 21: White 100%

0.7

Vp-p

3 switching voltage

Pin 2

1.5

5.0

OSD 2.9

5.0

1/2 switching voltage

Pins 1, 80

VSM

MUTE

1.1 1.5 1.7

BLK 7.0

P-MUTE

2.7 3.5 4.0

switching voltage

Pin 79

HALF

TONE

1.2 1.5 1.8

External V-BLK input current

Pin 35

0.78

1 mA

Note 5: See "Maximum Ratings" about T

opr

Electrical Characteristics

(

unless otherwise specified,

=
=
=
=

9 V/2 V, Ta

=
=
=
=

25°C)

Current Dissipation

Pin Name

Symbol

Test

Circuit

Min Typ. Max Unit

DEF/DAC V

(9 V)

CC1

19.2 24.0 28.2

RGB V

(9 V)

CC2

48.8 61.0 67.8

L V

(2 V)

CC3

21.3 25.0 29.4

Y/C V

(9 V)

CC4

36.8 46.0 51.1

TA1360AFG

2003-01-21

Pin Voltage

Test Condition

(1) BUS

Preset

(2) SW71

B, SW70

B, SW68

C, SW67

B, SW66

B, SW64

B, SW63

B, SW60 to 61

SW53

B, SW44

ON, SW40

B, SW39

A, SW37

A, SW24 to 26

A, SW21

A, SW18~19

SW77

OFF, SW74

Pin No.

Pin Name

Symbol

Test

Circuit

Min Typ. Max Unit

1 Y

2 V

0.1 0.2

2 Y

3 V

0.1 0.2

4 R

S/H

4.2 5.2 6.2

6 G

S/H

4.2 5.2 6.2

7 B

S/H

4.2 5.2 6.2

ANALOG OSD R IN

3.65 3.95 4.25

19 ANALOG

OSD

3.65 3.95 4.25

ANALOG OSD B IN

3.65 3.95 4.25

24 ANALOG

3.65 3.95 4.25

25 ANALOG

3.65 3.95 4.25

ANALOG B IN

3.65 3.95 4.25

40 H

CURVE

CORRECTION

2.2 2.5 2.8

42 HVCO

4.4 5.0 5.6

44 AFC

FILTER

5.4 6.2 7.0

49 CP

0 0.3

50 HD

0 0.3

52 VD

0 0.3

53 SYNC

1.8 2.1 2.4

57 VSM

FILTER

7.5 7.7 7.9

58 COLOR

LIMITER

6.65 6.9 7.15

60 Cr/Pr2

4.7 5.0 5.3

61 Cb/Pb2

4.7 5.0 5.3

63 Y2

4.7 5.0 5.3

LIGHT AREA DET FILTER

0.09 0.15

66 Cr/Pr1

4.7 5.0 5.3

67 Cb/Pb1

4.7 5.0 5.3

68 Y1

4.7 5.0 5.3

70 BPH

FILTER

5.5 5.8 6.1

DARK AREA DET FILTER

0.09 0.15

74 APL

FILTER

4.8 5.0 5.2

77 VSM

OUT

4.1 4.3 4.5

78 ABCL

6.1 6.35 6.6

79 Y

0.1 0.2

80 Y

1 V

0.1 0.2

TA1360AFG

2003-01-21

Picture Quality (Sharpness) Block

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

Y input dynamic range

0.7 1.0 1.5 Vp-p

15 10 15

Black detection level shift

(Note P01)

35 45 55

Black stretch amp maximum gain

(Note

P02)

2.4 2.8 3.2 dB

BST1

20 25 35

Black stretch start point 1

BST2

(Note P03)

50 55 60

IRE

BS1

0 5 10

Black stretch start point 2

BS2

(Note P04)

14 21 30

IRE

BSC1

26 28 30

BSC2

BSC3

26 28 30

BSC4

5.5

BSC5

26 28 30

Black stretch characteristic switch

BSC6

(Note P05)

3.5

0.5

IRE

Black stretch area reinforcement
current

IBSA

(Note

P06)

13 18 23

80 120 160

240 280 320

D.ABL detection voltage

(Note P07)

380 420 460

DAMIN

0.01 0.02

D.ABL sensitivity

DAMAX

(Note P08)

0.25 0.28 0.31

V/V

Black level correction

BLC

(Note

P09)

4.5 6.5 8.5 IRE

Dark area Y

correction point

DGP

(Note

P10)

25 28 33 IRE

Dark area dynamic Y

gain

DDGMAX

(Note

P11)

5.5 6 6.5 dB

DSGMIN

6.5

Dark area static Y

gain

DSGMAX

(Note P12)

2 2.4 2.6

Light area Y

correction point

LPG

(Note

P13)

64 74 80 IRE

Light area dynamic Y

gain

GLDG

(Note

P14)

1.1 1.7 2.3 dB

LSGMIN

0.3 0.6 0.9

Light area static Y

gain

LSGMAX

(Note P15)

1.4 1.7 2.3

DAMIN

0.25 0.3 0.37

DACEN

0.88 0.98 1.08

Dark area detection sensitivity

DAMAX

(Note P16)

0.95 1.05 1.15

ADT

100

0.9 1.1 1.2

ADT

135

1.2 1.35 1.5

DC restoration rate

ADT

(Note P17)

0.55 0.70 0.85

times

DT0

5 0 5

DC restoration point

DT1

(Note P18)

47 49 55

DTL60

64 67 70

DTL75

74 77 80

DTL87

74 80 82

DC restoration limit

DTL100

(Note P19)

74 80 82

TA1360AFG

2003-01-21

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

AP00

10.5 13.5 17

AP01

7 9.5 12

AP10

5 7.2 7.8

Sharpness control peak frequency

AP11

3.5 4.5 6.3

MHz

DC fluctuation at switching sharpness
control peak frequency

VRDC

(Note P20)

0.01 0.02 V

MAX00

15 17.5 19

MIN00

0.6 2.5

MAX01

15 17.5 19

MIN01

0.3 2.5

MAX10

15 17.5 19

MIN10

2.5 1.5

MAX11

15 17.5 19

Sharpness control range

MIN11

(Note P21)

5 0

CEN00

7 10 13

CEN01

7 10 13

CEN10

7 10 13

Sharpness control center
characteristic

CEN11

(Note P22)

7 10 13

SRT00

0.9 1.6 2.7

SRT01

3.5 4.8 7.1

SRT10

6.7 8.5 11.3

2T pulse response SRT control

SRT11

(Note P23)

11.5 12.5 15.5

VSM peak frequency

VSM

19.5

25.5

MHz

V000

V001

1.2

0.4

V010

3.7 4.6 5.5

V011

7.1 8.2 9.3

V100

8.9 10.5 12.1

V101

11.4 12.6 13.8

V110

13.5 14.4 15.3

VSM gain

V111

(Note P24)

14.8 15.7 16.6

SR1

0.62 0.78 0.85

SR2

0.62 0.78 0.85

VSM mute threshold voltage

SR580

Pins 1, 2, 80

0.62 0.78 0.85

0.55 0.66 0.75

VSM limit

(Note P25)

0.55 0.66 0.75

Vp-p

Y input to R output delay time

110 125 140 ns

YDLA

3 5 10

YDLB

7 10 15

Y delay time switch

YDLC

(Note P26)

10 15 25

AMIN

2.5

BMIN

2.5 3 3.5

AMAX

1 1.7 2.4

Y group delay correction

BMAX

(Note P27)

TA1360AFG

2003-01-21

Color Difference Block 1: YUV input and matrix

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

0.7 0.9 1.0

Color difference input dynamic range

0.7 0.9 1.0

Vp-p

RMAX

25 29 33

RMIN

BMAX

27 31 35

Color difference tint control
characteristic

BMIN

B00

3.6 4.5 5.4

B01

4.6 5.8 7.0

R00

3.6 4.5 5.4

Color SRT peak frequency

R01

4.6 5.8 7.0

MHz

B00CEN

1.5 2.8 4.1

B00MAX

2.9 4.2 5.5

B01CEN

2.0 3.3 4.6

B01MAX

3.5 4.8 6.1

R00CEN

3.4 4.7 6.0

R00MAX

5.4 6.7 7.0

R01CEN

3.1 4.4 5.7

Color SRT gain

R01MAX

(Note S01)

5.2 6.5 7.8

Cb1 input to B output delay time

130 155 185 ns

Cr1 input to R output delay time

130 155 185 ns

BDY1

1.8 2.25 2.7

BDY2

1.65

1.2

0.75

RDY1

1.8 2.25 2.7

Dynamic Y/C compensation

RDY2

(Note S02)

1.65

1.2

0.75

Y00

2.4 3.4 4.4

Y01

2.4 3.4 4.4

CBB

9.5 11.0 12.5

PBB

9.9 11.4 12.9

PBR

18.0

16.0

14.0

CRR

9.5 11.0 12.5

PRB

15.0

13.5

12.0

YUV gain

PRR

(Note S03)

10.0 11.5 13.0

TA1360AFG

2003-01-21

Color Difference Block 2

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

Color difference contrast adjustment
characteristic

uCY

(Note A01)

14.5 16.0 17.5 dB

cCY

3.0 4.0 5.0

Color adjustment characteristic

vcCY

(Note A02)

RMAX

109 111.5 114

RCNT

98.5 101 103.5

RMIN

88 90 92

BMAX

0.86 0.90 0.94

BCNT

0.65 0.69 0.73

R-Y relative phase and amplitude

BMIN

0.42 0.45 0.49

times

GMAX

251 254 257

GCNT

244 247 250

GMIN

229 232 235

BMAX

0.43 0.48 0.53

BCNT

0.33 0.37 0.41

G-Y relative phase and amplitude

BMIN

0.22 0.25 0.28

times

GHT

0.47 0.50 0.53

GHT

0.47 0.50 0.53

Color difference halftone
characteristic

GHT

(Note A03)

0.47 0.50 0.53

times

0.09 0.23 0.37

0.26 0.40 0.54

0.44 0.58 0.72

Vp-p

Color

characteristic

(Note A04)

0.60 0.70 0.80

CLT

1.45 1.65 1.85

Color limiter characteristic

CLT

(Note A05)

1.80 2.00 2.20

Vp-p

High-bright color gain

HBC

(Note A06)

0.02 0.04 0.06 times

TA1360AFG

2003-01-21

Text Block

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

3.08 3.45 3.90

AC gain (Y1in~R/G/B out)

(Note T01)

3.08 3.45 3.90

times

G/R

0.94

1.00

1.06

AC gain axis difference

B/R

0.94

1.00

1.06

30 60

Frequency characteristic
(Y1in~R/G/B out)

3dB, sharpness

characteristic is flat

30 60

MHz

fCb

10 12.5

Frequency characteristic
(Cb1/Cr1in~R/G/B out)

fCr

10 12.5

MHz

Unicolor adjustment characteristic

(Note T02)

15.0

16.0

17.0

brMAX

4.10 4.45 4.80

brCNT

3.05 3.40 3.75

Brightness adjustment characteristic

brMIN

(Note T03)

1.95 2.30 2.65

wps1

2.20 2.32 2.44

White peak slice level

wps2

(Note T04)

2.59 2.74 2.89

Vp-p

Black peak slice level

bps

(Note T05)

1.15 1.35 1.45 V

RGB output S/N

(Note T06)

HT1

0.45

0.50

0.55

Halftone characteristic

HT2

(Note T07)

0.45

0.50

0.55

times

Halftone on voltage

Pin 79

0.65

0.85

1.05

0.30

0.80

1.30

0.30

0.80

1.30

V-BLK pulse output level

0.30

0.80

1.30

0.30

0.80

1.30

0.30

0.80

1.30

H-BLK pulse output level

0.30

0.80

1.30

0.00

0.30

BLK pulse delay time

OFF

(Note T08)

0.08

0.30

1.95

2.45

2.95

Sub-contrast variable range

vsu

3.8

3.3

2.8

CUT

0.42

0.47

0.52

Cut-off voltage variable range

CUT

0.42

0.47

0.52

#12

2.05 2.30 2.55

#13

2.05 2.30 2.55

RGB output voltage

#14

2.05 2.30 2.55

RGB output voltage 3-axis difference

OUT

0 150

TA1360AFG

2003-01-21

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

2.5

3.0

3.5

5.5

5.0

4.5

2.5

3.0

3.5

5.5

5.0

4.5

2.5

3.0

3.5

5.5

5.0

4.5

2.5

3.0

3.5

5.5

5.0

4.5

2.5

3.0

3.5

5.5

5.0

4.5

2.5

3.0

3.5

5.5

5.0

4.5

2.5

3.0

3.5

5.5

5.0

4.5

2.5

3.0

3.5

Drive adjustment variable range

(Note T09)

5.5

5.0

4.5

1.7

1.85

2.0

1.7

1.85

2.0

Output voltage at P-mute

1.7

1.85

2.0

P-mute ON voltage

MUTE

Pin 79

1.90

2.15

2.40

1.0 1.2

1.4

1.0 1.2

1.4

Output voltage at blue background

1.1 1.25

1.4

Vp-p

Input impedance of #78

Zin

(Note T10)

ACL

6.5

4.5

2.5

ACL characteristic

ACL

(Note T11)

15.0

13.5

11.0

ABL

0.21

0.16

0.11

ABL

0.28

0.23

0.18

ABL

0.37

0.32

0.27

ABL

0.45

0.40

0.35

ABL

0.54

0.49

0.44

ABL

0.62

0.57

0.52

ABL

0.70

0.65

0.60

ABL point

ABL

(Note T12)

0.75

0.70

0.65

ABL

0.06

0.02

0.00

ABL

0.17

0.12

0.07

ABL

0.34

0.29

0.24

ABL

0.52

0.47

0.42

ABL

0.68

0.63

0.59

ABL

0.85

0.80

0.75

ABL

1.01

0.96

0.91

ABL gain

ABL

(Note T13)

1.09

1.04

0.99

TA1360AFG

2003-01-21

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

12R

2.15

2.40

2.65

13R

0.30

0.80

1.30

14R

0.30

0.80

1.30

12G

0.30

0.80

1.30

13G

2.15

2.40

2.65

14G

0.30

0.80

1.30

12B

0.30

0.80

1.30

13B

0.30

0.80

1.30

RGB output mode

14B

(Note T14)

2.15

2.40

2.65

56 66

IRE

0.49

1.24

1.99

1.67

0.92

0.17

Y-OUT

characteristic

(Note T15)

4.59

3.84

3.09

Pmin

37 42 47

Pcnt

72 77 82

Pmax

101 106 111

IRE

Gmin

2.1 3.1 4.1

Gcnt

6.4 7.4 8.4

White-peak blue characteristic

Gmax

(Note T16)

Forced BLK input threshold voltage

BLKIN

Pin 79

5.1 5.6 6.1 V

ACBR

ACBG

ACBB

ACB1R

0.15 0.20 0.25

ACB1G

0.15 0.20 0.25

ACB1B

0.15 0.20 0.25

ACB2R

0.27 0.32 0.37

ACB2G

0.27 0.32 0.37

ACB2B

0.27 0.32 0.37

ACB3R

0.52 0.57 0.62

ACB3G

0.52 0.57 0.62

ACB insertion pulse phase and
amplitude

ACB3B

(Note T17)

0.52 0.57 0.62

Vp-p

0.73

0.93

1.13

0.73

0.93

1.13

IK input amplitude

(Note T18)

0.73

0.93

1.13

Vp-p

DIK

3.00 3.30 3.60

IK input cover range

DIK

(Note T19)

0.50

0.30

0.10

TA1360AFG

2003-01-21

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

TXR

3.03

3.40

3.83

TXG

3.03

3.40

3.83

Analog RGB gain

TXB

(Note T20)

3.03

3.40

3.83

times

TXG/R

0.94

1.00

1.06

Analog RGB gain 3-axis difference

TXB/R

0.94

1.00

1.06

TXR

30 35

TXG

30 35

Analog RGB frequency characteristic

TXB

3dB

30 35

MHz

0.80

1.20

1.50

0.80

1.20

1.50

Analog RGB input dynamic range

0.80

1.20

1.50

Vp-p

TXV

WPSR

2.45 2.70 2.95

TXV

WPSG

2.45 2.70 2.95

Analog RGB white peak slice level

TXV

WPSB

(Note T21)

2.45 2.70 2.95

Vp-p

BPSR

1.15 1.30 1.45

BPSG

1.15 1.30 1.45

Analog RGB black peak limit level

BPSB

(Note T22)

1.15 1.30 1.45

uTXR

15.5 16.5 18.5

uTXG

15.5 16.5 18.5

RGB contrast adjustment
characteristic

uTXB

(Note T23)

15.5 16.5 18.5

brTXmax

3.0 3.2 3.4

brTXcnt

2.6 2.8 3.0

Analog RGB bright adjustment
characteristic

brTXmin

(Note T24)

2.1 2.3 2.5

Analog RGB mode switching voltage

TXON

0.65 0.85 1.05 V

RYS

FYS

RYS

Analog RGB mode switching transfer
characteristic

RYS

(Note T25)

TXACL

6.7

4.7

2.7

Text ACL characteristic

TXACL

(Note T26)

16.5

14.5

12.5

OSDR

2.95 3.30 3.70

OSDG

2.95 3.30 3.70

Analog OSD gain

OSDB

(Note T27)

2.95 3.30 3.70

times

OSDG/R

0.94

1.00

1.06

Analog OSD gain 3-axis difference

OSDB/R

0.94

1.00

1.06

OSDR

OSDG

Analog OSD frequency characteristic

OSDB

3dB

MHz

0.80

1.20

1.50

0.80

1.20

1.50

Analog OSD input dynamic range

0.80

1.20

1.50

Vp-p

TA1360AFG

2003-01-21

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

OSDV

WPSR

2.45 2.70 2.95

OSDV

WPSG

2.45 2.70 2.95

Analog OSD input white peak slice
level

OSDV

WPSB

(Note T28)

2.45 2.70 2.95

Vp-p

OSDV

BPSR

1.30 1.45 1.60

OSDV

BPSG

1.30 1.45 1.60

Analog OSD black peak limit level

OSDV

BPSB

(Note T29)

1.30 1.45 1.60

UOSDR11

0.58 0.64 0.71

UOSDG11

0.58 0.64 0.71

UOSDB11

0.58 0.64 0.71

UOSDR10

0.47 0.53 0.59

UOSDG10

0.47 0.53 0.59

UOSDB10

0.47 0.53 0.59

UOSDR01

0.31 0.37 0.45

UOSDG01

0.31 0.37 0.45

UOSDB01

0.31 0.37 0.45

UOSDR00

0.19 0.22 0.24

UOSDG00

0.19 0.22 0.24

OSD contrast adjustment
characteristic

UOSDB00

(Note T30)

0.19 0.22 0.24

Vp-p

brOSD0

2.20 2.40 2.60

brOSD1

2.05 2.25 2.45

brOSD2

1.95 2.15 2.35

Analog OSD bright adjustment
characteristic

brOSD3

(Note T31)

1.80 2.00 2.20

OSDON1

2.05 2.30 2.55

Analog OSD mode switching voltage

OSDON2

2.05 2.30 2.55

RYS1

FYS1

RYS1

RYS2

FYS2

RYS2

Analog OSD mode switching transfer
characteristic

RYS2

(Note T32)

OSDACL

0.00

OSDACL

0.00

OSDACL

6.7

4.7

2.7

OSD ACL characteristic

OSDACL

(Note T33)

16.5

14.5

12.5

TA1360AFG

2003-01-21

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

41TV

42TV

43TV

41TV

42TV

43TV

41TV

42TV

43TV

41OSD

6.5

5.5

4.5

42OSD

6.5

5.5

4.5

43OSD

6.5

5.5

4.5

41OSD

12.0

10.5

9.0

42OSD

12.0

10.5

9.0

43OSD

12.0

10.5

9.0

41OSD

42OSD

OSD blending characteristic

43OSD

(Note T34)

RGB input

OSD input

RGB input

OSD input

RGB input

Input: Signal 1
(f

4 MHz,

Amplitude 0.7 Vp-p)

RGB input in
three axes

Input crosstalk

OSD input in
three axes

Input: Signal 1
(f

1 MHz,

Amplitude 0.7 Vp-p)

BLP

min

23 28 33

BLP

max

55 60 65

IRE

BLG

min

2.4 2.9 3.4

Blue stretch point/gain

BLG

max

(Note T35)

5.4 6.4 7.4

84 89 94

89 94 99

93 98 103

Blue stretch

correction

(Note T36)

98 103 108

IRE

WPL1

16 21 25

WPL2

51 56 61

White letters improvement

WPL3

(Note T37)

97 102 107

Vp-p

TA1360AFG

2003-01-21

Sync Block

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

Sync input horizontal sync phase

(Note HA01)

0.55 0.65 0.75

HD input horizontal sync phase

(Note HA02)

0.58 0.68 0.78

DUTY1

0.5 2.0

DUTY2

62 67 72

DUTY3

99.5 98

Polarity detecting rage

DUTY4

(Note HA03)

47.5 52.5 57.5

thS00

10 16 22

thS01

18 24 30

thS10

26 32 38

Sync input threshold amplitude

thS11

(Note HA04)

34 40 46

HD input threshold voltage

thHD

(Note HA05)

0.65 0.75 0.85 Vp-p

SFT

11 12.5 14

Horizontal picture position (phase)
adjustment variable range

SFT

(Note HA06)

11 12.5 14

Horizontal picture position (phase)
shift switching amount

SFT

5.2 6.7 9.2 %

Curve correction variable amount

#40

(Note HA07)

2.9 3.4 3.9 %

3.1 3.8 4.5

2.0 2.5 3.0

4.7 5.0 5.3 V

0 0.7 1.5

1.9 2.4 2.9

4.7 5.0 5.3 V

3.2 4.2 5.2

2.2 2.7 3.2

Clamp pulse phase/width/level

(Note HA08)

4.7 5.0 5.3 V

HBP

S00a

1.2 3.0 5.9

HBP

S00b

1.2 3.0 5.9

HBP

S01a

6.0 8.0 11.0

HBP

S01b

6.0 8.0 11.0

HBP

s10a

10.0 13.0 15.0

HBP

s10b

10.0 13.0 15.0

HBP

s11a

16.0 18.0 21.0

Black peak detection pulse phase

HBP

s11b

(Note HA09)

16.0 18.0 21.0

FBP threshold

thFBP

(Note HA10)

4.8 5.3 5.8 V

HVCO oscillation start voltage

VCO

Pin 42: Monitor, V

voltage

3.0 4.0 5.0 V

H-OUT start voltage

HON

Pin 37: Monitor, V

voltage

5.0 6.0 7.0 V

H-OUT stop voltage

HOFF

Pin 37: Monitor, V

voltage 4.3 5.3 6.3 V

38 41 43

H-OUT pulse duty

(Note HB01)

44 47 49

TA1360AFG

2003-01-21

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

F15K

15.59 15.75 15.91

F28K

27.90 28.125 28.35

F31K

31.19 31.5 31.82

F33K

33.41 33.75 34.09

F37K

37.60 37.9 38.40

Horizontal free-run frequency

F45K

(Note HB02)

44.52 45.0 45.48

kHz

F15K

MIN

14.78 15.08 15.38

F15K

MAX

16.37 16.70 17.03

F28K

MIN

26.00 26.90 27.80

F28K

MAX

28.90 29.70 30.60

F31K

MIN

29.47 30.06 30.65

F31K

MAX

32.72 33.39 34.06

F33K

MIN

31.41 31.94 32.57

F33K

MAX

34.91 35.62 36.33

F37K

MIN

36.50 37.30 38.20

F37K

MAX

40.20 41.10 42.10

F45K

MIN

43.20 44.00 44.80

Horizontal oscillation frequency
variable range

F45K

MAX

(Note HB03)

47.85 48.65 49.45

kHz

BH15K

176 220 264

BH28K

320 400 480

BH31K

352 440 528

BH33K

376 470 564

BH37K

390 480 570

Horizontal oscillation control
sensitivity

BH45K

Hz/0.1 V (Note HB04)

520 650 780

HOH

4.8 5.1 5.2

H-OUT output voltage

HOL

(Note HB05)

0.1 0.3

Pin 55

fHSW1

1.7 2.0 2.3

fHSW2L

1.3 1.5 1.7

fHSW2M

4.3 4.5 4.7

Horizontal oscillation
frequency control voltage
threshold

Pin 41

fHSW2H

7.3 7.5 7.7

VDAC

TEST

(00), DAC1

(0)

8.5

9.0

DAC1

VDAC

TEST

(00), DAC1

(1)

0.3 0.7

VDAC

TEST

(00), DAC2

(1)

8.5

9.0

DAC switch voltage

DAC2

VDAC

TEST

(00), DAC2

(0)

0.3 0.7

VP output pulse width

(Note V01)

4 4.5 5 H

000 VPt0

1278 1281 1284

001 VPt1

846 849 852

010 VPt2

722 725 728

011 VPt3

657 660 663

100 VPt4

610 613 616

101 VPt5

360 363 366

Vertical free-run
(maximum pull-in range)

110 VPt6

304 307 310

Vertical minimum pull-in range

VPULL

(Note V02)

47 48 49 H

TA1360AFG

2003-01-21

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

VBPP

51 52 53

000

VBPP

1099.5 1100.5 1101.5

VBPP

51 52 53

001

VBPP

729.5 730.5 731.5

VBPP

49.5 50.5 51.5

010

VBPP

599.5 600.5 601.5

VBPP

49.5 50.5 51.5

011

VBPP

544.5 545.5 546.5

VBPP

51 52 53

100

VBPP

499.5 500.5 501.5

VBPP

51 52 53

101

VBPP

289.5 290.5 291.5

VBPP

(Note V03)

51 52 53

Vertical black peak detection
pulse

110

VBPP

239.5 240.5 241.5

BLKMIN

15 16 17

Vertical blanking end phase

BLKMAX

(Note V04)

45 46 47

High V

VPH

4.6 5.0 5.4

VP output voltage

Low V

VPL

pin 35 voltage

0.1 0.5

15.75 kHz

10.0 11.6 13.4

28.125 kHz

5.4 6.4 8.8

31.5 kHz

4.8 5.8 7.6

33.75 kHz

4.4 5.4 7.2

37.9 kHz

3.9 4.8 6.6

SYNC input to VP output delay time

45 kHz

3.1 4.1 5.9

CBLK1

000min

1087 1088 1089

000

CBLK1

000max

1117 1118 1119

CBLK1

001min

719 720 721

001

CBLK1

001max

749 750 751

CBLK1

010min

591 592 593

010

CBLK1

010max

621 622 623

CBLK1

011min

527 528 529

011

CBLK1

011max

557 558 559

CBLK1

100min

487 488 489

100

CBLK1

100max

517 518 519

CBLK1

101min

279 280 281

101

CBLK1

101max

309 310 311

CBLK1

110min

223 224 225

Compression BLK 1
(start phase)

110

CBLK1

110max

253 254 255

TA1360AFG

2003-01-21

Test Condition for Picture Quality (Sharpness) Block

Common Test Condition for Picture Quality (Sharpness) Block

1. SW67

SW66

B, SW63

B, SW60 to SW61

B, SW44

ON, SW40

B, SW18 to SW26

A, SW77

OPEN

Send bus control data as preset values, turn ACB operation switching to ACB OFF (00), select Sync input (1), turn P-MODE to Normal 1(000), WPL-LEVEL to
max (111), and change subaddress (1C) to (03).

Input sync signal, which is in sync with input signal for testing except "Sweep", to #53 (Sync input). "H-Freq." should be the same frequency as the one of #53.

Set Y/color difference input mode to (0), sync separator level to 20 % (01), and vertical free-running frequency to 307H (110).

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P01

Black detection level shift

OPEN 1. Connect external power supply PS to #68, and monitor #70 and #74.

2. Set black stretch point 1 to OFF (000), and black detection level to 0 IRE (1).

3. Increase PS voltage from 4.95 V in steps of 1 mV. At the moment when #70 picture period (High) drops to

Low level, monitor DC difference on #74 V

4. Set black detection level to 3 IRE (0).

5. Repeat the step 3 above and monitor DC difference, V

on #74.

P02

Black stretch amp maximum
gain

OPEN 1. Set SW70 to A (maximum gain), and input 500-kHz sine wave to TPA.

2. Adjust signal amplitude to 0.1 Vp-p on #68.

3. Set black stretch point 1 to OFF (000), and measure #74 amplitude V

4. Set black stretch point 1 to 001 (black stretch ON), and measure #74 amplitude V

5. Calculate GBS using a following equation.

GBS

) [dB]

, V

#74 waveform

#70 waveform

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P03

Black stretch start point 1

OPEN 1. Set SW70 to A (maximum gain), and black stretch point 1 to OFF (000). Apply 0 V to #71.

2. Connect external power supply PS to #68, increase voltage from V

, and plot #74 voltage change S1. The

#74 voltage is set as V

when V

is applied, and as V

100

when V

0.7 V is applied.

3. Set black stretch point 1 to minimum (001), increase PS voltage from V

, and then plot #74 voltage change

S2.

4. Set black stretch point to maximum (111), repeat 3 above, then plot #74 voltage change S3.

5. Determine intersection points of S1, S2 (V

BST1

), and S3 (V

BST2

) as shown in the figure below. Also

calculate P

BST1

and P

BST2

using following equations.

[V]

100

[V]

BST1

[(IRE)]

[(V

BST1

[V]

[V])

]

100 (IRE)

BST2

[(IRE)]

[(V

BST2

[V]

[V])

]

100 (IRE)

#74

#68

BST1

BST2

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P04

Black stretch start point 2

1. Set black stretch point 1 to OFF (000), apply 0 V to #71, input TG7 LINEARITY to TPA, adjust amplitude on

#68 as shown in the figure below, set unicolor to center (1000000), and measure amplitude of #12 (R OUT),
V

P12

2. Set black stretch point 1 to 001 (black stretch ON), connect external power supply PS to #74, and monitor

#12 (R OUT).

3. Set black stretch start point 2 data to minimum (00). When PS is V

(APL 0%), and V

1.0 V (APL

100%), determine black stretch start point difference

as shown in the figure below. (Monitor input

waveform and output waveform with an oscilloscope, adjust the both waveforms to have the same amplitude
(gradient), and compare them to determine the bend point of the output.)

4. Set black stretchstart point 2 data to maximum (11), determine black stretch start point difference

5. Calculate

following

equations.

BS1

(

P12

)

100

BS2

(

P12

)

100

APL 0%

#68 waveform (linearity)

0.7 V

p-p

0.3 V

p-p

***

#12 (R OUT)

APL 100%

LINEARITY

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P05

Black stretch characteristic
switch

OPEN 1. Set SW70 to A (maximum gain), black stretch point 1 (18) to maximum (E0), subaddress (1C) data to (00)

and (1E) data to (08).

2. Apply 0 V to #71 and connect external power supply PS to #68. Set PS to V

0.7 V, and adjust unicolor so

that DC level of #12 is

1.0 V. Plot voltage change S4 of #12 (voltage in picture period).

3. Determine intersection points (V

BSC1

and V

BSC2

) of S2 and S4 obtained from the plot in black stretch start

point 1. Then calculate P

BSC1

and P

BSC2

using following equation.

4. Set black stretch characteristic switch subaddress data (1C)/(1E) to (20)/(00) and (20)/(08) respectively. As

described in steps 2 and 3, determine intersection points (V

BSC3

, V

BSC4

, V

BSC5

and V

BSC6

) and calculate

BSC3

BSC4

BSC5

and

BSC6.

BSC

[V]

[V])

1.0

100 [(IRE)]

V68

S4 Black stretch characteristic switch ON

BSC2

BSC1

#12

0.7 V

#68

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P06 Black

stretch

area

reinforcement current

1. Connect external power supply PS1 to #68.

2. Leave SW70 open, put an ammeter between SW70A and #70, connect external power supply PS2 to SW70A,

set PS1 to 5.7 V, and set PS2 to 5 V.

3. Measure current value IBSA0 and IBSA1 when bus data of black stretch area reinforcement [18] is set to ON

[80] and OFF [81]. Calculate IBSA using the following equation.

IBSA

IBSA0

IBSA1

P07

D.ABL detection voltage

OPEN 1. Set D.ABL sensitivity to maximum (11), and black stretch point 1 to OFF (000).

2. Connect external power supply PS to #78 and decrease voltage from 6.5 V.

3. Repeat 2 when D.ABL detection voltage is changed to 00, 01, 10, and 11. At the moment when #74 picture

period changes to Low, measure respective PS voltages V

, V

, and V

4. Calculate voltage differences between V

and V

(DV

), between V

and V

(DV

), and between V

and V

(DV

)

***

, V

)

#70 waveform

#74 detected

#74 undetected

mmeter

SW70

PS2

5 V

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P10 Dynamic

correction point

OPEN 1. Connect external power supply PS1 to #68, PS2 to TP1, and set PS2 to 0 V.

2. Set dark area dynamic Y

gain VS dark area to MIN (00), static Y

gain1 to OFF (000).

3. Increase PS1 from V

[V] to V

[V]

0.7 V and plot voltage change of #12 picture period. Take 0 for V

[V] when the change is plotted. (V

is pin voltage of pin 68)

4. Set dark area dynamic Y

gain VS dark area max (11), static Y

gain1 to max (111) and PS2 to 1.2 V.

5. Increase PS1 from V

[V] to V

[V]

0.7 V and plot voltage change of #12 picture period.

6. Measure VDGP by the following figure, and P

DGP

using the following equation.

DGP

(VDGP [V]

[V])/0.7 [V]

100

OFF

#12 voltage [V]

#68 voltage [V]

VDGP

0.7V

(100 IRE)

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P11 Dark

area

dynamic

gain

OPEN 1. Connect external power supply PS1 to #68, external power supply PS2 to TP1, and set PS2 to 0 V.

2. Set dark area dynamic Y

gain [1C] to MIN [03], and dark area static Y

gain [1C] to 0dB [17].

3. Set PS1 to V

[V], and measure #12 picture period voltage VDDGV

[V].

Set PS1 VDGP [V], and measure #12 picture period voltage VDDGMIN [V].

4. Set dark area dynamic Y

gain [1C] to MAX [D7], PS2 to 1.2 V, measure voltage VDDGMAX [V] of #12

picture period when PS1 is VDGP [V], and calculate the following equations.

VDDGMAX

VDDGMIN

VDDGV

GDDGMAX

20 og

[B/(B-A)] [dB]

OFF

#12 voltage [V]

#68 voltage [V]

VDGP

VDDGV

VDDGMIN

VDDGMAX

VDDGMIN

VDDGV

VDDGMAX

VDDGMIN

0.7 V

(100IRE)

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P12

Dark area static Y

gain

OPEN 1. Connect external power supply PS1 to #68, external power supply PS2 to TP1, and set PS2 to 0 V.

2. Set dark area dynamic Y

gain [1C] to MIN [03], and dark area static Y

gain [1C] to OFF [03].

3. Set PS1 to V

[V], and measure #12 picture period voltage VSGOFF1 [V].

4. Set PS1 to VDGP [V], and measure #12 picture period voltage VSGOFF2 [V].

5. Set dark area static Y

gain [1C] to MAX [1F], PS1 to VDGP [V], measure #12 picture period voltage

VSGMAX, and calculate GDSGMAX using the following equations.

VSGMAX

VSGOFF2

VSGOFF1

GDSGMAX

[B/(B - A)] [dB]

6. Set dark area static Y

gain [1C] to MIN [07], PS1 to VDGP [V], measure #12 picture period voltage VSGMIN,

and calculate GDSGMIN using the following equation.

GDSGMIN

[(VSGMIN

VSGOFF1)/(VSGOFF2

VSGOFF1)] [dB]

OFF

#12 voltage [V]

#68 voltage [V]

VDGP

VSGOFF1

VSGOFF2

VSGMAX

VSOFF2

0.7 V

(100IRE)

VSGOFF2

VSGOFF1

VSGMIN

VSGOFF1

OFF

#12 voltage [V]

#68 voltage [V]

VDGP

VSGOFF1

VSGOFF2

VSGMIN

0.7 V

(100IRE)

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P13 Light

area

correction point

OPEN 1. Connect external power supply PS1 to #68, external power supply PS2 to TP1, and set PS2 to 0 V.

2. Set dark area static Y

gain [1C] to 0dB [17], and bright area static Y

gain [1C] to 0dB [17].

3. Increase PS1 from V

[V] to V

[V] + 0.7 [V], and plot the voltage change of #12 picture period. Take 0 for

[V] when the change is plotted. (V

is pin voltage of pin 68)

4. Set light area static Y

gain [1C] to MAX [04].

5. Increase PS1 from V

[V] to V

[V]

0.7 [V], and plot the voltage change of #12 picture period.

6. Measure VLGP using the following figure, and PLGP using the following equation.

LGP

(VLGP [V]

[V])/0.7 [V]

100 (IRE)

#12 voltage [V]

OFF

#68 voltage

VLGP

0.7 V

(100IRE)

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P14

Light area dynamic Y

gain

OPEN 1. Connect external power supply PS1 to #68, external power supply PS2 to TP7, and set PS2 to 1.2 V.

2. Set dark area static Y

gain [1C] to 0dB [17], and light area static Y

gain [1C] to 0dB [17].

3. Set PS1 to V

[V], and measure #12 picture period voltage VLDGOFF1.

4. Set PS1 to VLGP [V], and measure #12 picture period voltage VLDGOFF2.

5. Set light area static Y

gain [1C] to MAX [14], PS2 to 0 V, PS1 to VLGP [V], determine #12 picture period

voltage VLDGMAX [V] using the following equations.

VLDGMAX

VLDGOFF2

VLDGOFF1

GLDG

[B/(B

A)]

VLDGMAX

VLDGOFF2

VLDGOFF1

OFF

#12 voltage [V]

#68 voltage

VLGP

VLDGOFF1

VLDGOFF2

VLDGMAX

0.7 V

(100IRE)

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P15

Light area static Y

gain

OPEN 1. Connect external power supply PS1 to #68, external power supply PS2 to TP7, and set PS2 to 0 V.

2. Set dark area static Y

gain [1C] to 0dB [17], and light area static Y

gain [1C] to 0dB [17].

3. Set PS1 to V

[V], and measure #12 picture period voltage VLSGOFF1 [V].

4. Set PS1 to VLGP [V], and measure #12 picture period voltage VLDGOFF2 [V].

5. Set light area static Y

gain [1C] to MAX [14], PS1 to VLGP [V], measure #12 picture period voltage

VlSGMAX, and calculate GLASGMAX [dB] using the following equations.

VLSGMAX

VLSGOFF2

VLSGOFF1

GLSGMAX

[B/(B

A)] [dB]

6. Set light area static Y

gain [1C] to MIN [16], PS1 to VLGP [V], measure #12 picture period voltage

VLSGMIN, and calculate GLASGMIN [dB] using the following equations.

VLSGMIN

VLSGOFF2

VLSGOFF1

GLSGMIN

[B/(B

C)] [dB]

VLSGMIN

VLDGOFF2

VLSGOFF2

VLSGOFF1

OFF

#12 voltage [V]

#68 voltage [V]

VLGP

VLSGOFF1

VLSGMIN

0.7 V

(100IRE)

VLSGMAX

VLDGOFF2

VLSGOFF2

VLSGOFF1

OFF

#12 voltage [V]

#68 voltage [V]

VLGP

VLSGOFF1

VLSGOFF2

VLSGMAX

0.7 V

(100IRE)

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P17 DC

restoration

rate

correction

gain

1. Set DC restoration rate correction point to minimum (000), DC restoration rate correction limit point to 80%

(11), and connect external power supply PS1 to #68.

2. Monitor DC level of #12 picture period. Set PS1 to V

0.7 V, and adjust uncolor so that DC level is

0.7.

3. Set DC restoration correction rate to minimum (000), and measure V

DT1

and V

DT2

of V

[V] and V

0.1

V as shown in the figure below.

4. Set #68 to V

0.1 V, DC restoration correction rate to maximum (111), and measure V

DT3

5. Set DC restoration correction rate SW to less than 100 % (1), #68 to V

0.1 V, DC restoration correction

rate to maximum (111), and measure V

DT4

6. Calculate

ADT

100

, ADT

135

, and ADT

using following equations.

ADT

100

DT2

[V]

DT1

[V])

0.1 [V]

ADT

135

DT3

[V]

DT1

[V])

0.1 [V]

ADT

( (V

DT2

[V]

DT4

[V])

0.1 [V])

Picture period

DT1

[V]

DT2

DT3

DT4

0.1 V

#12 waveform

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P18 DC

restoration

rate

correction

point

1. Set DC restoration rate correction point to minimum (000), DC restoration rate correction limit point to 80%

(11), and connect external power supply PS1 to #68.

2. Monitor DC level of #12 picture period. Set PS1 to V

0.7 V, and adjust unicolor so that DC level is

1.0.

3. Set DC restoration correction rate to minimum (000), and increase PS1 from V

. Plot relation between #74

(DC voltage) and #12 (voltage in picture period).

4. Set DC restoration correction rate to maximum (111), and increase PS1 from V

. Plot relation between #74

and #12.

5. Set DC restoration correction rate to maximum (111), DC restoration rate correction point (111), and increase

PS1 from V

. Plot relation between #74 and #12.

6. Determine

DT0

, and V

DT1

using the following equations.

DT0

= [(V

SP0

)/1 V]

100%

DT1

= [(V

SP1

)/1 V]

100%

DC restoration correction
rate 000

DC restoration rate correction
point 111

DC restoration rate
correction point 000

#74

SP1

SP0

#12

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P19 DC

restoration

rate

correction

limit point

1. Set unicolor to maximum (1111111), DC restoration rate correction point to minimum (000), and connect

external power supply PS1 to #74.

2. Set DC restoration correction rate to maximum (111).

3. Increase PS from 5 V. Monitor #12, and plot DC restoration correction amount.

4. Repeat the step 3 above by changing data at DC restoration rate correction limit point. Measure the value

using the figure below. Calculate P

DTL60

, P

DTL75

, P

DTL87

, and P

DTL100

using following equations.

DTL60

= [(V

L60

)/1.0]

100%

DTL75

= [(V

L75

)/1.0]

100%

DTL87

= [(V

L87

)/1.0]

100%

DTL100

= [(V

L100

)/1.0]

100%

100% (00)

87% (01)

73% (10)

60% (11)

L87

L100

L75

L60

#74

#12

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P21

Sharpness control range

1. Input sine wave to TPA. (The frequency is variable.)

2. Set #68 amplitude to 20 mVp-p.

3. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), APACON peak frequency to 13.5 M

(00), and color detail enhancer (CDE) to center (10).

4. Set picture mute to OFF (P-MODE: Normal 1, 000), and monitor #12.

5. Set picture sharpness to center (1000000). Set input frequency to 100 kHz, and measure the amplitude V

100

6. Set picture sharpness to maximum (1111111). Set input frequency to F

AP00

, measure the amplitude V

MAX00

and calculate G

MAX00

using the following equations.

7. Set picture sharpness to minimum (0000000). Set input frequency to F

AP00

, measure the amplitude V

MIN00

and calculate G

MIN00

using the following equations.

8. Set APACON peak frequency to 9.5 M (01). Set input frequency to F

AP01

, measure V

MAX01

MIN01

and

calculate G

MAX01

MIN01

9. Set APACON peak frequency to 6.4 M (10). Set input frequency to F

AP10

, measure V

MAX10

MIN10

and

calculate G

MAX10

MIN10

10. Set APACON peak frequency to 4.5 M (11). Set input frequency to F

AP11

, measure V

MAX11

MIN11

and

calculate G

MAX11

MIN11

MAX

***

MAX

***

100

) [dB]

MIN

***

MIN

***

100

) [dB]

Note: When a spectrum analyzer is used, measure gain for low frequency.

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P22 Sharpness

control

center

characteristic

1. Input sine wave to TPA. (The frequency is variable.)

2. Set the amplitude of #68 to 20 mVp-p.

3. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), APACON peak frequency to 13.5 M

(00), and color detail enhancer (CDE) to center (10).

4. Set picture mute to OFF (P-MODE: Normal 1, 000), and monitor #12.

5. Set picture sharpness to center (1000000). Set input frequency to 100 kHz, and measure the amplitude

100

6. Set picture sharpness to center (1000000). Set input frequency to F

AP00

, measure #12 amplitude V

CEN00

and calculate G

CEN00

using the following equations.

7. Set APACON peak frequency to 9.5 M (01). Set input frequency to F

AP01

, measure V

CEN01

and calculate

CEN01

8. Set APACON peak frequency to 6.4 M (10). Set input frequency to F

AP10

, measure V

CEN10

and calculate

CEN10

9. Set APACON peak frequency to 4.5 M (11). Set input frequency to F

AP11

, measure V

CEN11

and calculate

CEN11

CEN

***

CEN

***

100

) [dB]

Note: When a spectrum analyzer is used, measure gain for low frequency.

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P23 2T

pulse

response

SRT

control

1. Input 2T pulse (0.7 Vp-p) signal to TPA. Set unicolor to maximum (1111111), SRT-GAIN to minimum

(00000), CDE to center (10) picture sharpness control to center (1000000).

2. Set APACON peak frequency to13.5 M (00), and monitor #12.

3. Measure

SRTMIN00

and V

SRTMIN00

as shown in the figure below.

4. Set SRT-GAIN to maximum (11111), and measure T

SRTMAX00

and V

SRTMAX00

5. Set APACON peak frequency to 9.5 M (01). Set SRT-GAIN to minimum (00000) and maximum (11111).

Measure T

SRTMIN01

and T

SRTMAX01

/ V

SRTMAX01

6. Set APACON peak frequency to 6.4 M (10). Set SRT-GAIN to minimum (00000) and maximum (11111).

Measure T

SRTMIN10

and T

SRTMAX10

/ V

SRTMAX10

7. Set APACON peak frequency to 4.5 M (11). Set SRT-GAIN to minimum (00000) and maximum (11111).

Measure T

SRTMIN11

and T

SRTMAX11

8. Calculate the following equations.

SRT00

[

((V

SRTMAX00

)/(V

SRTMIN00

))

SRT01

[(V

SRTMAX01

)/(V

SRTMIN01

)]

SRT10

[(V

SRTMAX10

)/(V

SRTMIN10

)]

SRT11

[(V

SRTMAX11

)/(V

SRTMIN11

)]

20%

100%

***

20%

***

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P24

VSM

gain

B B A B ON

Input

sine

wave

VSM

frequency to TPA. Set #68 amplitude to 0.02 Vp-p.

2. Turn on SW77 and change VSM gain from minimum (001) to maximum (111). Measure #77 amplitude, V

001

011

, V

100

, V

101

, V

110

, and V

111

. Set input amplitude to 0.7 Vp-p, and VSM gain to OFF (000). Measure

TP77 amplitude V

000

3. Calculate the following equations.

V000

= 20

000

/0.7) [dB]

V001

= 20

001

/0.02) [dB]

V010

= 20

010

/0.02) [dB]

V011

= 20

011

/0.02) [dB]

V100

= 20

100

/0.02) [dB]

V101

= 20

101

/0.02) [dB]

V110

= 20

110

/0.02) [dB]

V111

= 20

111

/0.02) [dB]

P25

VSM limit

1. Input sine wave of frequency F

VSM

to TPA.

2. Set VSM gain to 111, and #68 amplitude to 0.7 Vp-p.

3. Turn on SW77 and measure TP77 amplitude V

and V

[Vp-p] as shown in the figure below.

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P26

Y delay time switching

1. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), and input 2T pulse signal

(approximately 0.7 V (p-p)) to TPA.

2. Set picture sharpness to center (1000000).

3. Monitor #68 and #12 as shown in the figure below. Measure YDL00 that is the time difference between

signals #68 and #12.

4. Set Y/C-DL1 to

5 ns (1), and

measure YDL01 as shown in the
figure below.

5. Set Y/C-DL1 to 0 ns (0),

Y/C-DL2 to

10 ns (1) and

measure YDL10 as shown in the
figure below.

6. Set Y/C-DL1 to

5 ns (1),

Y/C-DL2 to

10 ns (1) and

measure YDL11 as shown in the
figure below.

7. Determine YDLA, YDLB, and

YDLC using the following
equations.

YDLA

YDL01

YDL00

YDLB

YDL10

YDL00

YDLC

YDL11

YDL00

2T pulse

Approximately

0.7 Vp-p

50%

YDL00

#68

#12

YDL01
YDL10
YDL11

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P27

Y group delay correction

1. Input Multi Burst signal (4.2-MHz frequency, 0.1 Vp-p at #68) of A signal in TPA. Set unicolor to maximum

(1111111), SRT-GAIN to minimum (00000), and Color detail enhancer (CDE) to minimum (00000).

2. Set sharpness to flat (DEC [30]),

APACON peak frequency to 4.5
M (11), and monitor #12.

3. Sine wave signal A input

becomes like signal B on #12 as
shown in the figure on the right.
Measure S

and S

4. When group delay correction is

set to minimum (0000), signal A
becomes like signal C on #12.
Measure S

AMIN

and S

BMIN

5. When group delay correction is

set to maximum (1111), signal A
becomes like signal D on #12.
Measure S

AMAX

and S

BMAX

6. Calculate the following equations.

AMIN

) [dB]

BMIN

) [dB]

AMAX

) [dB]

BMAX

) [dB]

Note: Sine wave input starts and ends within the picture period such as a burst signal. The wave is not

continuous.

Signal

AMIN

BMIN

BMAX

AMAX

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P28

Color detail enhancer (CDE)

1. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), color to center (1000000), and color

limiter level to 2 Vp (1). Input SWEEP signal to TPA so that #68 amplitude is 20 mVp-p. Set SW67 to A, and
input signal as shown in the figure below (#67 amplitude is 0.2 Vp-p) to TP67.

2. Set picture sharpness to center (1000000), Y detail control to center (1000), and monitor #14 with a spectrum

analyzer.

3. When CDE is at minimum (00), set low frequency area to 0dB, and determine peak level G

CDEMIN

4. When CDE is at maximum (11), set low frequency area to 0dB, and determine peak level G

CDEMAX

5. Calculate the following equation.

CDE00

CDEMAX00

CDEMIN00

6. When APACON peak frequency is 13.5 M (00), 9.5 M (01), 6.4 M (10), and 4.5 M (11), calculate G

CDE00

CDE01

, G

CDE10

, and G

CDE11

respectively using above equation.

max

Output gain [dB]

Input frequency [MHz]

0dB

picture period

BLK

period

0.2 Vp-p

min

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW71 SW70 SW68 SW64 SW74

Test Method (Test condition: V

9 V/2 V, Ta

P29

Y detail control range

1. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), CDE to center (10), and APACON

peak frequency to 4.5 M (11). Input SWEEP signal to TPA.

2. Set #68 amplitude to 20mVp-p.

3. Set picture sharpness to center (1000000), Y detail control to maximum (1111), and monitor #12 with a

spectrum analyzer.

4. Set low frequency area to 0dB, and measure each peak level G

YDMAX

5. Set Y detail control to center (1000), and measure peak level G

YDCEN

6. Set Y detail control to minimum (0000), and measure peak level G

YDMIN

TA1360AFG

2003-01-21

Test Conditions for Color Difference Block 1: YUV input and matrix

Common Test Condition for Color Difference Block 1: YUV input and matrix

1. SW71

B, SW70

B, SW44

ON, SW18 to SW26

A, SW77

OPEN, SW74

OPEN

Transfer BUS control data with preset values.

Turn ACB operation switching to ACB OFF (0), and turn high blight color OFF (0).

Input sync signal [must be sync with input signal for testing except Sweep.] to #53 (sync input), and set SYNC-IN-SW to 1.

Test Conditions

SW Mode

Note No.

Characteristics

SW68 SW67 SW66 SW64

Test Method (Test condition: V

9 V/2 V, Ta

C A A B

SW63 SW61 SW60

S01

Color SRT gain

B B B

1. Set Y mute ON (P-MODE: Y-MUTE, 001), brightness to center (10000000), color to center (1000000),

unicolor to maximum (1111111).

2. Input 2T pulse signal to TP67 so that #67 amplitude is 423 mVp-p.

3. Monitor #14 output waveform. When color SRT peak frequency is 4.5 MHz (0), measure gradients of color

SRT gain for minimum (00), center (10), and maximum (11) that are SB00MIN, SB00CEN, and SB00MAX as
shown in the figure below. Set SB00MIN to 0dB, calculate GS

B00CEN

(SB00CEN/SB00MIN) and

B00MAX

(SB00MAX/SSB00MIN).

4. When color SRT peak is 5.8 MHz (1), measure gradients of color SRT gain for minimum (00), center (10), and

maximum (11). Calculate G

SB01CEN

and G

SB01MAX

5. Input 2T pulse signal to TP66 so that #66 amplitude is 300 mVp-p.

6. Monitor #12 output waveform. When color SRT peak frequency is 4.5 MHz (0), measure gradients of color

SRT gain for minimum (00), center (10), and maximum (11) that are SR00MIN, S

R00CEN

, and S

R00MAX

shown in the figure below. Set SR00MIN to 0dB, calculate GSB00CEN

(SB00CEN/SB00MIN) and

GSB00MAX

(SB00MAX/SSB00MIN).

7. When color SRT peak is

5.8 MHz (1), measure
gradients of color SRT
gain for minimum (00),
center (10), and
maximum (11). Calculate
G

SR01CEN

and

SR01MAX

20%

100%

***

20%

***

Gradient S

***

= V

***

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW68 SW67 SW66 SW64

Test Method (Test condition: V

9 V/2 V, Ta

C A A B

SW63 SW61 SW60 SW74

S02 Dynamic

Y/C

compensation

B B B

OPEN

1. Input 100-kHz sync signal to TP67, and set #67 amplitude to 0.2 Vp-p.

2. Set Y mute OFF (P-MODE: Normal 1, 000), brightness to center (1000000), color to center (1000000),

unicolor to maximum (1111111), and Y/C Gain Comp to minimum (00). Set black stretch point 1 to OFF (000),
dark area static Y

gain to minimum (00), light area static Y

gain to maximum (11), and SW1 to B. Apply 5.16

V to #68 from external power supply PS1.

3. Monitor #14 output waveform, and measure amplitude VBDY0.

4. Set Y/C Gain Comp to maximum (11). Set SW1 to B. Set black stretch point 1 to OFF (000), dark area static

gain to maximum (11), light area static Y

gain to maximum (00), and monitor #14 amplitude VBDY1.

5. Set Y/C Gain Comp to maximum (11). Switch SW1 to A, and TPI to GND. Set black stretch point 1 to

maximum (111), dark area static Y

gain to minimum (00), bright area static Y

gain to maximum (11), and

monitor #14 amplitude VBDY2.

6. Calculate the following equations.

BDY1

(VBDY1/VBDY0), GC

BDY2

(VBDY2/VBDY0)

7. Input 100-kHz sync signal to TP5, and repeat the procedure above. Calculate the following equations.

RDY1

(VRDY1/VRDY0), GC

RDY2

(VRDY2/VBDY0)

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW68 SW67 SW66 SW64

Test Method (Test condition: V

9 V/2 V, Ta

A/C A/B A/B B

SW8 SW9 SW10 SW56

S03 YUV

gain

B B B

OPEN

1. Set picture mute to OFF (P-MODE: Normal 1, 000), brightness to maximum (11111111), color to center

(1000000), and unicolor to maximum (1111111).

2. Set SW68 to A. Set SW67 and SW66 to B, and input 100-kHz sine wave to TPA. Set #68 amplitude to

0.2 Vp-p.

3. Set SW74 open. Measure #74 amplitude VY00 and VY01 when Y/color difference input mode is set to

Y/Cb/Cr (0) and Y/Pb/Pr (1).

4. Set SW68 to C, SW67 to A, and SW66 to B. Input 100-kHz sine wave to TP67, and set #67 amplitude to

0.2 Vp-p.

5. Measure #14 amplitude VB00 when Y/color difference input mode is set to Y/Cb/Cr (0).

6. Measure #14 and #12 amplitude VBB01 and VBR01 when Y/color difference input mode is set to Y/Pb/Pr (1).

7. Set SW68 to C, SW67 to B, and SW66 to A. Input 100-kHz sine wave to TP66, and set #66 amplitude to

0.2 Vp-p.

8. Measure #12 amplitude VR00 when Y/color difference input mode is set to Y/Cb/Cr (0).

9. Measure #14 and #12 amplitude VRB01 and VRR01 when Y/color difference input mode is set to Y/Pb/Pr (1).

10. Calculate the following equations.

Y00

(VY00/0.2), G

Y01

(VY01/0.2)

CBB

(VB00/0.2), G

PBB

(VBB01/0.2),

PBR

(VBR01/0.2)

CRR

(VR00/02), G

PRB

(VRB01/0.2),

PRR

(VRR01/0.2)

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW68 SW67 SW66 SW64

Test Method (Test condition: V

9 V/2 V, Ta

C A A

SW26 SW25 SW24 SW21

A A A A

SW19 SW18

S04 Green

stretch

A A

1. Input signal B as shown in the figure below from TP67 (Cb/Pb1 input), and signal A from TP66 (Cr/Pr input).

2. Set brightness [06] to maximum (FF).

3. Measure amplitudes A, B, C, D, and E at #13 (Gout) as shown in the figure below. (A00 to E00)

4. Set green stretch [14] data to (08), and repeat the step 3 above. (A01 to E01)

5. Set green stretch [14] data to (10), and repeat the step 3 above. (A10 to E10)

6. Set green stretch [14] data to (18), and repeat the step 3 above. (A11 to E11)

7. Green stretch gain is calculated by the following equations

A00

A01

GrA01

A00

A10

GrA10

A00

A11

GrA11

B00

B01

GrB01

B00

B10

GrB10

B00

B11

GrB11

C00

C01

GrC01

C00

C10

GrC10

C00

C11

GrC11

D00

D01

GrD01

D00

D10

GrD10

D00

D11

GrD11

E00

E01

GrE01

E00

E10

GrE10

E00

E11

GrE11

Signal A

0.05 Vp-p

0.087 Vp-p

0.05 Vp-p

0 Vp-p

0.1 Vp-p

Signal B

0.07 Vp-p

0.122 Vp-p

0.14 Vp-p

0.122 Vp-p

0 Vp-p

Pin 13

150°

270°

240°

210°

180°

TA1360AFG

2003-01-21

Test Conditions for Color Difference Block 2

Common Test Conditions for Color Difference Block 2

1. SW71

B, SW70

B, SW61 to SW63

B, SW44

ON, SW40

Unless otherwise specified, measure each bus data with preset values.

Set the following data.
Subaddress (00)

Data (02)

Subaddress (02)

Data (0C)

Subaddress (05)

Data (7F)

Subaddress (06)

Data (6C)

Subaddress (07)

Data (40)

Subaddress (0B)

Data (7F)

Subaddress (0C)

Data (84)

Subaddress (12)

Data (F0)

Subaddress (13)

Data (F0)

Subaddress (15)

Data (00)

Subaddress (18)

Data (00)

Subaddress (1A)

Data (C0)

Subaddress (1B)

Data (E0)

Subaddress (1C)

Data (03)

Subaddress (1D)

Data (78)

Test Conditions

SW Mode

Note No.

Characteristics

SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18

Test Method

A01 Color

difference

contrast

adjustment
characteristic

C A

1. Set brightness to maximum, and subaddress (12) data to (F0).

2. Input signal 3 (f

100 kHz, picture period amplitude = 0.23 Vp-p) from pin 66.

3. Change unicolor data to maximum (7F), center (40), and minimum (00), and

measure pin 12 picture period amplitude V

uCYMAX

, V

uCYCNT

, and V

uCYMIN

respectively.

4. Determine unicolor amplitude ratio between maximum and minimum in

decibels. (

uCY

)

5. Repeat the steps 2 to 4 above with the following pins: Input (picture period

amplitude 0.2 Vp-p) from pin 67, and measure pin 14.

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18

Test Method

A02 Color

adjustment

characteristic

C A

1. Set brightness to maximum, and subaddress (12) data to (F0).

2. Input signal 3 (f

100 kHz, picture period amplitude

0.115 Vp-p) from pin 66.

3. Change color data to maximum (7F), center (40), and minimum (01), and

measure pin 12 picture period amplitudes V

CCYMAX

CCYCNT

, and V

CCYMIN

respectively.

4. Calculate amplitude ratios of maximum and minimum against color center in

decibels. (

CCY

)

5. Repeat the steps 2 to 4 above with the following pins: Input (picture period

amplitude 0.1Vp-p) from pin 67 and measure pin 14.

A03

Color difference halftone
characteristic

C A

A A A A A A

1. Input signal 3 (f

100 kHz, picture period amplitude 0.2 Vp-p) from pin 66.

2. Measure pin 12 output picture period amplitude vHTARY.

3. Apply 1.5 V to pin 79 from external power supply.

4. Measure pin 12 output picture period amplitude vHTBRY.

5. Calculate

GHT

vHTBRY/vHTARY

6. Repeat the steps 1 to 5 above and measure pin 13.

Calculate GHT

vHTBGY/vHTAGY

7. Repeat the steps 1 to 5 above and measure pin 67. Calculate GHT

vHTBBY/vHTABY.

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note No.

Characteristics

SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18

Test Method

A05 Color

limiter

characteristic

C B A A A A A A A

Input

signal

(picture

period

amplitude

0.56 Vp-p) from pin 67.

2. Set subaddress (14) to (00)/(01), and measure pin 12 output signal picture

period amplitude, CLT

/CLT

A06

High-bright

color

gain C B A A A A A A A

Input

signal

(picture

period

amplitude

0.28 Vp-p) from pin 67.

2. Adjust color so that pin 14 output picture period amplitude is 1.2 Vp-p.
3. Set subaddress (0B) data to (80) and measure pin 14 output signal picture

period amplitude v

4. Calculate the following equation. HBC

(1.2

)/1.2

TA1360AFG

2003-01-21

Test Conditions for Text Block

Common Test Conditions for Text Block

1. SW71

B, SW70

B, SW60 to SW64

B, SW44

ON, SW40

Unless otherwise specified, measure each bus data with preset values.

Set the following data.
Subaddress (00) Data (02)
Subaddress (02) Data (0C)
Subaddress (05) Data (7F)
Subaddress (06) Data (6C)
Subaddress (07) Data (40)
Subaddress (0B) Data (7F)
Subaddress (0C) Data (84)
Subaddress (12) Data (F0)
Subaddress (13) Data (F0)
Subaddress (15) Data (00)
Subaddress (18) Data (00)
Subaddress (1A) Data (C0)
Subaddress (1B) Data (E0)
Subaddress (1C) Data (03)
Subaddress (1D) Data (78)

Test Conditions

SW Mode

Note

No.

Characteristics

SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18

Test Method

T01

gain

A B B A A A A A A

Input

signal

100 kHz, picture period amplitude

0.2 Vp-p) from pin 68.

2. Measure pins 12, 13, and 14 picture period amplitude, V

, V

, and V

3. Calculate AC gain using the following equations.

/0.2 G

/0.2

T02 Unicolor

adjustment
characteristic

A B B A A A A A A

Input

signal

100 kHz, picture period amplitude

0.2 Vp-p) from pin 68.

2. Change unicolor data to maximum (7F), center (40), and minimum (00) and measure pin 12

picture period amplitude, V

uMAX

, V

uCNT

, and V

uMIN

respectively.

3. Calculate amplitude ratio of V

uMAX

and V

uMIN

in decibels (

)

T03 Brightness

adjustment
characteristic

1. Input signal 2 from pin 68 and adjust pin 12 picture period output amplitude to 1 Vp-p.
2. Change brightness data to maximum (7F), center (80), and minimum (00) and measure pin

12 voltages, V

brMAX

, V

brCNT

, and V

brMIN

respectively.

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note

No.

Characteristics

SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18

Test Method

T04 White

peak

slice level

C B B A A A A A A

Set

subcontrast

maximum.

2. Apply external power supply to pin 68 and gradually increase voltage from 5.8 V.

3. When picture period of pin 12 is clipped, measure pin 12 picture period amplitude voltage,

wps1

4. Change subaddress (0C) data to (FC) and repeat the steps 1 to 3 above. (V

wps2

)

T05 Black

peak

slice level

1. Apply external power supply to pin 68 and gradually decrease voltage from 5.8 V.

2. When picture periods are clipped, measure pins 14, 13, and 12 voltage, V

bps

T06 RGB

output

S/N

1. Adjust brightness data so that picture period voltage of pin 14 is 2.4 V.

2. Set color data to minimum.

3. Measure noise levels n14-, n13-, and n12-Vp-p in picture period of pin 14, 13, and 12 with an

oscilloscope.

4. Calculate

S/N.

[2.3/(0.2

n14)]

[2.3/(0.2

n13)]

[2.3/(0.2

n12)]

T07 Halftone

characteristic

A B B A A A A A A

Input

signal

100 kHz, picture period amplitude 0.2 Vp-p) from pin 68.

2. Measure pin 14 picture period amplitude v14A.

3. Apply 1.5 V to pin 79 from external power supply.

4. Measure pin 14 picture period amplitude v14B

5. Calculate the following equation. G

HT1

v14B/v14A

6. Stop applying voltage to pin 79. Set subaddress (1A) to data (E2) and measure pin 14-picture

period amplitude, v14C.

7. Calculate the following equation. G

HT2

v414C/v14A

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note

No.

Characteristics

SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18

Test Method

T09 Drive

adjustment
variable range

A B B A A A A A A

Input

signal

100 kHz, picture period amplitude 0.2 Vp-p) from pin 68.

2. Measure picture period amplitude of pin 13 when subaddress (0D) data is changed to

maximum (FE), center (80), and minimum (00).

3. Use picture period amplitude at center as the base. Determine amplitude ratio DR

and

at maximum and minimum in decibels.

4. Repeat the steps 1 to 3 above to measure amplitude ratio of pin 14, DR

and DR

decibels when subaddress (0E) data is changed.

5. Repeat the steps 1 to 3 above to measure amplitude ratio of pin 13, DR

and DR

decibels when subaddress (0E) center data is set to (81) used as the base.

6. Repeat the steps 1 to 3 above to measure picture period amplitude ratio of pin 14, DR

and DR

in decibels when subaddress (0E) data is changed to maximum (FF), center (81),

and minimum (01).

7. Repeat the steps 1 to 3 above to measure picture period amplitude ratio of pin 12, DR

and DR

in decibels when subaddress (0D) data is changed to maximum (FF), center (81),

and minimum (01).

8. Repeat the steps 1 to 3 above to measure picture period amplitude ratio of pin 14, DR

and DR

in decibels when subaddress (0D) data is set to (81), and subaddress (0E) data

is changed.

9. Repeat the steps 1 to 3 above to measure picture period amplitude ratio of pin 13, DR

and DR

in decibels when subaddress (0E) data is set to (81), and subaddress (0D) data

is changed to maximum (FF), center (81), and minimum (01).

10. Repeat the steps 1 to 3 above to measure picture period amplitude ratio of pin 12, DR

and DR

in decibels when subaddress (0D) data is set to (81), and subaddress (0E) data

is changed to maximum (FF), center (81), and minimum (01).

T10 #78

input

impedance

1. Connect external power supply, an ammeter, and a voltmeter to pin 78. Adjust voltage so that

current value is set to zero.

2. Measure the current when voltage of pin 78 is increased by 0.2V. (l

)

3. Calculate

the

following

equation.

in53

0.2 V/I

(

)

Ammeter (

Voltmeter

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note

No.

Characteristics

SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18

Test Method

T11 ACL

characteristic

A B B A A A A A A

Input

signal

100 kHz, picture period amplitude 0.2 Vp-p) from pin 68.

2. Measure pin 12 picture period amplitude, vACL1.

3. Apply "DC voltage of pin 78

0.8 V" to pin 78 from external power supply and measure pin

12-picture period amplitude, vACL2.

4. Apply "DC voltage of pin 78

1.3 V" to pin 78 from external power supply and measure pin

12-picture period amplitude, vACL3.

5. Calculate

the

following

equations.

ACL

(vACL2/vACL1)

ACL

(vACL3/vACL1)

T12

ABL

point C B B A A A A A A

Measure

voltage

78,

VABL1.

2. Set subaddress (1B) data to (1C).

3. Apply external voltage to pin 78, and decrease voltage from 6.5 V. When voltage of pin 12

starts changing, measure pin 78 voltage, VABL2.

4. Change subaddress (1B) data to (3C), (5C), (7C), (9C), (BC), (DC), and (FC) under the

status of the step 3 above. Measure pin 78 voltage: VABL3, VABL4, VABL5, VABL6, VABL7,
VABL8, and VABL9.

5. ABL

VABL2

VABL1 ABL

VABL6

VABL1

ABL

VABL3

VABL1 ABL

VABL7

VABL1

ABL

VABL4

VABL1 ABL

VABL8

VABL1

ABL

VABL5

VABL1 ABL

VABL9

VABL1

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note

No.

Characteristics

SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18

Test Method

T13 ABL gain

1. Apply 6.5-V external voltage to pin 78.

2. Set subaddress (1B) data to (00).

3. Set brightness data to maximum.

4. Apply 4.5-V external voltage to pin 78.

5. Change subaddress (1B) data to (00), (04), (08), (0C), (10), (14), (18), and (1C).

Repeat the step 3 above, and measure VABL11, VABL12, VABL13, VABL14, VABL15,
VABL16, VABL17, and VABL18.

6. ABL

VABL11

VABL10

ABL

VABL12

VABL10

ABL

VABL13

VABL10

ABL

VABL14

VABL10

ABL

VABL15

VABL10

ABL

VABL16

VABL10

ABL

VABL17

VABL10

ABL

VABL18

VABL10

T14 RGB

output

mode

1. Adjust brightness data so that picture period voltage of pin 12 is 2.4 V.

2. Set subaddress (1B) data to (01).

3. Measure pins 12, 13, and 14 picture period voltage, V

12R

, V

13R

, and V

14R

4. Set subaddress (1B) data to (02), and repeat the step 3 above. Measure pins 12, 13, and 14

picture period voltage, V

12G

, V

13G

, and V

14G

5. Set subaddress (1B) data to (03), and repeat the step 3 above. Measure pins 12, 13, and 14

picture period voltage, V

12B

, V

13B

, and V

14B

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note

No.

Characteristics

SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18

Test Method

T15 Y-OUT

characteristic

A B B A A A A A A

1. Input RAMP waveform from pin 68. Adjust input amplitude so that picture period amplitude of

pin 12 is 2.3 Vp-p.

2. Set subaddress (0C) data to (81).

3. Adjust input amplitude so that picture period amplitude of pin 12 is 2.3 Vp-p.

4. Monitor pin 12. According to the figure below, determine Y-OUT

correction start points

and

2. Also determine ratios of gradients at Y-OUT ON to Y-OUT OFF in decibel. (

and

100 IRE

Output amplitude (Y-OUT)

Input amplitude

2.3 Vp-p

Note: Solid line indicates gamma OFF.

Dotted line indicates gamma ON.

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note

No.

Characteristics

SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18

Test Method

T16 White-peak

blue
characteristic

A B B A A A A A A

Input

0.7-Vp-p

RAMP

signal

from

68.

2. Set subcontrast data to maximum.

3. Set subaddress (1F) data to (04).

4. Set subaddress (1E) data to (01), and monitor pin 14. Determine blue stretch start point

Pmin

using the figure below.

5. Repeat the step 4 above by changing subaddress (1E) data to (04) and (07). Determine blue

stretch start point BS

PCNT

and BS

Pmax

6. Set subaddress (1E) data to (04).

7. Monitor pin 14 and calculate ratio of blue stretch ON gradient in relative to blue stretch OFF

gradient in decibel (BS

GCNT

) using the figure below.

8. Repeat the step 7 above by changing subaddress (1F) data to (00) and (07). Calculate

gradient ratio in decibel (BS

Gmin

and BS

Gmax

Note: Calculate white-peak blue start point in IRE as setting positive amplitude at pedestal level

of output signal to 2.3 Vp-p

100 IRE.

OFF

Start point

Output

Input amplitude

(Output from pin 14)

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note

No.

Characteristics

SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18

Test Method

T17 ACB

insertion

pulse phase
and amplitude

B B A A A A A A

Input

signal

1(f

100 kHz, picture period amplitude

0.2 Vp-p) from pin 68. Control drive

gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12.
Set brightness data to 108.

2. Measure pins 4, 6, and 7 voltage. Apply measured voltages from external power supply.

3. Set subaddress (02) data to (40).

4. Use output signals from pins 12, 13, and 14, and measure ACB insertion pulse phase as

shown in the Figure 1.

Note: Take picture period following FBP input fall after V

BLK ends as phase 1H. After next H

BLK, count the phase as 2H, 3H, and so on.

5. Monitor pins 12, 13, and 14. Measure ACB insertion pulse amplitudes (level from picture

period amplitude at quiescent.): VACB1R, VACB1G, and VACB2B.

6. Set subaddress (02) data to (80), and repeat the step 5 above: VACB2R, VACB2G, and

VACB2B.

7. Set subaddress (02) data to (C0), and repeat the step 5 above: VACB3R, VACB3G, and

VACB3B.

Figure 1: RGB Output

ACB insertion pulse

1H 2H 3H 4H

BLK period

Figure 2: FBP Input (#39)

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note

No.

Characteristics

SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18

Test Method

T18 IK

input

amplitude

B B A A A A A A

Input

signal

1(f

100 kHz, picture period amplitude

0.2 Vp-p) from pin 68. Control drive

gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12.

2. Set subaddress (02) data to (40).

3. Measure voltage amplitude of pin-8 input signal in ACB insertion period.

T19 IK input cover

range

C B B A A A A A A

Input

signal

1(f

100 kHz, picture period amplitude

0.2 Vp-p) from pin 68. Control drive

gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12.

2. Set subaddress (02) data to (40).

3. Measure pin 8 DC voltage in V

BLK period. (#8VBLK)

4. Apply the current externally to pin 8.

5. Measure DC voltage of pin 8 in V

BLK period when pin-12 picture period voltage begins to

be decreased. (#8VBLK

)

6. Apply current outward from pin 8.

7. Measure DC voltage of pin 8 in V

BLK period when pin-12 picture period voltage begins to

be increased. (#8VBLK

)

8. DIK

(#8VBLK

)

(#8VBLK)

DIK

(#8VBLK

)

(#8VBLK)

T20 Analog

RGB

gain

A B B A

A A A

Input

signal

1(f

100 kHz, picture period amplitude

0.2 Vp-p) from pin 68. Control drive

gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12.

2. Apply 5-V external voltage to pin 2.

3. Input

signal

1(f

100 kHz, picture period amplitude

0.2 Vp-p) from pin 24.

4. Measure pin 12 picture period amplitude, v12R.

5. Repeat the steps 3 and 4 above with the following pins:

Input from pin 25, and measure output from pin 13 (v13G).
Input from pin 26, and measure output from pin 14 (v14B).

6 Calculate the following equations. GTXR

v12R/0.2 GTXG

v13G/0.2 GTXB

v14B/0.2

T21 Analog

RGB

white peak
slice level

A B B A A A A A A

Input

signal

1(f

100 kHz, picture period amplitude

0.2 Vp-p) from pin 68. Control drive

gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12.

2. Apply 5-V external voltage to pin 2.

3. Set RGB contrast data to maximum (7F).

4. Input signal 2 to pin 24. Gradually increase picture amplitude, and measure picture period

amplitude voltage when output from pin 12 is clipped.

5. Repeat the steps 3 and 4 above with following pins: Input from pin 25 and measure output

from pin 13. Input from pin 26 and measure output pin 14.

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note

No.

Characteristics

SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18

Test Method

T22 Analog

RGB

black peak
limit level

A B B A A A A A A

Input

signal

1(f

100 kHz, picture period amplitude

0.2 Vp-p) from pin 68. Control drive

gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12.

2. Apply 5-V external voltage to pin 2.

3. Set RGB contrast data to maximum (7F).

4. Input signal 2 to pin 24. Gradually decrease picture amplitude, and measure picture period

amplitude voltage when output from pin 12 is clipped.

5. Repeat the step 4 above with the following pins: Input from pin 25 and measure output from

pin 13. Input from pin 26 and measure output pin 14.

T23 RGB

contrast

adjustment
characteristic

A B B A

1. Input

signal

1(f

100 kHz, picture period amplitude

0.2 Vp-p) from pin 68. Control drive

gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12.

2. Apply 5-V external voltage to pin 2.

3. Input

signal

100 kHz, picture period amplitude

0.2 Vp-p) from pin 24.

4. RGB contrast data to maximum (7F), center (40), and minimum (00). Measure pin 12 picture

period amplitudes V

uTXR

(maximum, center, and minimum) respectively.

5. Calculate amplitude ratio of maximum and minimum in decibels.

6. Repeat the steps 4 and 5 above with the following pins: Input from pin 25 and measure pin

13. Input from pin 26 and measure pin 14.

T24 Analog

RGB

brightness
adjustment
characteristic

A B B A

A A A

Input

signal

1(f

100 kHz, picture period amplitude

0.2 Vp-p) from pin 68. Control drive

gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12.

2. Input signal 2 from pins 26, 25, and 24.

3. Apply 5-V external voltage to pin 2.

4. Adjust amplitude A of signal 2 so that picture period amplitude of pin 12 is 0.5 Vp-p.

5. Change RGB brightness data to maximum (FE), center (80), and minimum (00). Measure

pins 12, 13, and 14 picture period voltage V

brTX

(maximum, center, and minimum)

respectively.

T25 Analog

RGB

mode
switching
transfer
characteristic

C B B A A A A A A

Set

RGB

brightness

data

maximum

(FE).

2. Input signal 4 (signal amplitude

1.5 Vp-p) from pin 2.

3. Measure input/output transfer characteristics using pin 12 according to the figure T-2.

4. Repeat the steps 2 and 3 above with the following pins: Input from pin 25 and measure pin

13. Input from pin 24 and measure pin 14.

5. Calculate maximum inter-axial rise/fall transfer delay time, using the data measured above.

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note

No.

Characteristics

SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18

Test Method

T26 Text

ACL

characteristic

A B B A A B A A A

Input

signal

1(f

100 kHz, picture period amplitude

0.2 Vp-p) from pin 68. Control drive

gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12.

2. Apply 5-V external voltage to pin 2.

3. Input

signal

1(f

100 kHz, picture period amplitude

0.2 Vp-p) from pin 24.

4. Measure pin 12 picture period amplitude, vTXACL1.

5. Apply "pin 78 DC voltage

0.8 V" to pin 78 from external power supply, and measure pin

12-picture period amplitude, vTXACL2.

6. Apply "pin 78 DC voltage

1.3 V" to pin 78 from external power supply, and measure pin

12-picture period amplitude, vTXACL3.

7. TXACL

(vTXACL2/vTXACL1)

TXACL

(vTXACL3/vTXACL1)

T27 Analog

OSD

gain

A B B A A A A

1. Input

signal

1(f

100 kHz, picture period amplitude

0.2 Vp-p) from pin 68. Control drive

gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12.

2. Apply 5-V external voltage to pins 1 and 80.

3. Input

signal

1(f

100 kHz, picture period amplitude

0.2 Vp-p) from pin 18.

4. Measure pin 12 picture period amplitude, v12R.

5. Repeat the steps 3 and 4 above with the following pins: Input from pin 19, and measure pin

13. Input from pin 21 and measure pin 14. (v13G and v14B)

6. Calculate

the

following

equations.

OSDR

v12R/0.2 G

OSDG

v13G/0.2 G

OSDB

v14B/0.2

T28 Analog

OSD

input white
peak slice
level

A B B A A A A A A

Input

signal

1(f

100 kHz, picture period amplitude

0.2 Vp-p) from pin 68. Control drive

gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12.

2. Apply 5-V external voltage to pins 1 and 80.

3. Input signal 2 from pin 18. Gradually increase picture amplitude, and measure picture period

amplitude voltage when output from pin 12 is clipped.

4. Repeat the step 3 above with the following pins: Input from pin 19, and measure pin 13. Input

from pin 21, and measure pin 14.

T29 Analog

OSD

black peak
limit level

A B B A A A A A A

Input

signal

1(f

100 kHz, picture period amplitude

0.2 Vp-p) from pin 68. Control drive

gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12.

2. Apply 5-V external voltage to pins 1 and 80.

3. Input signal 2 from pin 18. Gradually decrease picture amplitude, and measure picture period

amplitude voltage when output from pin 12 is clipped.

4. Repeat the step 3 above with the following pins: Input from pin 19, and measure pin 13. Input

from pin 21, and measure pin 14.

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note

No.

Characteristics

SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18

Test Method

T30 OSD

contrast

adjustment
characteristic

A B B A A A A

1. Input

signal

1(f

100 kHz, picture period amplitude

0.2 Vp-p) from pin 68. Control drive

gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12.

2. Apply 5-V external voltage to pins 1 and 80.

3. Input

signal

1(f

100 kHz, picture period amplitude

0.2 Vp-p) from pin 18.

4. Change OSD contrast data to (11), (10), (01), and (00). Measure pin 12 picture period

amplitude V

uOSDR

(11), (10), (01), and (00) respectively.

5. Repeat the steps 3 and 4 above with the following pins: Input from pin 19, and measure pin

13, V

uOSDG

(11), (10), (01), and (00). Input from pin 21, and measure pin 14, VuOSDB

(11), (10), (01), and (00).

T31 Analog

OSD

brightness
adjustment
characteristic

C B B A A A A A A

Input

signal

1(f

100 kHz, picture period amplitude

0.2 Vp-p) from pin 68. Control drive

gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12.

2. Apply 5-V external voltage to pins 1 and 80.

3. Change OSD brightness data (subaddress 1D) to (38), (78), (B8), and (F8), and measure

picture period voltage of pins 12, 13, and 14 respectively.

Data

(38)

brOSD0

Data

(78)

brOSD1

Data

(B8)

brOSD2

Data

(F8)

brOSD3

T32 Analog

OSD

mode
switching
transfer
characteristic

C B B A A A A A A

Set

OSD

brightness

data

maximum

(11).

2. Input signal 4 (signal amplitude = 4.5 Vp-p) from pin 1.

3. Measure input/output transfer characteristics using pin 12 according to the figure T-2.

4. Repeat the steps 2 and 3 above, and measure pins 13 and 14.

5. Calculate maximum inter-axial rise/fall transfer delay time, using the data measured above.

6. Repeat the steps 1 to 5 above with the following pin. Input signal 4 (signal amplitude 4.5

Vp-p) from pin 80.

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note

No.

Characteristics

SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18

Test Method

T33 OSD

ACL

characteristic

A B B A A A A A B

Input

signal

1(f

100 kHz, picture period amplitude

0.2 Vp-p) from pin 68. Control drive

gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12.

2. Set subaddress (07) data to (01).

3. Apply 5-V external voltage to pins 1 and 80.

4. Input

signal

100 kHz, picture period amplitude

0.2 Vp-p) from pin 18.

5. Measure pin 12 picture period amplitude, vOSDACL1.

6. Apply "pin 78 DC voltage

0.8 V" to pin 78 from external power supply, and measure pin

12-picture period amplitude, vOSDACL2.

7. Apply "pin 78 DC voltage

1.3 V" to pin 78 from external power supply, and measure pin

12-picture period amplitude, vOSDACL3.

8. OSDACL

(vOSDACL2/vOSDACL1)

OSDACL

(vOSDACL3/vOSDACL1)

9. OSDACL3

OSDACL4 Change subaddress (07) data to (80), and repeat the steps 6 to 8

above to measure OSDACL3 and OSDACL4.

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note

No.

Characteristics

SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18

Test Method

T34 OSD

blending

characteristic

B B A A A A

1. Input

signal

1(f

100 kHz, picture period amplitude

0.2 Vp-p) from pin 68.

2. Measure pins 14, 13, and 12 picture period amplitude, v14a, v13a, and v12a.

3. Apply 5-V external voltage to pin 80.

4. Measure pins 14, 13, and 12 picture period amplitude, v14b, v13b, and v12b.

5. Calculate v14b amplitude in relation to v14a, v13b amplitude in relation to v13a, and v12b

amplitude in relation to v12a in decibel:

14TV1,

13TV1, and

12TV1.

6. Apply 5-V external voltage to pin 1, and repeat the steps 3 to 5 above:

14TV2,

13TV2, and

12TV2.

7. Apply 5-V external voltage to pins 1 and 80, and repeat the steps 3 to 5 above:

14TV3,

13TV3, and

12TV3.

8. Set SW68 to C. Set SW21, 19, and 18 to B.

9. Input

signal

100 kHz, picture period amplitude

0.2 Vp-p) from pins 21, 19, and 18.

10. Apply 5-V external voltage to pins 1 and 80.

11. Measure pins 14, 13, and 12 picture period amplitude, v14c, v13c, and v12c.

12. Apply 5-V external voltage to pin 1.

13. Measure pins 14, 13, and 12 picture period amplitude, v14d, v13d, and v12d.

14. Calculate v14d amplitude in relation to v14c, v13d amplitude in relation to v13c, and v12d

amplitude in relation to v12c in decibel:

14OSD1,

13OSD1, and

12OSD1.

15. Apply 5-V external voltage to pin 80, and repeat the steps 12 to 14 above:

14OSD2,

13OSD2, and

12OSD2.

16. Apply 5-V external voltage to pins 1 and 80, and repeat the steps 12 to 14 above:

14OSD3,

13OSD3, and

12OSD3.

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note

No.

Characteristics

SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18

Test Method

T35 Blue

stretch

point/gain

A B B A A A A A A

Input

RAMP

signal

0.7

Vp-p

from

68.

2. Set subcontrast data to maximum.

3. Set subaddress (15) data to (0C).

4. Set subaddress (1A) data to (C0), monitor pin 14, and measure blue stretch start point using

the figure below (BLP

min

5. Set subaddress (1A) data to (CC), and repeat the step 4 above. (BLP

max

)

6. Set subaddress (1A) data to (C4).

7. Monitor pin 14 and measure gradient at blue stretch ON in decibel in relation to the one at

blue stretch OFF according to the figure below. (BLG

max

)

8. Set subaddress (15) data to (04), and repeat the step 7 above. (BLG

min

)

Note: Calculate blue stretch start point in IRE as setting positive amplitude at pedestal level of

output signal to 2.3 Vp-p = 100 IRE.

Blue stretch ON

Blue stretch OFF

Output amplitude

Input amplitude

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note

No.

Characteristics

SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18

Test Method

T36 Blue

stretch

gamma
correction

A B B A A A A A A

Input

RAMP

signal

0.7

Vp-p

from

68.

2. Set subcontrast data to maximum.

3. Set subaddress (15) data to (08).

4. Set subaddress (09) data to (81).

5. Monitor pin 14 and measure amplitude of the intersection point of blue stretch

OFF and

blue stretch

ON according to the figure below. Calculate pin 14 output amplitude in IRE as

setting positive amplitude at pedestal level of output signal to 2.3 Vp-p

100 IRE.

6. Set subaddress (1A) data to (C4), (C8), and (CC). Repeat the step 5 above. (BL

2, BL

3, and

Blue stretch

OFF

Blue stretch

Output amplitude

Input amplitude

Intersection

poiint

TA1360AFG

2003-01-21

Test Conditions

SW Mode

Note

No.

Characteristics

SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18

Test Method

T37 White

letters
improvement

1. Apply a pulse to pin 68 as shown in Figure A.

2. Monitor # 12 output waveform. Plot # 12 output amplitude when changing # 68 input signal

amplitude from 0 to 120 IRE (0.857 Vp-p) (See Figure B below).

3. Set subaddress (19) data to (80).

4. Monitor # 12 output waveform. Plot # 12 output amplitude when changing # 68 input signal

amplitude from 0 to 120 IRE (0.857 Vp-p). Then, compare to the plot in the step 2, calculate
a point where a gradient changes (WPL1).

5. Repeat the step 4 above by changing subaddress (19) data to (83) and (86). Calculate

points where gradients change (WPL2, WPL3).

Figure A

80 ns

# 12 output

amplitude

Data 87

Data 86

Data 83

Data 80

Figure B

# 68 input amplitude

WPL2

WPL3

WPL1

TA1360AFG

2003-01-21

Test Condition for Synchronization Block

Common Test Conditions for Synchronization Block: unless otherwise specified,
V

=
=
=
= 9 V, Ta ==== 25°C, bus data; preset value, SW68 ==== A, SW53 ==== A, SW INPUT ==== B,

SW44

=
=
=
= ON, SW41 ==== OPEN, SW40 ==== B, SW39a ==== B, SW39b ==== OPEN, SW37 ==== B

Note Characteristics

Test

Conditions

HA01 Sync input horizontal

sync phase

Input signal A (as shown in the figure below) to TPA. Set subaddress (00) data to 82H.

Monitor # 53 (Sync input) and #44 (AFC filter) waveforms. Measure phase difference (S

HA02 HD input horizontal

sync phase

1. Set subaddress (00) data to 40H.

2. Input signal B (as shown in the figure below) to TP50.

3. Monitor #50 (Sync input) and #44 (AFC filter) waveforms. Measure phase difference (HD

29.36

µs

0.285 V

0.593

µs

Signal A

#44 waveform

31.75

µs

1.5 V

2.35

µs

Signal B

#44 waveform

TA1360AFG

2003-01-21

Note Characteristics

Test

Conditions

HA03 Polarity

detection

range

1. Set subaddress (00) data to 40H.

2. Input signal B (as shown in the figure below) to TP50 pin.

3. Decrease signal B duty from 10% (to shorter negative polarity period) and measure signal B

duty (HD

DUTY1

) when #50 input signal phase no longer locks with that of #37 (H-OUT).

4. Increase signal B duty from 10% (to longer negative polarity period) and measure signal B duty

(HD

DUTY2

) when #39 (FBP input) phase changes in relation to signal B.

5. Further increase signal B duty (to longer negative polarity period) and measure signal B duty

(HD

DUTY3

) when #50 input signal phase no longer locks with that of #37 (H-OUT).

6. Decrease signal B duty from 90 % (to shorter negative polarity period) and measure signal B

duty (HD

DUTY4

) when #39 (FBP input) phase changes in relation to signal B.

Duty

= A/B × 100% (0 to 100%)

HA04 Sync

input

threshold

amplitude

1. Set subaddress (00) data to 82H, and TEST mode to 01.

2. Connect variable power supply to #53 via 20-k

resistor.

3. Set variable power supply voltage to 0 V, and measure #53 voltage. (SYNC_TIP_00) Also

check that #34 voltage is set to Low (GND level).

4. Increase variable power supply voltage so that #34 voltage becomes High (VCC level).

Measure #53 voltage. (SYNC_OFF_00)

5. Calculate the following equation to determine SYNC input separation level at SYNC separation

level is 00. V

thS00

= (SYNC_OFF_00 - SYNC_TIP_00)/0.286 × 100

6. Change SYNC separation level to 01, 10, and 11. Calculate following equations to determine

VthS01, VthS10, and VthS11.

thS01

= (SYNC_OFF_01 - SYNC_TIP_01)/0.286 × 100

thS10

= (SYNC_OFF_10 - SYNC_TIP_10)/0.286 × 100

thS11

= (SYNC_OFF_11 - SYNC_TIP_11)/0.286 × 100

31.75

µs

1.5 V

Signal B

Sync separation level

0.08H

40IRE

(

= 286 mVp-p)

Sync tip level

34
(SYNC output mode

TA1360AFG

2003-01-21

Note Characteristics

Test

Conditions

HA05 HD

input

threshold

amplitude

1. Set subaddress (00) data to 40H.

2. Input signal B (as shown in the figure below) to TP50.

3. Increase signal B amplitude from 0 Vp-p. When #37 (H-OUT) phase locks with that of signal B,

measure signal B amplitude V

thHD

HA06 Horizontal

picture

phase adjustment
variable range

1. Set subaddress (00) data to 40H.

2. Input signal B (the figure is shown below) to TP50.

3. Change subaddress (01) data from 80H to 00H, and measure phase change amount

SFT

of #39 (H-OUT) waveform.

4. Change slave address (01) data from 80H to FEH, and measure phase change amount

SFT

of #39 (H-OUT) waveform.

31.75

µs

thDH

2.35

µs

Signal B

31.75

µs

1.5 V

2.35

µs

Signal B

#39 waveform
Data: 00H

SFT

#39 waveform
Data: FEH

#39 waveform
Data: 80H

TA1360AFG

2003-01-21

Note Characteristics

Test

Conditions

HA07 Curve

correction

amount

1. Set subaddress (00) data to 40H.

2. Input signal B (as shown in the figure below) to TP50.

3. Connect external voltage to #40 (curve correction), and measure phase change amount

(

H#40) of #37 (H-OUT) output waveform at 1.5 V and 3.5 V.

HA08 Clamp pulse phase,

width and level

1. Set subaddress (00) data to 40H.

2. Input signal B (as shown in the figure below) to TP50.

3. Measure #47 (SCP output) clamp pulse phase (CP

), width (CP

PW0

), and output level

(CP

) in relation to signal B.

4. Set subaddress (01) data to 81H, and repeat the step 3 above to measure (CP

), (CP

and (CP

5. Apply no signal input to TP50.

6. Measure #47 clamp pulse phase (CP

), width (CP

), and output level (CP

) in relation to

#39.

31.75

µs

1.5 V

2.35

µs

Signal B

#37 waveform
(#40 voltage; 1.5 V)

H#40

#37 waveform
(#40 voltage; 3.5 V)

31.75

µs

1.5 V

2.35

µs

Signal B

#47 waveform

#39 waveform

V0/1

W0/1

S0/1

#47 waveform

TA1360AFG

2003-01-21

100

Note Characteristics

Test

Conditions

HA09 Black peak detection

pulse phase and
level

1. Set subaddress (00) data to 40H.

2. Set SW70 to C, SW68 to C, and SW39A to OPEN

3. Input signal C (as the figure shown below) to #39 (FBP input).

4. Measure #70 (BPH filter) black peak detection pulse phase (HBP

S00a

and HBP

S00b

) in relation

to signal C.

5. Set HBP-PHS 1/2 to (01), (10), and (11). Measure black peak detection pulse phase.

HA10 FBP input threshold

1. Set subaddress (00) data to 40H.

2. Input signal B (as shown in the figure below) to TP50.

3. Increase amplitude of FBP signal to be input to #39 (FBP input) from 0 Vp-p. When #37

(H-OUT) phase locks with that of signal B, measure #39 input amplitude V

thFBP

31.75

µs

1.5 V

2.35

µs

31.5

µs

2 V

0 V

Signal C

#70 waveform

4.13

µs

HBP

S**b

HBP

S**a

TA1360AFG

2003-01-21

101

Note Characteristics

Test

Conditions

HB01 H-OUT pulse duty

1. No signal input.

2. Measure T1 and T2 (as shown in the figure below) from #37 (H-OUT) output waveform when

subaddress (00) data is 80H and A0H. Calculate duties (TH

and TH

) using the following

equation:

= T1/(T1 + T2) × 100 %

HB02 Horizontal

free-run

frequency

1. Set SW44 to open.

2. Set subaddress (00) data to 01H and measure horizontal free-run frequency (F15K) according

to #37 (H-OUT) output waveform.

3. Set subaddress (00) data to 00H, 41H, 81H, C0H, and C1H. Measure horizontal free-run

frequency F28K, F31K, F33K, F37K, and F45K as in the step 2 above.

HB03 Horizontal

oscillation

frequency variable
range

1. Set subaddress (00) data to 01H.

2. Connect

10-k

resistor between #44 and V

. Measure horizontal frequency (F15K

MIN

)

according to #37 (H-OUT) output waveform.

3. Connect

68-k

resistor between #44 and GND. Measure horizontal frequency (F15K

MAX

)

according to #37 (H-OUT) output waveform.

4. Set subaddress (00) data to 00H, 41H, 81H, C0H, and C1H. Repeat the steps 2 and 3 above

and measure horizontal frequencies F28K

MIN

, F28K

MAX

, F31K

MIN

, F31K

MAX

, F33K

MIN

F33K

MAX

, F37K

MIN

, F37K

MAX

, F45K

MIN

, and F45K

MAX

HB04 Horizontal

oscillation

control sensitivity

Set SW44 to open.

Connect external power supply to TP44, and set subaddress (00) data to 01H.

3. Apply

+ 0.05 V, and V

- 0.05 V to TP44. Measure frequencies FA and FB according to

#37 (H-OUT) output waveform. Calculate frequency change rate (BH15K) using the following
equation.
BH15K

= (FB - FA)/0.1

Set subaddress (00) data to 00H, 41H, 81H, C0H, and C1H. Repeat the step 2 above, and
measure frequency change rate BH28K, BH31K, BH33K, BH37K, and BH45K

HB05 H-OUT

output

voltage

1. Set SW37 to open.

2. Measure voltage at High (V37

) and Low (V37

) of #37 (H-OUT) output waveform.

#37 waveform

T1 T2

TA1360AFG

2003-01-21

102

Note Characteristics

Test

Conditions

V01

VP output pulse
width, Vertical
free-run (maximum
pull-in range)

1. Input signal D (shown in the figure below) to TP50, and signal E (shown in the figure below) to

#39 (FBP input).

2. Measure VP output pulse width (VPw) according to TP35 output waveform.

3. Measure VP pull-in range (VPt0) according to TP35 output waveform.

4. Set subaddress (03) data to 01H, 02H, 03H, 04H, 05H, and 06H. Measure pull-in range VPt1,

VPt2, VPt3, VPt4, VPt5, and VPt6 as in the step 3 above.

V02 Vertical

minimum

pull-in range

1. Repeat the step 1 of Note #V01.

2. Input signal F (shown in the figure below) to TP52.

3. Increase signal-F cycle from 30 H. Measure the cycle (T

VPULL

) when phase locks with that of

TP35.

Signal F (TP 52
waveform input)

VPULL

#39
input waveform

TP 35 waveform

#39
input waveform

VPt

TP35 waveform

VPw

Signal E
(#39 input waveform)

9 V

GND

5.6

µs

Signal D
(TP50 input signal)

4 V

2.35

µs

29.63

µs

TA1360AFG

2003-01-21

103

Note Characteristics

Test

Conditions

V03

Vertical black peak
detection pulse

1. Repeat the step 1 of Note #V01. Set SW70 to C, and SW68 to C.

2. Input signal F (shown in the figure below) to TP52.

3. Measure phase differences VBPP

and VBPP

according to #47 output waveform.

4. Set subaddress (03) data to 01H, 02H, 03H, 04H, 05H, and 06H. Measure phase differences

VBPP

, VBPP

VBPP

, VBPP

, and VBPP

as in the step 3 above.

V04 Vertical

blanking

stop

phase

1. Repeat the step 1 of Note #V01.

2. Input signal F (shown in the figure below) to TP52.

3. Set subaddress (03) data to 00H and F0H. Measure blanking stop phase VBLK

MIN

and

VBLK

MAX

according to #12 output waveform.

Signal F (TP 52
waveform input)

1125H

#39
input waveform

#12
input waveform

VBLK

Signal F (TP 52
waveform input)

262.5H to 1125H

VBPP

#39
input waveform

#70 waveform

TA1360AFG

2003-01-21

106

Test Circuit

0.1

µF

30 pF

µF

100 k

TA1360AFG

#64

#58

#54

#51

HVC

AFC F

I
L

DEF

/
D

C V

SCP I

HD I

SYNC I

COL

R L

I
MI

Y2 I

DET

I
L

H-

FREQ S

VSM

I
LTE

H-

FREQ S

VD I

CP OU

0.47

µF

100

µF

#70

#74

(ANALOG OSD)

/P-MUTE/BLK

ABCL IN

VSM OUT

Y/C V

APL FILTER

DARK AREA DET FILTER

BPH FILTER

Y1 IN

Y/C GND

#40

1 k

µF

ANALOG G IN

ANALOG B IN

L GND

SDA

SCL

L V

DAC1 (SYNC OUT)

VP OUT

DEF/DAC GND

FBP IN

H CURVE

CORRECTION

H-OUT

ANAL

OG R

I
N

ANAL

OG O

G I

ANAL

OG OSD

R I

B V

B O

R O

B GN

G S/

R S/

3 (

2 (

)

B S/

G OUT

ANAL

OG OSD

I
N

DAC2

(

(9 V)

9 k

µF

2 k

1 k

TPA

µF

#67

TP67

#66

0.1

µF

TP66

0.1

µF

0.1

µF

0.1

µF

#63

#61

#60

#57

#55

30 k

SW INPUT

#53 #52

#50

#49

#47

#44

3 k

#42

SBLA

503KE

#41

15 k

TPB

9 k

µF

2 k

1 k

TPC

TPD

TP71

#71

µF

2 k

20 k

SW74

0.01

µF

#75

SW77

1 k

#77

0.01

µF

#78

100 k

TP78

#79

#80

100

A
B

SW40

10 k

5.1 k

470

A
B

TP26

SW26

0.1

µF

#26

A
B

TP25

SW25

0.1

µF

#25

TP28

30 k

TP30

TP35

#28

#30

#31

#34

#35

3.9 k

SW37

SW39a

SW39B

#12

#13

#14

10 k

#16

#18

#19

#21

#24

#23

10 k

38BP

51 k

µF

00 pF

1 k

50 k

00 p

5 k

50 k

45 kH

38BP

51 k

µF

00 pF

1 k

00 p

5 k

50 k

31.

.
7

38BP

51 k

µF

00 p

1 k

00 pF

5 k

50 k

15.

75 k

(9 V)

1 k

#39

TP40b

2.0 V

220

8 V

#37

20 k

SW70

SW68

SW67

SW66

SW71

TP77

TA1360AFG

2003-01-21

107

Application Circuit

R OU

G OU

B OU

0.01

µF

TA1360AFG

HVC

AFC F

I
L

DEF

/
D

C V

SCP I

HD I

SYNC I

COL

R L

I
MI

Y2 I

DET

I
L

H-

FREQ S

VSM

I
LTE

H-

FREQ S

VD I

CP OU

100

µF

(ANALOG OSD)

/P-MUTE/BLK

ABCL IN

VSM OUT

Y/C V

APL FILTER

DARK AREA DET FILTER

BPH FILTER

Y1 IN

Y/C GND

ANALOG G IN

ANALOG B IN

L GND

SDA

SCL

L V

DAC1 (SYNC OUT)

VP OUT

DEF/DAC GND

FBP IN

H CURVE

CORRECTION

H-OUT

ANALOG R

I
N

ANAL

OG OSD

I
N

ANAL

OG OSD

R I

B V

B O

R O

B GN

G S/

R S/

3 (

2 (

)

B S/

G OUT

ANAL

OG OSD

I
N

DAC2

(

2.2

µF

0.1

µF

0.1

µF

VD-

I
N

CP-

SBLA

503KE

9 k

µF

1 k

0.01

µF

0.01

µF

100 k

ABCL

Ys1

470

ANALOG B IN

0.1

µF

ANALOG G IN

0.1

µF

SDA

30 k

SCL

30 k

2.0 V

8 V

µH

100 k

0.1

µF

9 k

µF

1 k

9 k

µF

1 k

Y1 IN

µF

0.47

µF

3 k

SCP-

I
N

-
I
N

9 k

µF

1 k

9 k

µF

1 k

Y2-IN

9 k

µF

1 k

10 k

1 k

30 k

SYNC IN

9 k

µF

1 k

5 k

µ H

VSM OUT

-
I
N

OSD

R-

I
N

OSD

G-

I
N

OSD

B-

I
N

ANALOG R

-
I
N

DAC2

-
O

DAC1-OUT

VP-OUT

H-OUT

FBP-IN

CURVE CORR

: Mylar capacitor

Application of H-FREQ switching (31.5 k/33.75 k/45 kHz)

Tr.

H-FREQ

A B

voltage Pin 41 voltage

31.5 kHz

9 V

6 V

33.75 kHz

9 V

3 V

45 kHz

9 V

0 V

*: Don't care

TA1360AFG

2003-01-21

110

· TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor

devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability
Handbook" etc..

· The TOSHIBA products listed in this document are intended for usage in general electronics applications

(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer's own risk.

· The products described in this document are subject to the foreign exchange and foreign trade laws.

· The information contained herein is presented only as a guide for the applications of our products. No

responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.

· The information contained herein is subject to change without notice.

000707EBA

RESTRICTIONS ON PRODUCT USE

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