TB62201AFG

2005-04-04

TOSHIBA Bi-CMOS Processor IC Silicon Monolithic

TB62201AFG

Dual-Stepping Motor Driver IC for OA Equipment Using PWM Chopper Type

The TB62201AFG is a dual-stepping motor driver driven by
chopper micro-step pseudo sine wave.
To drive two-phase stepping motors, Two pairs of 16-bit latch and
shift registers are built in the IC. The IC is optimal for driving
stepping motors at high efficiency and with low-torque ripple.
The IC supports Mixed Decay mode for switching the attenuation
ratio at chopping. The switching time for the attenuation ratio
can be switched in four stages according to the load.

Features

Two stepping motors driven by micro-step pseudo sine wave
are controlled by a single driver IC

Monolithic Bi-CMOS IC

Low ON-resistance of Ron = 0.5 (T

= 25癈 @ 1.0 A: typ.)

ESD protection Exceeds 2000 V, MIL-STD-883D

Two pairs of built-in 16-bit shift and latch registers

Two pairs of built-in 4-bit DA converters for micro steps

Built-in ISD, TSD, V

power monitor (reset) circuit for protection

Built-in charge pump circuit (two external capacitors)

36-pin power flat package (HSOP36-P-450-0.65)

Output voltage: 40 V max

Output current: 1.5 A/phase max

Built-in Mixed Decay mode enables specification of four-stage attenuation ratio.
(The attenuation ratio table can be overwritten externally.)

Chopping frequency can be set by external resistors and capacitors. High-speed chopping possible at 100 kHz or
higher.

Note: When using the IC, pay attention to thermal conditions.

These devices are easy damage by high static voltage.
In regards to this, please handle with care.

Weight: 0.79 g (typ.)

TB62201AFG

2005-04-04

Block Diagram

1. Overview (Power lines: A/B unit (C/D unit is the same as A/B unit))

Current feedback circuit

Protected circuit

TSD

circuit

DDR

circuit

Current Setting

Mixed decay timing, table logic circuit

4-bit D/A

(angle control)

Torque

control

COMP

circuit 1

Output control circuit

Stepping

motor

16-bit shift

High-Voltage Wiring (V

)

Logic data

Analog data

IC Terminal

ref

DATA

Charge

pump

circuit

Output circuit

(H-bridge)

Chopping

waveform

generator

circuit

Waveform

shaping

circuit

Chopping reference
circuit

RESET

16-bit latch

Mixed decay

timing table

selector

16-bit latch

16-bit shift

Current control data logic circuit

DATA

input

selector

SETUP

CLK

STROBE

COMP

circuit 2

circuit 1

circuit 2

cp1

cp2

ISD

circuit

Out X

TB62201AFG

2005-04-04

2. Logic Unit A/B (C/D unit is the same as A/B unit)

Function

This circuit is used to input from the DATA pins micro-step current setting data and to transfer them to the
subsequent stage. By switching the SETUP pin, the data in the mixed decay timing table can be
overwritten.

Note: The RESET and SETUP pins are pulled down in the IC by 10 k

resistor.

When not using these pins, connect them to GND. Otherwise, malfunction may occur.

Initial

setup

circuit

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Mixed
decay
timing

table 1

Mixed decay timing table logic circuit

Mixed
decay
timing

table 2

Mixed
decay
timing

table 3

Mixed
decay
timing

table 4

Mixed
decay
timing

table selector

16-bit latch

Mixed
decay
timing

Output
control
circuit

16-bit shift register

Current feedback circuit

D/A circuit

Torque

�

2 bits

Decay

�

2 bits

B unit side

Current

�

4 bits

B unit side

Phase

�

1 bit

B unit side

Output control circuit

CLK

STROBE

DATA

RESET

SETUP

Data input
selector

16-bit shift register

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

16-bit latch

A unit side

Micro-step current setting data logic circuit

TB62201AFG

2005-04-04

3. Current Feedback Circuit and Current Setting Circuit

(A/B unit (C/D unit is the same as A/B unit))

Function

The current setting circuit is used to set the reference voltage of the output current using the micro-step
current setting data input from the DATA pins.
The current feedback circuit is used to output to the output control circuit the relation between the set
current value and output current. This is done by comparing the reference voltage output to the current
setting circuit with the potential difference generated when current flows through the current sense
resistor connected between RS and V

The chopping waveform generator circuit to which CR is connected is used to generate clock used as
reference for the chopping frequency.

Note 1: RS COMP 1: Compares the set current with the output current and outputs a signal when the output current

reaches the set current.

Note 2: RS COMP 2: Compares the set current with the output current at the end of Fast mode during chopping.

Outputs a signal when the set current is below the output current.

100%

85%
70%
50%

circuit 1

(detects

potential

difference

between

and V

)

COMP

circuit 1

(Note 1)

(set current

reached signal)

circuit 2

(detects

potential

difference

between

and R

)

COMP

circuit 2

(Note 2)

RNF

(set current

monitor signal)

Use in Fast mode

Use in Charge mode

Output
control

circuit

Mixed
decay
timing
circuit

Output stop signal (ALL OFF)

Chopping reference circuit

Current feedback circuit

TORQUE

control

circuit

Current setting circuit

TORQUE

0, 1

CURRENT

0 to 3

Logic

unit

15
14
13
12
11
10

9
8
7
6
5
4
3
2
1
0

Micro-step

current

setting

selector

circuit

4-bit

D/A

circuit

ref

Waveform shaping circuit

wavefor

generat

cir

c
uit

TB62201AFG

2005-04-04

4. Output Control Circuit, Current Feedback Circuit and Current Setting Circuit

(A/B unit (C/D unit is the same as A/B unit))

Note: The RESET pins is pulled down in the IC by 10-k

resistor.

When not using the pin, connect it to GND. Otherwise, malfunction may occur.

ISD (current

shutdown)

circuit

Output pin

circuit

DDR

circuit

Thermal

shut down

(TSD)

circuit

Charge pump

circuit

Ccp A

Logic

DDR

: V

power on Reset

: V

power on Reset

ISD: Current shutdown circuit
TSD: Thermal shutdown circuit

Protection circuit

Charge pump

circuit

Micro-step

current

setup latch clear

signal

Mixed decay

timing table
clear signal

Ccp B

Ccp C

Output reset signal

Output
circuit

Charge

pump

halt

signal

Power supply

for upper

output MOS

transistors

Reset signal

selector

circuit

Current

feedback

circuit

Current

setting

circuit

counter

CR counter

Chopping

reference circuit

Micro-step current setting

data logic circuit

Output control circuit

Phase

Decay

mode

Mixed
decay
timing
circuit

Output
circuit

Output stop
signal

Mixed
decay
timing

charge start

RESET

NF
set current
reached signal

RNF
set current
monitor signal

Output control circuit

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2005-04-04

Pin Assignment

Note: [Important] If this IC is inserted reverse, voltages exceeding the voltages of standard may be applied to some

pins, causing damage.
Please confirm the pin assignment before mounting and using the IC.

M B

OUT B

PGND

OUT B

SETUP

Ccp A

REF AB

)

REF CD

Ccp B

Ccp C

OUT D

PGND

S D

OUT D

TB62201AFG

(Top view)

M A

OUT A

PGND

OUT A

STROBE AB

CLK AB

DATA AB

RESET

)

DATA CD

CLK CD

STROBE CD

OUT C

PGND

S C

OUT C

TB62201AFG

2005-04-04

Pin Description

Pin No.

Pin Symbol

Description

1 V

M B

Voltage major for output B block

OUT B

Output B pin

3 R

S B

Channel B current pin

4 PGND

Power

GND

OUT Output

B pin

SETUP

CR setup switching pin (L: normal, H: setup)

7 C

Capacitor pin for charge pump (Ccp1)

External C/R (osc) pin (sets chopping frequency)

9 V

REF AB

ref

input pin AB

): Logic GND pin

10 V

REF CD

Vref input pin CD

11 NC

Non

conection

12 C

Capacitor pin for charge pump (Ccp2)

13 C

Capacitor pin for charge pump (Ccp2)

OUT

Output

D pin

15 PGND

Power

GND

16 R

S D

Channel D current pin

OUT D

Output D pin

18 V

M D

Voltage major for output D block

19 V

M C

Voltage major for output C block

OUT

Output

C pin

21 R

S C

Channel C current pin

22 PGND

Power

GND

OUT C

Output C pin

STROBE CD

CD STROBE (latch) signal input pin ( : LATCH)

CLK CD

CD clock input pin

DATA CD

CD serial data signal input pin

27 V

Power pin for logic block

) : Logic GND pin

RESET

Output reset signal input pin (L: RESET)

DATA AB

AB serial data signal input pin

CLK AB

AB clock input pin

STROBE AB

AB STROBE (latch) signal input pin ( : LATCH)

OUT A

Output A pin

33 PGND

Power

GND

34 R

S A

Channel A current pin

OUT

Output

A pin

36 V

M A

Voltage major for output A block

Note: How to handle GND pins

All power GND pins and FIN (V

: signal GND) pins must be grounded.

Since FIN also functions as a heat sink, take the heat dissipation into consideration when designing the board.

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2005-04-04

Signal Functions

1. Serial Input Signals

(for A/B. C/D is the same as A/B)

Data No.

Name

Functions

0 LSB

TORQUE 0

1 TORQUE

DATA No.0, 1

= HH: 100%, LH: 85%

HL: 70%, LL: 50%

DECAY MODE B

00: DECAY MODE 0, 01: DECAY MODE 1
10: DECAY MODE 2, 11: DECAY MODE 3

4 Current

5 Current

6 Current

7 Current

Used for setting current.
(LLLL

= Output ALL OFF MODE)

4-bit current B data
(Steps can be divided into 16 by 4-bit data)

PHASE B

Phase information (H: OUT A: H, OUT A: L)

DECAY MODE A

00: DECAY MODE 0, 01: DECAY MODE 1
10: DECAY MODE 2, 11: DECAY MODE 3

11 Current

12 Current

13 Current

14 Current

Used for setting current.
(LLLL

= Output ALL OFF MODE)

4-bit current A data
(Steps can be divided into 16 by 4-bit data)

15 MSB

PHASE A

Phase information (H: OUT A: H, OUT

: L)

Note 1: Serial data input order

Serial data are input in the order LSB (DATA 0)
MSB (DATA 15)

Role of Data

Data Name

Number of Bits

Functions

TORQUE 2

Roughly regulates the current (four stages).
Common to A and B units.

DECAY MODE

� 2 phases

Selects Decay mode.
A and B units are set separately.

CURRENT 4

� 2 phases

Sets a 4-bit micro-step electrical angle.
A and B units are set separately.

PHASE 1

� 2 phases

Determines polarity (

+ or -).

A and B units are set separately.

(Note 1)

TB62201AFG

2005-04-04

2. Serial Input Signal Functions

Input Action

CLK STROBE DATA RESET

VDDR

(Note 2) or

Operation of

TSD/ISD

(Note 2)

�

� H H L

No change in shift register.

� H H H L

H level is input to shift register.

� L H H L

L level is input to shift register.

�

� H H L

Shift register data are latched.

�

� H H L

�

� L � L

Output off, charge pump halted
(S/R DATA CLR)

�

� L L

Output off (S/R DATA CLR)
Charge pump halted
Mixed decay timing table cleared (only V

DDR

)

�

� H H H

Output off (S/R DATA HOLD)
Charge pump halted
Restored when RESET goes from Low to High

�: Don't

Care

Qn:

Latched output level when STROBE is .

Note 1: V

DDR

and V

H when the operable range (3 V typical) or higher and L when lower.
When one of V

DDR

or V

is operating, the system resets (OR relationship).

Note 2: High when TSD is in operation.

When one of TSD or ISD is operating, the system resets (OR relationship).

Note:

Function of overcurrent protection circuit
Until the RESET signal is input after ISD is triggered, the overcurrent protection circuit remains in operation.
During ISD, the charge pump stays halted.
When TSD and ISD are operating, the charge pump halts.

3. PHASE

Functions

Input Function

Positive polarity (A: H, : L)

Negative polarity (A: L, : H)

TB62201AFG

2005-04-04

4. DECAY Mode X0, X1 Functions

DECAY MODE X1

DECAY MODE X0

Function

L L

Decay mode 0
(Initial value: SLOW DECAY MODE)

L H

Decay mode 1
(Initial value: MIXED DECAY MODE: 37.5%)

H L

Decay mode 2
(Initial value: MIXED DECAY MODE: 75%)

H H

Decay mode 3
(Initial value: FAST DECAY MODE)

5. TORQUE

Functions

TORQUE 0

TORQUE 1

Comparator Reference Voltage Ratio

H H

100%

L H

85%

H L

70%

L L

50%

6. Current

(BX)

Functions

Step

Set Angle

90.0 H H H H L L L L

84.4 H H H H L L L H

78.8

H H H L L L H L

73.1

H H L H L L H H

67.5

H H L L L H L L

61.2

H L H H L H L H

56.3

H L H L L H H L

9 50.6

H L L H L H H H

8 45.0

H L L L H L L L

7 39.4 L H H H H L L H

6 33.8 L H H L H L H L

5 28.1 L H L H H L H H

4 22.5 L H L L H H L L

3 16.9 L L H H H H L H

2 11.3 L L H L H H H L

1 5.6 L L L H H H H H

0 0.0 L L L L H H H H

By inputting the above current data (A: 4-bit, B: 4-bit), 17-microstep drive is possible. For 1 step fixed to 90
degrees, see the section on output current vector line (83 page).

TB62201AFG

2005-04-04

7. SETUP

Functions

Input Function

Decay timing data input mode

Normal operating mode

Note: The SETUP pin is pulled down in the IC by 10-k

resistor.

8. Serial Data Input Setting

(Normal operation)

SETUP pin: L

Note: Data input to the DATA pin are 16-bit serial data.

Data are transferred from DATA 0 (Torque 0) to DATA 15 (Phase A). Data are input and transferred at the
following timings.
At CLK falling edge: data input
At CLK rising edge: data transfer
After data are transferred, all data are latched on the rising edge of the STROBE signal.
As long as STROBE is not rising, the signal can be either Low or High during data transfer.

9. Serial Data Input Setting

(Decay timing setup)

SETUP pin: H

Note: Data input to the DATA pin are 16-bit serial data.

� Data are transferred from DATA 0 (Current Mode 1) to DATA 15 (DECAY MODE X-4). Data are input and

transferred at the following timings.

� At CLK falling edge: data input
� At CLK rising edge: data transfer
� After data are transferred, all data are latched on the rising edge of the STROBE signal.

As long as STROBE is not rising, the signal can be either Low or High during data transfer.

DATA

CLK

STROBE

DATA

CLK

STROBE

TB62201AFG

2005-04-04

10. Conditions on Overwriting MIXED DECAY TIMING Table

If the following conditions are satisfied, the table can be overwritten.

� When RESET = H (when RESET = L, the shift register is cleared, thus data cannot be input)
� When an internal reset is not triggered.

1) When the temperature is such that TSD is not triggered (or not reset by TSD).
2) Under a condition where ISD is not triggered (or not reset by ISD).
3) Both V

and V

are within the operating voltage.

Note 1: While the output transistors are operating, do not rewrite the values in the mixed decay timing

table.

Note 2: The SETUP pins is pulled down in the IC by 10-k

resistor

When not using the pin, connect it to GND. Otherwise, malfunction may occur.

11. Data Input Signal at Setting Mixed Decay Timing Table

Data No.

Name

Function

Initial Value

15 MSB

Current Mode 3

Selects Slow or Mixed Decay mode

1 : MIXED DECAY MODE

DECAY MODE 3-2

Sets decay 3 ratio (decay 3 raito)

13 DECAY

MODE

3-1

12 DECAY

MODE

3-0

1 : 100% : FAST DECAY MODE

Current Mode 2

Selects Slow or Mixed Decay mode

1 : MIXED DECAY MODE

DECAY MODE 2-2

Sets decay 2 ratio

9 DECAY

MODE

2-1

8 DECAY

MODE

2-0

1 : 75% MIXED DECAY

Current Mode 1

Selects Slow or Mixed Decay mode

1 : MIXED DECAY MODE

DECAY MODE 1-2

Sets decay 1 ratio

5 DECAY

MODE

1-1

4 DECAY

MODE

1-0

0 : 37.5% MIXED DECAY

Current Mode 0

Selects Slow or Mixed Decay mode

0 : SLOW DECAY MODE

DECAY MODE 0-2

Sets decay 0 ratio

1 DECAY

MODE

0-1

0 LSB

DECAY MODE 0-0

0 (SLOW DECAY MODE)

Note 1: Input order of serial data

When setting decay timing, first input H to the SETUP pin, the same as for ordinary data, then
input data from LSB (DATA 0) to MSB (DATA 15).

When power is first turned on, the initial values in the table above are set as defaults.
Once latched, data are not cleared except by VDDR (power-on and power-off reset).
Next, after the mode changes to SETUP, the data are retained until mixed decay timing data are input and
latched.

TB62201AFG

2005-04-04

12. Function of Setting Mixed Decay Timing

CURRENT

MODE X

DECAY MODE

X-2

DECAY MODE

X-1

DECAY MODE

X-0

MIXED DECAY TIMING

Don't care

(SLOW DECAY MODE)

H L L L

12.5%

H L L H

25.0%

H L H L

37.5%

H L H H

50.0%

H H L L

62.5%

H H L H

75.0%

H H H L

87.5%

H H H H

100%

(FAST DECAY MODE)

Mixed decay timing means the time for switching Slow mode to Fast mode in MIXED DECAY MODE.
In Mixed Decay mode, the Fast mode time at the end of chopping Cycle (T

chop

) is fixed by data.

The IC is switched from Slow to Fast mode according to the percentage representing mode time in the table
above.
(For example, 12.5% means that 12.5% of the time is in Fast mode and the rest of the time, 87.5%, in
Charge and Slow modes.)
Only when the value is maximum (100%), the mode is Fast Decay mode.

TB62201AFG

2005-04-04

Maximum Ratings

(Ta

= 25癈)

Characteristics Symbol

Rating

Unit

Logic supply voltage

7 V

Output voltage

Output current

OUT

1.5

A/phase (Note

Current detect pin voltage

� 4.5

Charge pump pin maximum voltage
(CCP1 pin)

+ 7.0

Logic input voltage

+ 0.4

1.4 W

(Note

Power dissipation

3.2 W

(Note

Operating temperature

opr

-40 to 85

癈

Storage temperature

stg

-50 to 150

癈

Junction temperature

150

癈

Note 1: Perform thermal calculations for the maximum current value under normal conditions. Use the IC at 1.2 A or

less per phase.

Note 2: Input 7 V or less as V

Note 3: Measured for the IC only. (Ta

= 25癈)

Note 4: Measured when mounted on the board. (Ta

= 25癈)

Ta: IC ambient temperature
T

opr

: IC ambient temperature when starting operation

: IC chip temperature during operation T

(max) is controlled by TSD (thermal shut down circuit)

Recommended Operating Conditions

(Ta

= 0 to 85癈)

Characteristics Symbol Test

Condition Min

Typ.

Max

Unit

Power supply voltage

4.5 5.0 5.5 V

Output voltage

= 5.0 V

OUT (1)

= 25癈, per phase

(when one motor is driven)

1.1 1.3 A

Output current

OUT (2)

= 25癈, per phase

(when two motors are driven)

1.1 1.3 A

Logic input voltage

GND

Clock frequency

CLK

= 5.0 V

1.0

6.25

MHz

Chopping frequency

chop

= 5.0 V

100

150

kHz

Reference voltage

ref

= 24 V, T

orque

= 100%

2.0

3.0

Current detect pin voltage

= 5.0 V

�1.0

�1.5

Note: Use the Maximum Junction Temperature (T

) at 120癈 or less

TB62201AFG

2005-04-04

Electrical Characteristics 1

(unless otherwise specified, Ta

= 25癈, V

= 5 V, V

= 24 V)

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

High V

(H)

2.0

+ 0.4

Input voltage

Low V

(L)

1 CLK,

RESET , STROBE, DATA pins

GND

- 0.4

GND 0.8

IN1

(H)

1.0

Input current 1

IN1

(L)

CLK, STROBE, DATA pins

1.0

礎

IN2

(H)

700

Input current 2

IN2 (L)

RESET

, SETUP pins

700

礎

DD1

= 5 V (STROBE,

RESET

DATA

= L),

RESET

= L,

Logic, output all off

3.0 6.0

Power dissipation (V

pin)

DD2

Output OPEN, f

CLK

= 6.25 MHz

LOGIC ACTIVE, V

= 5 V,

Charge Pump

= charged

4.0 80

Output OPEN (STROBE,

RESET

DATA

= L),

RESET

= L,

Logic, output all off
Charge Pump

= no operation

5.0 6.0

Output OPEN, f

CLK

= 6.25 MHz

LOGIC ACTIVE, V

= 5 V,

= 24 V, Output off

Charge Pump

= charged

12 20

Power dissipation (V

pin)

Output OPEN, f

CLK

= 6.25 MHz

LOGIC ACTIVE, 100 kHz
chopping (emulation), Output OPEN,
Charge Pump

= charged Ccp1 = 0.22

礔, Ccp2

= 0.01礷

30 40

Output standby
current

Upper I

= V

= 24 V, V

out

= 0 V,

RESET

= H, DATA = ALL L

-400

Output bias current

Upper

= V

= 24 V, V

out

= 24 V,

RESET

= H, DATA = ALL L

-200

Output leakage
current

Lower I

= V

= CcpA = V

out

=24 V,

RESET

= L

1.0

礎

High

(reference)

RS (H)

ref

= 3.0 V, V

ref

(Gain)

= 1/5.0

TORQUE

= (H.H) = 100% set

100

Mid high

RS (MH)

ref

= 3.0 V, V

ref

(Gain) = 1/5.0

TORQUE

= (H.L) = 85% set

83 85 87

Mid low

RS (ML)

ref

= 3.0 V, V

ref

(Gain)

= 1/5.0

TORQUE

= (L.H) = 70% set

68 70 72

Comparator
reference voltage
ratio

Low V

RS (L)

ref

= 3.0 V, V

ref

(Gain)

= 1/5.0

TORQUE

= (L.L) = 50% set

48 50 52

Output current differential

out1

Differences between output current
channels
I

out

= 1000 mA

-5

5 %

Output current setting differential

out2

out

= 1000 mA

-5

5 %

RS pin current

IRS

VRS

= 24 V, V

= 24 V,

RESET

= L

(RESET status)

10 礎

TB62201AFG

2005-04-04

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

ON (D-S) 1

out

= 1.0 A, V

= 5.0 V

= 25癈, Drain-Source

0.5 0.6

ON (D-S) 1

out

= 1.0 A, V

= 5.0 V

= 25癈, Source-Drain

0.5 0.6

ON (D-S) 2

out

= 1.0 A, V

= 5 V,

= 105癈, Drain-Source

0.6 0.75

Output transistor drain-source
on-resistance

ON (D-S) 2

out

= 1.0 A, V

= 5 V,

= 105癈, Source-Drain

0.6 0.75

Electrical Characteristics 2

(unless otherwise specified, Ta

= 25癈, V

= 5 V, V

= 24 V)

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

ref

input voltage

ref

= 24 V, V

= 5 V,

RESET

= H, Output on

2.0

ref

input current

ref

RESET

= H, Output off

= 24 V, V

= 5 V,

ref

= 3.0 V

100

ref

attenuation ratio

ref

(GAIN)

= 24 V, V

= 5 V,

RESET

= H, Output on,

ref

= 2.0 to V

- 1.0 V

1/4.8 1/

5.0 1/5.2

TSD temperature

TSD

(Note 1)

11 V

= 5 V, V

= 24 V

130

170

癈

TSD return temperature difference

TSD 11

TSD = 130 to 170癈

TSD

-35

癈

return voltage

DDR

= 24 V, RESET = H,

STROBE

= H

2.0

4.0 V

return voltage

= 5 V,

RESET

= H,

STROBE

= H

2.0

4.0 V

Over current protected circuit
operation current

(Note 2)

= 5 V, V

= 24 V,

fchop

= 100 kHz set

2.6 A

Note 1: Thermal shut down (TSD) circuit

When the IC junction temperature reaches the specified value and the TSD circuit is activated, the internal
reset circuit is activated switching the outputs of both motors to off.
When the temperature is set between 130 (min) to 170癈 (max), the TSD circuit operates. When the TSD
circuit is activated, the function data latched at that time are cleared. Output is halted until the reset is
released. While the TSD circuit is in operation, the charge pump is halted.
Even if the TSD circuit is activated and RESET goes H

L H instantaneously, the IC is not reset until

the IC junction temperature drops 35癈 (typ.) below the TSD operating temperature (hysteresis function).

Note 2: Overcurrent protection circuit

When current exceeding the specified value flows to the output, the internal reset circuit is activated
switching the outputs of both shafts to off.
When the ISD circuit is activated, the function data latched at that time are cleared.
Until the RESET signal is input, the overcurrent protection circuit remains activated.
During ISD, the charge pump halts.
For failsafe operation, be sure to add a fuse to the power supply.

TB62201AFG

2005-04-04

Electrical Characteristics 3

(Ta

= 25癈, V

= 5 V, V

= 24 V, I

out

= 1.0 A)

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

A = 90 (16)

100

A = 84 (15)

100

A = 79 (14) 93

A = 73 (13) 91

A = 68 (12) 87

A = 62 (11) 83

A = 56 (10) 78

A = 51 (9) 72

A = 45 (8) 66

A = 40 (7) 58

A = 34 (6) 51

A = 28 (5) 42

A = 23 (4) 33

A = 17 (3) 24

A = 11 (2) 15

A = 6 (1) 5

Chopper current

Vector

A = 0 (0)

TB62201AFG

2005-04-04

AC Characteristics

(Ta

= 25癈, V

= 24 V, V

= 5 V, 6.8 mH/5.7

)

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

Clock frequency

CLK

1.0

25 MHz

(CLK)

Minimum clock pulse width

wn (CLK)

STROBE

STROBE (H)

Minimum STROBE pulse width

STROBE (L)

suSIN-CLK

Data setup time

suST-CLK

Hsin-CLK

Data hold time

hCLK-ST

0.1

Output Load; 6.8 mH/5.7

0.1

pLH (ST)

pHL (ST)

STROBE () to VOUT
Output Load; 6.8 mH/5.7

pLH (CR)

1.2

Output transistor switching
characteristic

pHL (CR)

CR to VOUT
Output Load; 6.8 mH/5.7

2.5

祍

Noise rejection dead band time

BLNK

out

= 1.0 A

200

300

400

CR reference signal oscillation
frequency

osc

= 560 pF, R

osc

= 3.6 k

736 kHz

Chopping frequency range

chop (min)

chop (typ.)

chop (max)

Output active (I

out

= 1.0 A)

Step fixed, Ccp1

= 0.22 礔,

Ccp2

= 0.01 礔

40 100 150

kHz

Chopping frequency

chop

Output active (I

out

= 1.0 A)

CR CLK

= 800 kHz

100 kHz

Charge pump rise time

ONG

Ccp2

= 0.22 礔, Ccp = 0.01 礔

= 24 V, V

= 5 V,

RESET

= L H

2 4 ms

TB62201AFG

2005-04-04

Calculation of Set Current

Determining R

and V

ref

determines the set current value.

out

(max)

(GAIN)

ref

� V

ref

(V) �

)

(

)

orque

data

serial

input

50%

70,

85,

100,

1/5.0 is V

ref

(gain): V

ref

attenuation ratio (typ.).

For example,

to input V

ref

3 V and Torque

100% and to output I

out

0.8 A,

0.75 (0.5 W or more) is required.

Formulas for Calculating CR Oscillation Frequency

(Chopping reference frequency)

The CR oscillation frequency and f

chop

can be calculated by the following formulas:

�

[Hz]

KA (constant): 0.523

KB (constant): 600

chop

[Hz]

Example: When Cosc = 1,000 pF and Rosc = 2.0 k are connected, f

= 735 kHz.

At this time, the chopping frequency f

chop

is: f

chop

= f

/8 = 92 kHz.

Note: f

Charge)

(Dis

(Charge)

CR oscillation CR charge

CR distance

cycle

time

At this time, t (CR

- discharge) is subject to the following condition :

600

> t (CR - discharge) > 400 ns.

Be sure to set the CR value in accordance with this condition.

TB62201AFG

2005-04-04

CR Circuit Constants

OSC circuit oscillation waveform

The OSC circuit generates the chopping reference signal by charging and discharging the external capacitor Cosc
through current supplied from the external resistor Rosc in the OSC block.
Voltages E1 and E2 in the diagram are set by dividing the V

by approximately 3/5 (E1) and 2/5 (E2).

The actual current chopping time is 1/8 the CR frequency.

[Important: Setting the cr circuit constants]

The CR oscillation waveform is converted in the IC to the CLK waveform (CR-CLK signal) and used for control.
If the CR waveform discharge time is set outside the range shown below, the operation of the IC is not guaranteed.
Be sure to set the CR waveform discharge time within the following range.

600 ns > t (CR discharge) > 400 ns

= 0

= 1

= 2

t (CR

- charge)

t (CR

- dis-charge)

TB62201AFG

2005-04-04

IC Power Dissipation

IC power dissipation is classified into two: power consumed by transistors in the output block and power consumed
by the logic block and the charge pump circuit.

(1) Power consumed by the Power Transistor (calculated with R

= 0.6 )

In Charge mode, Fast Decay mode, or Slow Decay mode, power is consumed by the upper and lower transistors
of the H bridges. The following expression expresses the power consumed by the transistors of a H bridge.

(out)

= 2 (T

) � I

out

(A) � V

(V) = 2 � I

out

^2 � R

......................................(1)

The average power dissipation for output under 4-bit micro step operation (phase difference between phases A
and B is 90�) is determined by expression (1).
Thus, power dissipation for output per unit is determined as follows (2) under the conditions below.

= 0.6 (@ 1.0 A)

out

(Peak: max) = 1.0 A

= 24 V

= 5 V

P (out) = 2 (T

) � 1.0 (A)^2 � 0.60 () ................................................................. (2)

=1.20

(W)

(2) Power consumed by the logic block and IM

The following standard values are used as power dissipation of the logic block and IM at operation.

I (LOGIC) = 2 mA (typ.): /unit
I (IM3) = 12.5 mA (typ.): operation/unit

I (IM1) = 6.0 mA (typ.): stop/unit

The logic block is connected to V

(5 V). IM (total of current consumed by the circuits connected to V

and

current consumed by output switching) is connected to V

(24 V). Power dissipation is calculated as follows :

P (Logic & IM) = 5 (V) � 0.002 (A) + 24 (V) � 0.0125 (A) .................................... (3)

= 0.31 (W)

(3) Thus, power dissipation for 1 unit (P) is determined as follows by (2) and (3) above.

P = P (out) + P (Logic & IM) = 1.51 (W)

Power dissipation for 1 unit at standby is determined as follows:

P (standby) = 24 (V) � 0.006 (A) + 5 (V) � 0.002 (A)

= 0.154 (W)

When one motor driving = 100 %, power dissipation is determined as follows:

P (all) = 1.51 (W) + 1.664 (W) = 1.66 (W)

For thermal design on the board, evaluate by mounting the IC.

TB62201AFG

2005-04-04

Mixed Decay Mode Waveforms

(concept of mixed decay mode)

In Decay modes 1 to 4, any point from A to H can be set using 3-bit + 1-bit serial data � 4.

(Slow Decay mode for Decay mode 0 in the above figure can be set by setting current Decay mode X to 0.)
NF is the point where the output current reaches the set current value. RNF is the timing for monitoring the set
current.
In Mixed Decay and Fast Decay modes, where the condition RNF (set current monitor signal) < (output current)

applies, Charge mode is cancelled at the next chopping cycle (charge cancel circuit). Therefore, at the next chopping
cycle, the IC enters Slow + Fast modes (Slow Fast at MDT).

chop

SLOW
DECAY
MODE

CR pin
input
waveform

Set current value

RNF

DECAY MODE 0

37.5%
MIXED
DECAY
MODE

RNF

Set current value

DECAY MODE 1

75%
MIXED
DECAY
MODE

RNF

Set current value

MDT

DECAY MODE 2

FAST
DECAY
MODE

RNF

Set current value

DECAY MODE 3

100% 75% 50%

25%

MDT

Slow

Charge

Slow

Fast

Monitoring
set current
value

Charge

Fast

Charge

Fast

87.5% 62.5%

37.5%

12.5%

Monitoring
set current
value

TB62201AFG

2005-04-04

Mixed Decay Timing which can be Set

Defaults for

Decay mode 0

CURRENT MODE (X)

= 0

DECAY MODE (X

- 2, X - 1, X - 0) = (�, �, �)

X: arbitrary value

12.5%

CURRENT MODE (X)

= 1

DECAY MODE (X

- 2, X - 1, X - 0) = (0, 0, 0)

MDT

RNF

25%

CURRENT MODE (X)

= 1

DECAY MODE (X

- 2, X - 1, X - 0) = (0, 0, 1)

MDT

RNF

37.5%

MDT

RNF

Defaults for

Decay mode 1

CURRENT MODE (X)

= 1

DECAY MODE (X

- 2, X - 1, X - 0) = (0, 1, 0)

50%

CURRENT MODE (X)

= 1

DECAY MODE (X

- 2, X - 1, X - 0) = (0, 1, 1)

MDT

RNF

62.5%

CURRENT MODE (X)

= 1

DECAY MODE (X

- 2, X - 1, X - 0) = (1, 0, 0)

MDT

RNF

75%

RNF

Defaults for

Decay mode 2

CURRENT MODE (X)

= 1

DECAY MODE (X

- 2, X - 1, X - 0) = (1, 0, 1)

MDT

87.5%

CURRENT MODE (X)

= 1

DECAY MODE (X

- 2, X - 1, X - 0) = (1, 1, 0)

RNF

MDT

FAST
DECAY
MODE

RNF

Defaults for

Decay mode 3

CURRENT MODE (X)

= 1

DECAY MODE (X

- 2, X - 1, X - 0) = (1, 1, 1)

FAST MODE

RNF: CURRENT MONITOR

(WHEN SET CURRENT VALUE > OUTPUT CURRENT)
CHARGE MODE

FAST MODE

chop

Internal
CR
waveform

TB62201AFG

2005-04-04

Test Circuit

(A/B unit only. C/D unit conforms to A/B unit.)

1. V

IN (H)

, V

IN (L)

Test Method

IN (H)

: Set RESET to High and vary the logic input voltage from 0 to 7 V.

Monitor I

and measure the change point (V

= 24

IN (L)

: Set RESET to High and vary the logic input voltage from 5 to 0 V.

Monitor I

and measure the change point.

Setup Data

osc AB

3.6

0.22

�

Ccp 1

0.01

�

ref AB

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

6 SETUP

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560

No reset at testing

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

DD1

, I

DD2

0 V to 5 V

Vary V

IN (H)

, I

IN (L)

RS A

RS B

DATA

CLK

STROBE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

TB62201AFG

2005-04-04

2. I

IN (H)

IN (L)

DD1

, I

DD2

(A/B unit only. C/D unit conforms to A/B unit.)

Test Method

IN (H)

: Set RESET to High, set the the logic input voltage to 5 V, and measure the input current.

IN (H)

: Set RESET to High, set the the logic input voltage to 0 V, and measure the input current.

DD1

: Apply

, input RESET, and measure I

DD2

: Input 6.25 MHz clock and measure the current when the logic is operating. Set output to OPEN.

Setup Data

osc AB

3.6

0.22

�

Ccp 1

0.01

�

ref AB

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

6 SETUP

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560

No reset at testing

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

DD1

, I

DD2

0 V to 5 V

Vary V

IN (H)

, I

IN (L)

RS A

RS B

DATA

CLK

STROBE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

TB62201AFG

2005-04-04

3. IM1, IM2 (A/B unit only. C/D unit conforms to A/B unit.)

Test Method

IM1: Set the logic block to non-active (DATA = all 0), V

= 5 V, V

= 24 V, and output to open. Measure

the current input from V

supply. RESET = L

IM2: Set the logic block only to active (CLK = 6.25 MHz), V

= 24 V, and output to open. Measure the

current input from V

supply. RESET = H

Setup Data

5 V

osc

3.6

0.22

�

Ccp 1

0.01

�

CR AB

ref

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

SETUP

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560

At IM1 testing:

RESET

= L (0 V)

At IM2 testing:

RESET

= H (5 V)

5 V
0 V
5 V
0 V

5 V
0 V

DATA

CLK

STROBE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

TB62201AFG

2005-04-04

4. IM3 (A/B unit only. C/D unit conforms to A/B unit.)

This is the IM current when all of the circuits, including the output transistors, in the IC are operating.
The IM current includes the current dissipation in the charge pump circuit, output gate loss, and output
predriver.
Because the IM current (IM3) is input from the RS pin, which is also used for the output current, IM3
cannot be measured by the normal testing methods.
Use the method shown below.

Setup Data

The serial data PHASE signal (both A and B) switch over to high or low.

Test Method

Set output to open, change phase data from 1 0 1 0 and perform switching. When testing, input

phase data at double the chopping frequency (if f

chop

= 100 kHz, fDATA = 200 kHz) and measure the

current value of V

supply.

fDATA = 200 kHz means that the phase switches at 200 kHz.

5 V

osc AB

3.6

0.22

�

Ccp 1

0.01

�

CR AB

ref

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

SETUP

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc AB

560

No reset at testing

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

A IM

0 1 2 3 4

13 14 15

DATA

CLK

STROBE

TB62201AFG

2005-04-04

Number of Switchings at Phase Switching

Number of Switchings at Actual Operation

Number of switchings at actual operation = 2 � number of switchings at phase switching.

Therefore, switching the phase at 2 � chopping cycle matches the number of switchings at actual operation

with the number of switchings at phase switching, and allows the actual current dissipation, IM3, to be
measured.

OFF

One phase switching

(16-bit data input)

Four transistors switching

To V

Load

PGND

To V

Load

PGND

Switches by phase data

OFF

Four transistors are switched at one phase switching

OFF

Charge

OFF

Slow

Two transistors

switching

OFF

Four transistors switching

Eight transistors switching

in one chopping cycle

Mode changes three times
in one chopping cycle.

Chopping cycle

Fast

Four transistors switching

One phase switching

(16-bit data input)

Two transistors

switching

TB62201AFG

2005-04-04

5. I

, I

(A/B unit only. C/D unit conforms to A/B unit.)

Test Method

: With V

= 24 V, V

= 5 V, and logic input all = 0 applied, set RESET = H, connect the output pins

to GND, and measure the supply current.

: With V

= 24 V, V

= 5 V, and logic input all = 0 applied, set RESET = H, connect the output pins

to V

, and measure the supply current.

: With V

= 24 V, V

= 5 V, and logic input all = 0 applied, set RESET = L, connect the output pins

to GND, and measure the supply current.

Setup Data

5 V

osc

3.6

0.22

�

Ccp 1

0.01

�

CR AB

ref

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

SETUP

SGND

3 V

, I

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc AB

560

No reset at testing

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

DATA

CLK

STROBE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

TB62201AFG

2005-04-04

6. V

(H to L), V

ref

(GAIN) (when measuring phase A) after Measurement

(A/B unit only. C/D unit conforms to A/B unit.)

RS (H to L):

Input torque data = 100% (HH) and vary the voltage between V

and R

pins.

Measure the voltage (V

) when output changes from fixed Charge mode to another mode.

Also measure V

when torque data = 85% (HL), 70% (LH), or 50% (LL) as above and

calculate the ratio using V

value at 100% as reference.

ref (GAIN)

: V

ref (GAIN)

ref

(*)

((*) V

: when torque data = 100%)

Setup Data

5 V

osc AB

3.6

0.22

�

Ccp 1

0.01

�

CR AB

ref AB

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

SETUP

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560

No reset at testing

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

Oscilloscope

Vary between
0 and 1 V.

1 2 3 4

13 14 15

DATA

CLK

STROBE

TB62201AFG

2005-04-04

out1

out2

(A/B unit only. C/D unit conforms to A/B unit.)

With L load, perform chopping in Mixed Decay mode. Monitor the output current waveform and measure
the various output currents at constant current operation.

Setup Data

5 V

osc

3.6

0.22

�

Ccp 1

0.01

�

ref

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

SETUP

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560

No reset at testing

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

RS B

RS A

Monitors current

waveform.

0 1 2 3 4

13 14 15

Set to 100%

MDT

Output current
value (set
current value)

DATA

CLK

STROBE

Current

waveform

Charge

Slow

MDT

100%

Fast

Charge

Slow

Fast

Measurement of
peak current

TB62201AFG

2005-04-04

8. IRS (when measuring phase A) (A/B unit only. C/D unit conforms to A/B unit)

With L input to RESET , connect V

and R

to the power supply, and measure the current input to the

pin. (Either drop all the input pins to GND level or input all Low data to the DATA pin, then perform

measurement. At that time, leave all other output pins open.)

Setup Data

osc

3.6

0.22

�

Ccp 1

0.01

�

CR AB

ref

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

SETUP

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560

RESET

= L

DATA

CLK

STROBE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

TB62201AFG

2005-04-04

9. R

ON (D-S)

ON (S-D)

when Measuring Output A

(A/B unit only. C/D unit conforms to A/B unit.)

Input the current setting data (HHHH signal) to the DATA pin and measure the voltage between V

and

OUT when I

out

= 1000 mA or the voltage between OUT and GND. Then, change the phase and repeat

measurement. At that time, leave the output pins which are not measured open.

Setup Data

(Vary the phase data during testing.)

5 V

osc

3.6

0.22

�

Ccp 1

0.01

�

CR AB

ref AB

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

SETUP

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560

No reset at testing

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

Curve tracer

DATA

CLK

STROBE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

TB62201AFG

2005-04-04

10. V

ref

, I

ref

(A/B unit only. C/D unit conforms to A/B unit.)

ref

: Vary V

ref

= 2 to V

- 1 V and confirm that output is on.

ref

: When V

= 24 V and V

= 5 V, apply the specified voltage of 3 V to the V

ref

and monitor the

current flow value.

5 V

osc AB

3.6

0.22

�

Ccp 1

0.01

�

CR AB

ref

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

SETUP

SGND

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc AB

560

No reset at testing

RESET

= 5 [V]

RS A

Oscilloscope

Monitor

ref

(*)

Vary V

ref

= 2 to V

- 1.0 V

(*) When measuring I

ref

fix V

ref

= 3 V and

measure.

TB62201AFG

2005-04-04

11. T

TSD,

TSD

(Measure in an environment such as an constant temperature chamber where

the temperature for the IC can be freely changed) (A/B unit only. C/D unit conforms to A/B
unit.)

TSD : Increase the ambient temperature. Measure the temperature when output stops.

TSD : Gradually lower the temperature from the level when the TSD circuit was operating (output off).

At that time, control the RESET input thus : H L H L. Output will begin at a certain

temperature level.
T

TSD is the difference between the temperature at which output begins and the temperature at

which TSD is triggered.

Setup Data

5 V

osc

3.6

0.22

�

Ccp 1

0.01

�

CR AB

ref AB

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

SETUP

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560

No reset at testing

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

Curve tracer

DATA

CLK

STROBE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

TB62201AFG

2005-04-04

12. V

DDR

(A/B unit only. C/D unit conforms to A/B unit.)

Monitor the output pins. Increase the V

voltage from 0. Measure the V

value when output starts.

Next, decrease the V

voltage and measure the V

value when output stops.

Setup Data

5 V

osc

3.6

0.22

�

Ccp 1

0.01

�

CR AB

ref

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

SETUP

SGND

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

osc

560

No reset at testing

RESET

= 5 [V]

RS A

Oscilloscope

SGND

5 V

Vary from 0 V.

RS B

3 V

5 V
0 V
5 V
0 V

5 V
0 V

DATA

CLK

STROBE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

TB62201AFG

2005-04-04

13. V

(A/B unit only. C/D unit conforms to A/B unit.)

With the CLK signal and DATA (all High) input, increase the V

voltage from 0.

Measure the V

value when output starts.

Next, decrease the V

voltage and measure the V

value when output stops.

Setup data

5 V

osc

3.6

0.22

�

Ccp 1

0.01

�

CR AB

ref

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

SETUP

SGND

: PGND
: SGND (V

)

Ccp 2

SGND

osc

560

No reset at testing

RESET

= 5 [V]

RS A

Oscilloscope

Vary from 0 V.

RS B

3 V

5 V

5 V
0 V
5 V
0 V

5 V
0 V

DATA

CLK

STROBE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

TB62201AFG

2005-04-04

14. Overcurrent Protector Circuit

(ISD) (To measure output A: )

(A/B unit only. C/D unit conforms to A/B unit.)

Test method: To monitor operating current of the overcurrent protector circuit when output A is

short-circuited to the power supply

Input the current setting data (HHHH signal) to the DATA pin. If short-circuited to the supply, measure
the lower output transistors. If short-circuited to ground, measure the upper output transistors (see how to
measure R

When measuring R

, increase the current flow. There is a current value at which output is switched off

and R

cannot be measured. This value is the set current value for the overcurrent protector circuit.

Make sure to leave open the output pins not being measured.
Note that if the temperature changes, the value may fluctuate. Try to avoid applying power to the IC by
one-shot measuring.

Setup Data

(Example: The phase signal must be changed depending on the pin.)

5 V

osc AB

3.6

0.22

�

Ccp 1

0.01

�

CR AB

ref AB

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

SETUP

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560

At measuring, non-reset

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

Curve tracer

DATA

CLK

STROBE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

TB62201AFG

2005-04-04

15. Current Vector

(A/B unit only. C/D unit conforms to A/B unit.)

Perform chopping in Mixed Decay mode with load L. Monitor the output current waveform and measure
the output current at constant current operation. At this time, vary the 4-bit data for current setting and
measure the current values. Using the set output current as 100%, calculate the output current ratio.

100%

(example)
71%

Output current

5 V

osc

3.6

0.22

�

Ccp 1

0.01

�

ref

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

SETUP

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560

At measuring, non-reset

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

RS B

RS A

Monitor current

waveform

TB62201AFG

2005-04-04

16. f

CLK

, t

w (CLK)

, t

wp (CLK)

wn (CLK)

, t

STROBE

, t

STROBE (H)

, t

STOBE (L)

suSIN-CLK

, t

suST-CLK

, t

hSIN-CLK

, t

hCLK-ST

(A/B unit only. C/D unit conforms to A / B unit.)

Input any data at f

CLK

(max), perform chopping, and monitor the output waveform.

For the measuring points, see the timing chart below.

Setup Data

Measuring Points

5 V

osc

3.6

0.22

�

Ccp 1

0.01

�

CR AB

ref

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

SETUP

SGND

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

osc

560

No reset at testing

RESET

= 5 [V]

RS A

RS B

3 V

5 V
0 V
5 V
0 V

5 V
0 V

5 V

thIN-CLK

CLK

STROBE

DATA

50%

tsuSIN-CLK

tSTROBE (L)

tSTROBE (H)

50%

tsuST-CLK

DATA15

50%

thST-CLK

DATA0

twn (CLK) twp (CLK)

tw (CLK)

tSTROBE

1 2 3 4

12 13 14 15

DATA

CLK

STROBE

TB62201AFG

2005-04-04

17. OSC-fast Delay, OSC-charge Delay

(A/B unit only. C/D unit conforms to A / B unit.)

Fix the output current value in Mixed Decay mode and turn the output on. Measure the time until the
output switches from the CR pin waveform and the output voltage waveform.

Setup Data

5 V

osc

3.6

0.22

�

Ccp 1

0.01

�

CR AB

ref

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

SETUP

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560

No reset at testing

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

RS B

RS A

DATA

CLK

STROBE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

out A

(Mode)

50%

50% 50%

50%

Osc-charge delay

Osc-fast delay

Slow

Charge Fast

Charge

Bottom

Top

TB62201AFG

2005-04-04

18. t

pHL (ST)

, t

pLH (ST)

, t

(A/B unit only. C/D unit conforms to A/B unit.)

Setup Data

Switch PHASE every 130 祍 and measure the output pin voltage and the STROBE signal.

[Oscilloscope Waveform (example)]

50%

STROBE

Output

voltage A

Output

voltage A

50%

pHL (ST)

130

祍

pLH (ST)

90%

50%

10%

RS A

5 V

osc

3.6

0.22

�

Ccp 1

0.01

�

CR AB

ref AB

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

SETUP

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560

No reset at testing

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

RS B

Monitor

= 5.7

6.8 mH

1 2 3 4

12 13 14 15

DATA

CLK

STROBE

TB62201AFG

2005-04-04

19. t

BRANK

(A/B unit only. C/D unit conforms to A/B unit.)

BRANK

is the dead time band for avoiding malfunction caused by noise. Apply sufficient differential

voltage (when V

ref

= 3 V, 0.6 V or higher) to V

-R

and apply duty. When the pulse width reaches a certain

value, triggering feedback and changing the output. Check the value.

Setup Data

RS A

5 V

osc AB

3.6

0.22

�

Ccp 1

0.01

�

CR AB

ref AB

RS A

M A

DATA AB

CLK AB

STROBE AB

DD AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

SETUP

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc AB

560

No reset at testing

RESET

= 5 [V]

RS B

5 V
0 V
5 V
0 V

5 V
0 V

SGND

Apply pulse to the R

so that the R

= V

voltage

- 1.0 V.

pin voltage

Output operation

Measure the pulse width
where output changes.

0 1 2 3

12 13 14 15

DATA

CLK

STROBE

TB62201AFG

2005-04-04

20. f

chop

(min), f

hop

(max)) (A/B unit only. C/D unit conforms to A/B unit.)

Change the R

osc

and C

osc

values and measure the frequency on the CR pin using the oscilloscope.

At this time, 1/8 of the frequency of the measured CR waveform is f

chop

Oscilloscope Waveform

(example)

RS A

osc AB

3.6

0.22

�

Ccp 1

0.01

�

CR AB

ref AB

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

SETUP

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc AB

560

RS B

Oscilloscope

1/8 f

chop

(SYNC)

= f

= 0

= 1

TB62201AFG

2005-04-04

21. t

ONG

(A/B unit only. C/D unit conforms to A/B unit.)

Apply V

and V

and change RESET from L to H.

Measure the time until the CcpA pin becomes V

+ V

� 90%.

RS A

5 V

osc

3.6

0.22

�

Ccp 1

0.01

�

CR AB

ref AB

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

SETUP

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560

At measuring, change
from reset to non-reset.

RS B

5 V
0 V
5 V
0 V

5 V
0 V

ONG

50%

5 V

0 V

RESET

+ V

)

� 90%

TB62201AFG

2005-04-04

22. Mixed Decay Timing

(A/B unit only. C/D unit conforms to A/B unit.)

With V

= 24 V, V

= 5 V, RESET = H, change the SETUP pin from L to H and overwrite the MIXED

DECAY TIMING TABLE.
Then change the SETUP pin from H to L. With load L, perform chopping and monitor the output current
waveform at that time. Confirm that the switching timing from Slow Decay Mode to Fast Decay Mode
within an fchop cycle is the specified MIXED DECAY TIMING.
(Depending on the load L value and the test environment, chopping may be performed every two cycles or
there may be no Slow Decay Mode. If so, conditions, for example, load condition, may need to be changed.

RS A

5 V

osc

3.6

0.22

�

Ccp 1

0.01

�

ref AB

RS A

M A

DATA AB

CLK AB

STROBE AB

RS B

M B

)

Ccp C

Ccp B

Ccp A

RESET

P-GND

SETUP

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560

RS B

5 V
0 V
5 V
0 V

5 V
0 V

At measuring, non-reset

RESET

= 5 [V]

5 V

When overwriting the
mixed decay timing
table, set to 5 V.
When the motors are
operating, set to
GND level.

Output current value
(set current value)

MDT

100% 0%

MDT

Charge

Slow

Fast

Current waveform

TB62201AFG

2005-04-04

In MIXED DECAY MODE, when the Output Current

> the Set Current Value

FAST DECAY MODE Waveform

Set current value

Set current
value

RNF

STROBE signal input

out

FAST DECAY
MODE
(0% MIXED
DECAY MODE)

chop

Response delay time

NF is the point at which the output
current reaches the set current value.

Because the set current value > the output current,
FAST DECAY MODE in the next cycle, too

RNF

Because the set current value > the output current, CHARGE
MODE

NF FAST DECAY MODE in the next cycle, too

Set current value

MDT (MIXED DECAY TIMING) point

Set
current
value

RNF

STROBE signal input

out

12.5%
MIXED
DECAY
MODE

chop

CHARGE MODE for one fchop

cycle after STROBE signal input

RNF

Because the set current value >
the output current, no CHARGE

MODE in the next cycle.

TB62201AFG

2005-04-04

STROBE Signal, Internal CR CLK, and Output Current Waveform

(When STROBE signal is input in SLOW DECAY MODE)

When STROBE signal is input, the chopping counter (CR-CLK counter) is forced to reset at the next
CR-CLK timing.
Because of this, compared with a method in which the counter is not reset, response to the input data is
faster.
(The delay time, the theoretical value in the logic portion, is expected to be a one-cycle CR waveform:
1.25 祍 @ 100 kHz CHOPPING.)

When the C-CLK counter is reset due to STROBE signal input, CHARGE MODE is entered momentarily
due to current comparison.

Note: In FAST DECAY MODE, too, CHARGE MODE is entered momentarily due to current comparison.

MDT

RNF

Set current
value

STROBE signal input

out

chop

37.5% MIXED DECAY MODE

MDT

RNF

Momentarily enters
CHARGE MODE

Reset CR-CLK
counter here

TB62201AFG

2005-04-04

Current Modes

(mixed (

= SLOW

FAST) Decay Mode Effect)

� Sine wave in increasing (Slow Decay Mode (Charge + Slow + Fast) normally used)

� Sine wave in decreasing (When using MIXED DECAY Mode with large attenuation ratio (MDT%) at

attenuation)

� Sine wave in decreasing (When using MIXED DECAY Mode with small attenuation ratio (MDT%) at

attenuation)

Note: The above charts are schematics. The actual current transient responses are curves.

Set current
value

Slow

Charge

Fast

Slow

Fast

Charge

Fast Charge

Fast

Slow

Set current
value

Charge

Slow

Set current
value

Charge

Fast

Slow

Because current attenuates slowly, it
takes a long time for the current to follow
the set current value (or the current does
not follow).

Set current
value

Slow

Charge

Fast

Slow

Charge

Fast

Slow

Fast

Charge

Set current
value

Because current attenuates so quickly, the current
immediately follows the set current value.

TB62201AFG

2005-04-04

Output Transistor Operating Mode

Output Transistor Operation Functions

CLK U

CHARGE ON OFF OFF

SLOW OFF OFF

FAST OFF ON ON

OFF

Note: The above table is an example where current flows in the direction of the arrows in the above figures.

When the current flows in the opposite direction of the arrows, see the table below.

CLK U

CHARGE OFF ON ON OFF

SLOW OFF OFF

FAST ON OFF

OFF

To VM

Load

PGND

(Note)

RS pin

Charge mode

(Charges coil power)

To VM

Load

PGND

(Note)

RS pin

Slow mode

(Slightly attenuates

coil power)

To V

Load

PGND

(Note)

RS pin

Fast mode

(Drastically attenuates

coil power)

TB62201AFG

2005-04-04

Current Discharge Path when Current Data

= 0000 are Input during Operation

In Slow Decay Mode, when all output transistors are forced to switch off, coil energy is discharged in the following
MODES :

Note: Parasitic diodes are located on dotted lines. In normal MIXED DECAY MODE, the current does not flow to the

parasitic diodes. However, when signal 0000 is input during operation, the current flows to them.

As shown in the figure at right, an output transistor has parasitic diodes.
To discharge energy from the coil, each transistor is switched on allowing current to flow in the reverse direction to
that in normal operation. As a result, the parasitic diodes are not used. If all the output transistors are forced to
switch off, the energy of the coil is discharged via the parasitic diodes.

To VM

Load

PGND

(Note)

To VM

Load

PGND

(Note)

To V

power supply

Load

PGND

(Note)

RS pin RS pin

RS pin

OFF

Charge mode

Slow Decay mode

Forced OFF mode

OFF

Input Current DATA

= 0000

TB62201AFG

2005-04-04

Power Supply Sequence

(Recommended)

Note 1: If the V

drops to the level of the V

DDR

or below while the specified voltage is input to the V

pin, the IC is

internally reset. This is a protective measure against malfunction. Likewise, if the V

drops to the level of

the V

or below while regulation voltage is input to the V

, the IC is internally reset as a protective

measure against malfunction. To avoid malfunction, when turning on V

or V

, we recommend you input

the RESET signal at the above timing.
It takes time for the output control charge pump circuit to stabilize. Wait up to t

ONG

time after power on

before driving the motors.

Note 2: When the V

value is between 3.3 to 5.5 V, the internal reset is released, thus output may be on. In such a

case, the charge pump cannot drive stably because of insufficient voltage. We recommend the RESET state
be maintained until V

reaches 20 V or more.

Note 3: Since V

= 0 V and V

= voltage within the rating are applied, output is turned off by internal reset. At that

time, a current of several mA flows due to the Pass between V

and V

DD (max)

DD (min)

DDR

GND

M (min)

GND

Non-
reset

RESET

Internal
reset

RESET

input
.....*

Takes up to t

ONG

until operable.

Non-operable area

TB62201AFG

2005-04-04

Relationship between V

and V

is the voltage of the CcpA pin. It is the highest voltage in this IC (power supply for driving the upper gate of the

H bridge).

Vcharge Up is the voltage to boost V

to V

. Usually equivalent to V

� V

(& V

charge up

)

Supply voltage V

(V)

vol

t
age

, charg

e
up volt

age

volt

age

(V)

0 5 10 15 20 25 30 35 40

VMR

Recommended operation area

Usable area

Maximum

Input RESET (

RESET

= 0 V)

VH voltage

Charge up voltage

VM voltage

VDD = 5 V
Ccp1

= 0.22 礔

Ccp2

= 0.02 礔

VH = VDD + VM (CcpA)

TB62201AFG

2005-04-04

Operation of Charge Pump Circuit

Initial charging

(1) When RESET is released, T

is turned ON and T

turned OFF. Ccp2 is charged from Ccp2 via Di1

(This is the same as when TSD and ISD are operating and the IC is restored from Reset state.)

(2) T

is turned OFF, T

is turned ON, and Ccp1 is charged from Ccp2 via Di2.

(3) When the voltage difference between V

and V

(CcpA pin voltage = charge pump voltage) reaches V

higher, operation halts (Steady state: Because the capacitor is naturally discharged, the IC is continually
charging to the capacitor).

Actual operation

(4) Ccp1 charge is used at fchop switching and the VH potential drops.
(5) Charges up by (1) and (2) above.

Output switching

Normal state

Initial charging

Charge p

u
mp voltage

(2)

(1) (3)

(4)

(5)

(4)

(5)

1/18/19/36

3/16/21/34

Comparator

Controller

Di3

CcpC

Ccp2

0.01

�

Ccp1

0.22

�

= 24 V

Output

H switch

Output

Di2

Di1

CcpB

= 5 V

CcpA

(2)

(1)

(2)

= V

+ V

= charge pump voltage

= charge pump current

= gate block power dissipation

TB62201AFG

2005-04-04

External Capacitors for Charge Pumps

When V

= 5V, fchop = 100 kHz, and L = 10 mH is driven with V

= 24 V, I

out

= 1100 mA, the theoretical values

for Ccp1 and Ccp2 are as shown below:

Combine Ccp1 and Ccp2 as shown in the shaded area in the above graph.
Select values 10: 1 or more for Ccp1: Ccp2.
When making a setting, evaluate properly and set values with a margin.

0.05

0.04

0.03

0.02

0.01

0 0.1

0.2 0.3

0.4

0.5

Recommended value

Recommended area

Usable area

Ccp1

= (NG)

Ccp2

= (OK)

Ccp1 capacitance (

礔)

Ccp1 � Ccp2

p2 cap

a
cit

a
n
c
e

(
�

TB62201AFG

2005-04-04

Charge Pump Rise Time

ONG

: Time taken for capacitor Ccp2 (charging capacitor) to fill up Ccp1 (capacitor used to save charge) to V

after a reset is released.

The internal IC cannot drive the gates correctly until the voltage of Ccp1 reaches V

+ V

. Be sure to

wait for t

ONG

or longer before driving the motors.

Basically, the larger the Ccp1 capacitance, the longer the initial charge-up time but the smaller the
voltage fluctuation.
The smaller the Ccp1 capacitance, the shorter the initial charge-up time but the larger the voltage
fluctuation.
Depending on the combination of capacitors (especially with small capacitance), voltage may not be
sufficiently boosted. Thus, use the capacitors under the capacitor combination conditions (Ccp1 = 0.22 礔,

Ccp2 = 0.01 礔) recommended by Toshiba.

+ V

)

� 90%

5 V

0 V

50%

ONG

RESET

TB62201AFG

2005-04-04

Operating Time for Overcurrent Protector Circuit

(ISD non-sensitivity time and ISD operating time)

A non-sensitivity time is set for the overcurrent protector circuit to avoid misdetection of overcurrent due to spike
current at irr or switching.
The non-sensitivity time synchronizes with the frequency of the CR for setting the chopping frequency. The
non-sensitivity time is set as follows :
Non-sensitivity

time

= 4 � CR cycle

The time required for the ISD to actually operate after the no-sensitivity time is as follows :
Minimum:

� CR cycle

Maximum:

� CR cycle

Therefore, from the time overcurrent flows to the output transistors to the time output halts is as follows.
Note that ideally, the operating time is the operating time when overcurrent flows. Depending on the output control
mode timing, the overcurrent protector circuit may not be triggered.
Therefore, to ensure safe operation, add a fuse to the V

power supply for protection.

The fuse capacity would vary according to the use conditions. However, select a fuse whose capacity avoids any
operating problems and does not exceed the power dissipation for the IC.

Point where overcurrent flows to output transistors (overcurrent status start)

Output halts (Reset status)

CR oscillation

(basic chopping

waveform)

(Non-sensitivity time)

ISD BLANK time

min

max

ISD operating time

min

max

TB62201AFG

2005-04-04

Application Operation Input Data

(Example: 2-Phase Excitation mode)

TORQUE

DECAY

PHASE

DECAY

PHASE

Bit

4 5

10 11 12 13 14

1 1

0 1 1

0 1 1 1 1

2 1

0 1 1

0 1 1 1 1

3 1

0 1 1

0 1 1 1 1

4 1

0 1 1

0 1 1 1 1

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.
For the input conditions, see page 9, Functions.
We recommend Mixed Decay mode (37.5%) as Decay mode. Set torque to 100%.

Output Current Waveform of 2-phase Excitation Sine Wave

Note: We recommended 2-phase excitation drive in 37.5% Mixed Decay mode.

Please refer to the caution of 2-phase excitation mode on next page.

(%)

100

-100

Phase B

Phase A

TB62201AFG

2005-04-04

Application Operation Input Data

(Example: 1-2 Phase Excitation mode Typ. A)

TORQUE

DECAY

PHASE

DECAY

PHASE

Bit 0

3 4

10 11

0 1

0 1 1 1 1

0 1

0 1 1 1 1

0 1

0 1 1 1 1

0 1

0 1 0 0 0

0 1

0 1 1 1 1

0 1

0 1 1 1 1

0 1

0 1 1 1 1

0 1

0 1 0 0 0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.
For the input conditions, see page 10, Functions.
We recommend Mixed Decay Mode (37.5%) as Decay Mode.
Set torque to 100%.
When using this excitation mode, high efficiency can be achieved by setting the phase data to 10% (-10%). Set

current values in the order +100% -10% -100% +10%.

Output Current Waveform of 1-2 Phase Excitation Sine Wave

(Type. A)

(%)

100

-10

-100

(%)

100

-10

-100

Phase A

Phase B

TB62201AFG

2005-04-04

Points for Control that Includes Current of 0%

In modes other than 2-Phase Excitation mode (from 1-2 Phase Excitation mode to 4W1-2 Phase Excitation mode),
when the current is controlled to 0%, the TB62201AFG's output transistors are all turned off.
At the time, the coil's energy returns to the power supply through the parasitic diodes. If the same current is
applied several times and is within the rated current, then : the power consumed by the on-resistance when current
flows to the output MOS will be less than the power consumed when current is applied to the parasitic diodes.
Therefore, when controlling the current, rather than setting 0%, set the current to the next step beyond 0% (the
minimum step in the reverse direction) for better power dissipation results.
However, if the 0% (actually 10%) current cycle is long, the power dissipation may be greater than in Off mode
because of the need for constant-current control.
Therefore, Toshiba recommend setting the current according to the actual operating pattern. (1-2 Phase Excitation
mode is the most effective.)

Flyback Diode Mode

Non-flyback Diode Mode

Output off

period

Diode parasite

Constant-

current

control

[%]

100

-10

-100

Load

To V

power supply

OFF

Forced Off mode

PGND

Charge

The coil's energy returns through
the parasitic diodes.
Because V

< V

, the power

dissipation is large.

Constant-

current

control

[%]

100

-10

-100

Charge

Specifies a level of 10%,
either side of 0.

OFF

Load

To V

Charge mode

PGND

The coil's energy returns through
the MOS, which is turned on.
Then the coil is charged to a level
of 10%.
The power dissipation is smaller
than when the energy is returned
via the parasitic diode.
(However, the longer the

�10%

rated current control time, the
longer the period of current
dissipation.)

Constant-

current

control

Constant-

current

control

Constant-

current

control

TB62201AFG

2005-04-04

Application Operation Input Data

(Example: 1-2 Phase Excitation mode Typ.B)

TORQUE

MDMB

DECAY

PHASE

MDM A

DECAY

PHASE

Bit

10 11 12 13 14

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.
For the input conditions, see page 10, Functions.
We recommend Mixed Decay Mode (37.5%) as Decay Mode.
Set torque to 100%. Same as 1-2 phase excitation (typ. A) in the previous section, power dissipation can be reduced
by changing 0% level to 10% or -10%.

Output Current Waveform of 1-2 Phase Excitation Sine Wave

(Typ. B)

Phase A

(%)

100

-100

-71

Phase B

TB62201AFG

2005-04-04

Application Operation Input Data

(Example: 4-bit micro steps)

(2 bit micro steps

= W1-2 phase excitation drive)

TORQUE

DECAY

PHASE

DECAY

PHASE

Bit 0

3 4

10 11

0 1

0 0 0 0 0

0 0

0 0 0 1 0

0 0

0 0 0 0 1

0 0

0 0 0 1 1

0 0

0 1 1 1 1

0 0

0 1 1 1 1

0 0

0 0 0 1 1

0 0

0 0 0 0 1

0 0

0 0 0 1 0

10 1

0 1

0 0 0 0 0

11 1

0 1

1 0 0 0 0

12 1

0 0

1 0 0 1 0

13 1

0 0

1 0 0 0 1

14 1

0 0

1 0 0 1 1

15 1

0 0

1 1 1 1 1

16 1

0 0

0 1 1 1 1

17 1

0 0

0 0 0 1 1

18 1

0 0

0 0 0 0 1

19 1

0 0

0 0 0 1 0

20 1

0 1

0 0 0 0 0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.
For the input conditions, see page 9, Functions.
We recommend Slow Decay Mode in the ascending direction of the sine wave; Mixed Decay Mode (37.5%) in the
descending direction. Set torque to 100%.

TB62201AFG

2005-04-04

Application Operation Input Data

(Example: 3-bit micro steps)

(3 bit micro steps

= 2W1-2 phase excitation drive)

TORQUE

DECAY

PHASE

DECAY

PHASE

Bit

10 11 12 13 14

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.
For the input conditions, see page 10, Functions.
We recommend Slow Decay Mode in the ascending direction of the sine wave; Mixed Decay Mode (37.5%) in the
descending direction. Set torque to 100%.

TB62201AFG

2005-04-04

Output Current Waveform of Pseudo Sine Wave

(3-bit micro steps)

9 micro-step from 0 to 90� drive is possible by combining Current DATA (AB & CD) and phase data.
For input Current DATA at that time, see section on Current X in the list of the Functions.
Depending on the load, the optimum condition changes for selecting MIXED DECAY MODE when the sine wave
rises and falls. Select the appropriate MIXED DECAY TIMING according to the load.

100

[%]

-100

STEP

-83

-38

-20

-92

-98

-71

-56

Phase A

Phase B

TB62201AFG

2005-04-04

Application Operation Input Data

(Example: 4-bit micro steps)

TORQUE

DECAY

PHASE

DECAY

PHASE

Bit

10 11 12 13 14

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

TB62201AFG

2005-04-04

TORQUE

DECAY

PHASE

DECAY

PHASE

Bit

10 11 12 13 14

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.
For the input conditions, see page 10, Functions. In the above input data example, Decay mode has a Mixed Decay
mode (37.5%) setting for both the rising and falling directions of the sine wave, and a torque setting of 100%.

TB62201AFG

2005-04-04

4W1-2 Output Current Waveform of Pseudo Sine Wave

(4-bit micro steps)

17 micro-step from 0 to 90� drive is possible by combining Current DATA (AB & CD) and phase data.
For input Current DATA at that time, see section on Current X in the list of the Functions.
Depending on the load, the optimum condition changes for selecting MIXED DECAY MODE when the sine wave rises and falls. Select the
appropriate MIXED DECAY TIMING according to the load.

-100

STEP

-98

-96

-88

-92

-77

-71

-56
-63

-47

-38

-29

-20

-10

-83

100

[%]

Phase A

Phase B

TB62201AFG

2005-04-04

Temperature Characteristics Depending on Voltages between Output Transistor

Drain and Source

= 24 V, V

= 5 V)

100

1900 2000

1800

1700

1600

1500

1400

1300

1200

1100

1000

900

800

700

600

500

400

300

200

100

200

300

400

500

600

700

800

900

1000

1100

1200

Maximum rating

-40癈

0癈

25癈

85癈

105癈

105癈 (max)

25癈 (max)

Reference values

105癈

85癈

25癈

0癈

-40癈

25癈 max

105癈 max

o
lt
age

tween

tput

tran

sistor

drai

n
and

urce

(mV)

Output current I

out

(mA)

TB62201AFG

2005-04-04

Resistance Characteristics Depending on Voltages Output Transistor Drain and

Source

= 24 V, V

= 5 V) (Forward, reverse)

The IC's maximum rating is 1.5 A and recommended current is 1.2 A max.
Use the IC within this range.
The on-resistance value fluctuates according to temperature. Pay particular attention to the temperature
conditions when using.

-1200

-1000

-800

-600

-400

-200

200

400

600

800

1400

1600

Maximum rating

25癈 (max)

25癈

25癈 max

o
lt
age

tween

tput

age

drai

n an

d source

(mV)

Output current I

out

(mA)

200

1000

1200

180

160

140

120

100

800

600

400

200

400

600

800

100

120

140

160

180

200

220

240

260

280

300

25癈 (reference values)

Maximum rating

Reference values

TB62201AFG

2005-04-04

Recommended Application Circuit

The values for the devices are all recommended values. For values under each input condition, see the
above-mentioned recommended operating conditions.
(Example: f

chop

= 96 kHz, CR: I

out

= 0.7 (A), LF: I

out

= 1.1 (A) )

Note: We recommend the user add bypass capacitors as required.

Make sure as much as possible that GND wiring has only one contact point.
Also, make sure that the VM pins are connected.

For the data to be input, see the section on the recommended input data.

Because there may be shorts between outputs, shorts to supply, or shorts to ground, be careful when designing
output lines, V

) lines, and GND lines.

osc

2.0 k

osc

1000 pF

ref AB

M A

RS A

RS B

)

STROBE CD

DATA CD

CLK CD

RESET

P-GND

STROBE AB

DATA AB

CLK AB

STEPUP

ref AB

2.63 V

�

SGND

RS A

0.75

Stepping
motor 1
(CR: 6.8 mH/5.7

)

RS B

0.75

SGND

5 V

100

�

Ccp C

Ccp B

Ccp A

Ccp 2
0.015

礔

Cop 1

0.22

�

24 V

100

�

5 V

0 V

5 V

0 V

5 V

0 V

5 V

0 V

5 V

0 V

SGND

M B

5 V

0 V

5 V

0 V

RS C

RS D

RS C

0.75

Stepping
motor 2
(LF: 6.8 mH/5.7

)

RS D

0.75

M D

ref CD

4.13 V

�

SGND

5 V

TB62201AFG

2005-04-04

Example of 1-2 Phase Drive Current (actual) Waveform

Example of 4W 1-2 Phase Drive Current (actual) Waveform

Ch4

10.0 mV

M1.00 ms

Ch4

8.0 mV

500 mA

: 170 Hz
@: 218 Hz

Test conditions

VM = 34 V
VDD = 5 V
Vref = 3.75 V
RRS = 0.5
Cosc

= 1000 pF

Rosc

= 2.2 k

fchop = 95 kHz
37.5% MIXED DECAY mode
Ta

= 25癈

Using 6.8 mH/5.7

, 1.8-degree,

200-step motor

Using Toshiba test board100

Ch4

10.0 mV

M2.00 ms

Ch4

4.4 mV

500 mA

: 102 Hz
@: 99 Hz

Test conditions

VM = 24 V
VDD = 5 V
Vref = 2.8 V
RRS = 0.5
Cosc

= 1000 pF

Rosc

= 2.2 k

fchop = 95 kHz
37.5% MIXED DECAY mode
Ta

= 25癈

Using 6.8 mH/5.7

, 1.8-degree,

200-step motor

Using Toshiba test board

TB62201AFG

2005-04-04

About solderability, following conditions were confirmed

� Solderability

(1) Use of Sn-63Pb solder Bath

� solder bath temperature

= 230癈

� dipping time

= 5 seconds

� the number of times

= once

� use of R-type flux

(2) Use of Sn-3.0Ag-0.5Cu solder Bath

� solder bath temperature

= 245癈

� dipping time

= 5 seconds

� the number of times

= once

� use of R-type flux

� The information contained herein is subject to change without notice.

� The information contained herein is presented only as a guide for the applications of our products. No

responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
TOSHIBA or others.

� TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor

devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability
Handbook" etc..

� The TOSHIBA products listed in this document are intended for usage in general electronics applications

(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer's own risk.

� The products described in this document are subject to the foreign exchange and foreign trade laws.

� TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced

and sold, under any law and regulations.

030619EBA

RESTRICTIONS ON PRODUCT USE

协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: TB62201AFG

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: TB62201AFG