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TB62202AFG

2005-04-04

TOSHIBA

Bi-CMOS Processor IC Silicon Monolithic

TB62202AFG

Dual-Stepping Motor Driver IC for OA Equipment Using PWM Chopper Type

The TB62202AFG is a dual-stepping motor driver driven by
chopper micro-step pseudo sine wave.
To drive two-phase stepping motors, Two pairs of 16-bit latch and
shift registers are built in the IC. The IC is optimal for driving
stepping motors at high efficiency and with low-torque ripple.
The IC supports Mixed Decay mode for switching the attenuation
ratio at chopping. The switching time for the attenuation ratio
can be switched in four stages according to the load.

Features

Two stepping motors driven by micro-step pseudo sine wave
are controlled by a single driver IC

Monolithic Bi-CMOS IC

Low ON-resistance of Ron = 1.2 (T

= 25°C @1.0 A: Typ.)

Two pairs of built-in 16-bit shift and latch registers

Two pairs of built-in 4-bit DA converters for micro steps

Built-in ISD, TSD, V

and V

power monitor (reset) circuit for protection

Built-in charge pump circuit (two external capacitors)

36-pin power flat package (HSOP36-P-450-0.65)

Output voltage: 40 V max

Output current: 1.0 A/phase max

Built-in Mixed Decay mode enables specification of four-stage attenuation ratio.
(The attenuation ratio table can be overwritten externally.)

Chopping frequency can be set by external resistors and capacitors. High-speed chopping possible at 100 kHz or
higher.

Note: When using the IC, pay attention to thermal conditions.

These devices are easy damage by high static voltage.
In regards to this, please handle with care.

Weight: 0.79 g (typ.)

TB62202AFG

2005-04-04

Block Diagram

1. Overview (Power lines: A/B unit (C/D unit is the same as A/B unit))

High voltage wiring (V

)

Logic DATA

Analog DATA

IC terminal

Logic circuit

DATA

CLK

STROBE

Ccp 2

Ccp 1

Chopping

reference circuit

Current setting

Current feedback circuit

Protected circuit

ref

Stepping

motor

16-bit latch

Torque control

4-bit DA

(analog control)

circuit

S COMP

circuit

Charge pump

circuit

Output circuit

(H-bridge)

Waveform

chapping

circuit

Chopping

waveform

generator

circuit

Output control circuit

TSD

circuit

ISD

circuit

DDR

circuit

RESET

Current control data logic circuit

16-bit shift register

Out X

TB62202AFG

2005-04-04

2. Logic unit A/B (C/D unit is the same as A/B unit)

Function

This circuit is used to input from the DATA pins micro-step current setting data and to transfer them to the
subsequent stage. By switching the SETUP pin, the data in the mixed decay timing table can be overwritten.

Note: The RESET and SETUP pins are pulled down in the IC by 10-k

resistor.

When not using these pins, connect them to GND. Otherwise, malfunction may occur.

Micro-step current setting data logic circuit

SETUP

DATA

CLK

STROBE

MIXED

DECAY
TIMING

16-bit shift register

TORQUE

× 2 bits

DECAY

× 2 bits

B unit side

PHASE

× 1 bit

CURRENT

× 4 bits

B unit side

Current feedback circuit

Output control circuit

D/A circuit

Output control

circuit

RESET

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

16-bit latch

A unit side

Data input

selector

TB62202AFG

2005-04-04

3. Current feedback circuit and current setting circuit

(A/B unit (C/D unit is the same as A/B unit)

Function

The current setting circuit is used to set the reference voltage of the output current using the micro-step
current setting data input from the DATA pins.
The current feedback circuit is used to output to the output control circuit the relation between the set
current value and output current. This is done by comparing the reference voltage output to the current
setting circuit with the potential difference generated when current flows through the current sense resistor
connected between RS and V

The chopping waveform generator circuit to which CR is connected is used to generate clock used as
reference for the chopping frequency.

Note 1: RS COMP 1: Compares the set current with the output current and outputs a signal when the output current

reaches the set current.

Note 2: RS COMP 2: Compares the set current with the output current at the end of Fast mode during chopping.

Outputs a signal when the set current is below the output current.

100%

85%
70%
50%

circuit 1

(detects

potential

difference

between

and V

)

COMP

circuit 1

(Note 1)

(set current reached signal)

circuit 2

(detects

potential

difference

between

and R

)

COMP

circuit 2

(Note 2)

RNF

(set current monitor signal)

Use in Fast mode

Use in Charge mode

Output

control circuit

Mixed decay
timing circuit

Output stop signal (ALL OFF)

Chopping reference circuit

Current feedback circuit

Torque
Control

circuit

Current setting circuit

TORQUE

0, 1

CURRENT

0~3

LOGIC

UNIT

15
14
13
12
11
10

9
8
7
6
5
4
3
2
1
0

Micro-step curre

nt setting

selector

cir

c
uit

4-bit

D/A

circuit

ref

Waveform shaping circuit

Chopping waveform

generator circuit

TB62202AFG

2005-04-04

4. Output control circuit, current feedback circuit and current setting circuit

(A/B unit

(C/D unit is the same as A/B unit)

Note: The

RESET

pins is pulled down in the IC by 10-k

resistor.

When not using the pin, connect it to GND. Otherwise, malfunction may occur.

ISD (current

shutdown)

circuit

Output pin

circuit

DDR

circuit

Thermal

shut down

(TSD)

circuit

Charge pump

circuit

Ccp A

LOGIC

DDR

: V

power on Reset

: V

power on Reset

ISD:

Current shutdown circuit

TSD: Thermal shutdown circuit

Protection circuit

Charge pump

circuit

MICRO-STEP

CURRENT SETUP

LATCH CLEAR signal

MIXED DECAY
TIMING TABLE

CLEAR signal

Ccp B

Ccp C

Output RESET signal

Output
circuit

Charge

pump

halt

signal

Power supply

for upper

output MOS

transistors

Reset signal

selector

circuit

Current

feedback

circuit

Current

setting

circuit

COUNTER

CR COUNTER

Chopping

reference circuit

Micro-step current setting

data logic circuit

Output control circuit

PHASE

DECAY

MODE

MIXED

DECAY
TIMING

circuit

Output circuit

NF
set current
reached signal

MIXED

DECAY

TIMING

Charge start

RESET

RNF
set current
monitor signal

Output stop
signal

Output control circuit

TB62202AFG

2005-04-04

5. Output equivalent circuit (A/B unit (C/D unit is the same as A/B unit)

M B

To V

From output
control circuit

Output

Output A

S A

RS A

PGND

From output
control circuit

Output B

RS B

Output driver

circuit

Power supply

for upper

output MOS

transistors

)

Phase A

Output driver

circuit

Power supply

for upper

output MOS

transistors

)

Phase B

S B

TB62202AFG

2005-04-04

Pin Assignment

Note: [Important] If this IC is inserted reverse, voltages exceeding the voltages of standard may be applied to some

pins, causing damage.
Please confirm the pin assignment before mounting and using the IC.

M B

OUT B

PGND

OUT B

Ccp A

REF AB

)

REF CD

Ccp B

Ccp C

OUT

PGND

S D

OUT D

M D

TB62202AFG

(top view)

M A

OUT A

PGND

OUT A

STROBE AB

CLK AB

DATA AB

RESET

)

DATA CD

CLK CD

STROBE CD

OUT C

PGND

S C

OUT C

M C

TB62202AFG

2005-04-04

Pin Description

Pin No.

Pin Symbol

Description

1 V

M B

Voltage major for output B block

OUT B

Output B pin

3 R

S B

Channel B current pin

4 PGND

Power

GND

OUT

Output

6 NC

Non

connection

7 C

Capacitor pin for charge pump (Ccp1)

External C/R (osc) pin (sets chopping frequency)

9 V

REF AB

ref

input pin AB

) : Logic GND pin

10 V

REF CD

Vref input pin CD

11 NC

Non

connection

12 C

Capacitor pin for charge pump (Ccp2)

13 C

Capacitor pin for charge pump (Ccp2)

OUT

Output

15 PGND

Power

GND

16 R

S D

Channel D current pin

OUT D

Output D pin

18 V

M D

Voltage major for output D block

19 V

M C

Voltage major for output C block

OUT

Output

C pin

21 R

S C

Channel C current pin

22 PGND

Power

GND

OUT C

Output C pin

STROBE CD

CD STROBE (latch) signal input pin ( : LATCH)

CLK CD

CD clock input pin

DATA CD

CD serial data signal input pin

27 V

Power pin for logic block

) : Logic GND pin

RESET

Output reset signal input pin (L : RESET)

DATA AB

AB serial data signal input pin

CLK AB

AB clock input pin

STROBE AB

AB STROBE (latch) signal input pin ( : LATCH)

OUT A

Output A pin

33 PGND

Power

GND

34 R

S A

Channel A current pin

OUT

Output

A pin

36 V

M A

Voltage major for output A block

Note: How to handle GND pins

All power GND pins and FIN (V

: signal GND) pins must be grounded.

Since FIN also functions as a heat sink, take the heat dissipation into consideration when designing the board.

TB62202AFG

2005-04-04

Signal Functions

1. Serial input signals

(for A/B. C/D is the same as A/B)

Data No.

Name

Functions

0 LSB

TORQUE 0

1 TORQUE

DATA No.0, 1

= HH: 100%, LH: 85%

HL: 70%, LL: 50%

DECAY MODE B

00: DECAY MODE 0, 01: DECAY MODE 1
10: DECAY MODE 2, 11: DECAY MODE 3

4 Current

5 Current

6 Current

7 Current

Used for setting current.
(LLLL

= Output ALL OFF MODE)

4-bit current B data
(Steps can be divided into 16 by 4-bit data)

PHASE B

Phase information (H: OUT A: H, OUT A : L)

DECAY MODE A

00: DECAY MODE 0, 01: DECAY MODE 1
10: DECAY MODE 2, 11: DECAY MODE 3

11 Current

12 Current

13 Current

14 Current

Used for setting current.
(LLLL

= Output ALL OFF MODE)

4-bit current A data
(Steps can be divided into 16 by 4-bit data)

15 MSB

PHASE A

Phase information (H : OUT A : H, OUT

: L)

Note 1: Serial data input order

Serial data are input in the order LSB (DATA 0)
MSB (DATA 15)

Role of Data

Data Name

Number of Bits

Functions

TORQUE 2

Roughly regulates the current (four stages).
Common to A and B units.

DECAY MODE

× 2 phases

Selects Decay mode.
A and B units are set separately.

CURRENT 4

× 2 phases

Sets a 4-bit micro-step electrical angle.
A and B units are set separately.

PHASE 1

× 2 phases

Determines polarity (

+ or -).

A and B units are set separately.

(Note 1)

TB62202AFG

2005-04-04

2. Serial input signal functions

Input Action

CLK STROBE DATA

RESET

VDDR

(Note 1) or

Operation of

TSD/ISD

(Note 2)

× H H L

No change in shift register.

× H H H L

H level is input to shift register.

× L H H L

L level is input to shift register.

× H H L

Shift register data are latched.

× H H L

× L × L

Output off, charge pump halted
(S/R DATA CLR)

× L L

Output off (S/R DATA CLR)
Charge pump halted
Mixed decay timing table cleared (only V

DDR

)

× H H H

Output off (S/R DATA HOLD)
Charge pump halted
Restored when RESET goes from Low to High

×: Don't

Care

Qn:

Latched output level when STROBE is .

Note 1: V

DDR

and V

H when the operable range (3 V typical) or higher and L when lower.
When one of V

DDR

or V

is operating, the system resets (OR relationship).

Note 2: High when TSD is in operation.

When one of TSD or ISD is operating, the system resets (OR relationship).

Note: Function of overcurrent protection circuit

Until the RESET signal is input after ISD is triggered, the overcurrent protection circuit remains in operation.
During ISD, the charge pump stays halted.
When TSD and ISD are operating, the charge pump halts.

3. PHASE

functions

Input Function

Positive polarity (A: H, : L)

Negative polarity (A: L, : H)

TB62202AFG

2005-04-04

4. DECAY mode X0, X1 functions

DECAY Mode X1

DECAY Mode X0

Function

L L

Decay Mode 0
(Initial value: SLOW DECAY MODE)

L H

Decay Mode 1
(Initial value: MIXED DECAY MODE: 37.5%)

H L

Decay Mode 2
(Initial value: MIXED DECAY MODE: 75%)

H H

Decay Mode 3
(Initial value: FAST DECAY MODE)

5. TORQUE

functions

TORQUE 0

TORQUE 1

Comparator Reference Voltage Ratio

H H

100%

L H

85%

H L

70%

L L

50%

6. Current

(BX)

functions

Step

Set Angle

90.0 H H H H L L L L

84.4 H H H H L L L H

78.8

H H H L L L H L

73.1

H H L H L L H H

67.5

H H L L L H L L

61.2

H L H H L H L H

56.3

H L H L L H H L

9 50.6

H L L H L H H H

8 45.0

H L L L H L L L

7 39.4 L H H H H L L H

6 33.8 L H H L H L H L

5 28.1 L H L H H L H H

4 22.5 L H L L H H L L

3 16.9 L L H H H H L H

2 11.3 L L H L H H H L

1 5.6 L L L H H H H H

0 0.0 L L L L H H H H

By inputting the above current data (A: 4-bit, B: 4-bit), 17-microstep drive is possible. For 1 step fixed to 90
degrees, see the section on output current vector line (85 page).

TB62202AFG

2005-04-04

7. Serial data input setting

Note: Data input to the DATA pin are 16-bit serial data.

Data are transferred from DATA 0 (Torque 0) to DATA 15 (Phase A). Data are input and transferred at the
following timings.
At CLK falling edge: data input
At CLK rising edge: data transfer
After data are transferred, all data are latched on the rising edge of the STROBE signal.
As long as STROBE is not rising, the signal can be either Low or High during data transfer.

DATA

CLK

STROBE

TB62202AFG

2005-04-04

Maximum Ratings

(Ta

= 25°C)

Characteristics Symbol

Rating

Unit

Logic supply voltage

7 V

Output voltage

Output current

OUT

1.5

A/phase (Note

Current detect pin voltage

± 4.5

Charge pump pin maximum voltage
(CCP1 pin)

+ 7.0

Logic input voltage

+ 0.4

1.4 W

(Note

Power dissipation

3.2 W

(Note

Operating temperature

opr

-40 to 85

°C

Storage temperature

stg

-50 to 150

°C

Junction temperature

150

°C

Note 1: Perform thermal calculations for the maximum current value under normal conditions. Use the IC at 1.2 A or

less per phase.

Note 2: Input 7 V or less as V

Note 3: Measured for the IC only. (Ta

= 25°C)

Note 4: Measured when mounted on the board. (Ta

= 25°C)

Ta: IC ambient temperature

opr

: IC ambient temperature when starting operation

IC chip temperature during operation T

(max) is controlled by TSD (thermal shut down circuit)

Recommended Operating Conditions

(Ta

= 0 to 85°C)

Characteristics Symbol Test

Condition Min

Typ.

Max

Unit

Power supply voltage

4.5 5.0 5.5 V

Output voltage

= 5.0 V

OUT (1)

= 25°C, per phase

(when one motor is driven)

0.6 0.9 A

Output current

OUT (2)

= 25°C, per phase

(when two motors are driven)

0.6 0.9 A

Logic input voltage

GND

Clock frequency

CLK

= 5.0 V

1.0

6.25

MHz

Chopping frequency

chop

= 5.0 V

100

150

KHz

Reference voltage

ref

= 24 V, T

orque

= 100%

2.0

3.0

Current detect pin voltage

= 5.0 V

±1.0

±1.5

Note: Use the maximum junction temperature (T

) at 120°C or less

TB62202AFG

2005-04-04

Electrical Characteristics 1

(Unless otherwise specified, Ta

= 25°C, V

= 5 V, V

= 24 V)

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

High V

(H)

2.0

+ 0.4

Input voltage

Low V

(L)

1 CLK, RESET , STROBE, DATA pins

GND

- 0.4

GND 0.8

IN1

(H)

1.0

Input current 1

IN1

(L)

CLK, STROBE, DATA pins

1.0

µA

IN2

(H)

700

Input current 2

IN2 (L)

RESET , SETUP pins

700

µA

DD1

5 V (STROBE, RESET ,

DATA

L), RESET

= L,

Logic, output all off

3.0 6.0

Power dissipation (V

pin)

DD2

Output OPEN, f

CLK

= 6.25 MHz

LOGIC ACTIVE, V

= 5 V,

Charge pump

= charged

4.0 8.0

Output OPEN (STROBE, RESET ,
DATA

= L), RESET = L,

Logic, output all off
Charge Pump

= no operation

5.0 6.0

Output OPEN, f

CLK

= 6.25 MHz

LOGIC ACTIVE, V

= 5 V,

= 24 V, Output off

Charge Pump

= charged

12 20

Power dissipation (V

pin)

Output OPEN, f

CLK

= 6.25 MHz

LOGIC ACTIVE, 100 kHz
chopping (emulation), Output OPEN,
Charge Pump

= charged Ccp1 =

0.22

µF, Ccp2 = 0.01µf

30 40

Output standby
current

Upper I

= VM = 24 V, V

out

= 0 V,

RESET

= H, DATA = ALL L

-400

Output bias current

Upper

= VM = 24 V, V

out

= 24 V,

RESET

= H, DATA = ALL L

-200

Output leakage
current

Lower I

= VM = CcpA = V

out

= 24 V,

RESET

= L

1.0

µA

High

(Reference)

RS (H)

ref

= 3.0 V,

ref

(Gain)

= 1/5.0

TORQUE

= (H.H) = 100% set

100

Mid High

RS (MH)

ref

= 3.0 V, V

ref

(Gain)

= 1/5.0

TORQUE

= (H.L) = 85% set

83 85 87

Mid Low

RS (ML)

ref

= 3.0 V, V

ref

(Gain)

= 1/5.0

TORQUE

= (L.H) = 70% set

68 70 72

Comparator
reference voltage
ratio

LOw V

RS (L)

ref

= 3.0 V, V

ref

(Gain)

= 1/5.0

TORQUE

= (L.L) = 50% set

48 50 52

Output current differential

out1

Differences between output current
channels
I

out

= 1000 mA

-5

5 %

Output current setting differential

out2

out

= 1000 mA

-5

5 %

RS pin current

IRS

VRS

= 24 V, V

= 24 V,

RESET

= L (RESET status)

µA

TB62202AFG

2005-04-04

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

ON (D-S) 1

out

= 1.0 A, V

= 5.0 V

= 25°C, Drain-source

1.1 1.3

ON (D-S) 1

out

= 1.0 A, V

= 5.0 V

= 25°C, Source-drain

1.1 1.3

ON (D-S) 2

out

= 1.0 A, V

= 5 V,

= 105°C, Drain-source

1.4 1.6

Output transistor drain-source
on-resistance

ON (D-S) 2

out

= 1.0 A, V

= 5 V,

= 105°C, Source-drain

1.4 1.6

TB62202AFG

2005-04-04

Electrical Characteristics 2

(Unless otherwise specified, Ta

= 25°C, V

= 5 V, V

= 24 V)

Characteristics Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

ref

input voltage

ref

= 24 V, V

= 5 V,

RESET

= H, Output on

2.0

ref

input current

ref

RESET

= H, Output off

= 24 V, V

= 5 V,

ref

= 3.0 V

100

µA

ref

attenuation ratio

ref

(GAIN)

= 24 V, V

= 5 V,

RESET

= H, Output on,

ref

= 2.0 to V

- 1.0 V

1/4.8 1/5.0 1/5.2

TSD temperature

TSD (Note

11 V

= 5 V, V

= 24 V

130

170

°C

TSD return temperature difference

TSD 11

TSD

= 130 to 170°C

TSD

- 35

°C

return voltage

DDR

= 24 V, RESET = H,

STROBE

= H

2.0

4.0 V

return voltage

= 5 V, RESET = H,

STROBE

= H

2.0

4.0 V

Over current protected circuit
operation current

(Note 2)

= 5V, V

= 24V,

fchop

= 100 kHz set

2.6 A

Note 1: Thermal shut down (TSD) circuit

When the IC junction temperature reaches the specified value and the TSD circuit is activated, the internal
reset circuit is activated switching the outputs of both motors to off.
When the temperature is set between 130 (min) to 170°C (max), the TSD circuit operates. When the TSD
circuit is activated, the function data latched at that time are cleared. Output is halted until the reset is
released. While the TSD circuit is in operation, the charge pump is halted.
Even if the TSD circuit is activated and RESET goes H

L H instantaneously, the IC is not reset until

the IC junction temperature drops 35°C (typ.) below the TSD operating temperature (hysteresis function).

Note 2: Overcurrent protection circuit

When current exceeding the specified value flows to the output, the internal reset circuit is activated
switching the outputs of both shafts to off.
When the ISD circuit is activated, the function data latched at that time are cleared.
Until the RESET signal is input, the overcurrent protection circuit remains activated.
During ISD, the charge pump halts.
For failsafe operation, be sure to add a fuse to the power supply.

TB62202AFG

2005-04-04

Electrical Characteristics 3

(Ta

= 25°C, V

= 5 V, V

= 24 V, I

out

= 1.0 A)

Characteristics SymboL

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

90 (

16)

100

84 (

15)

100

79 (

14) 93

73 (

13 91

68 (

12) 87

62 (

11) 83

56 (

10) 78

51 (

9) 72

45 (

8) 66

40 (

7) 58

34 (

6) 51

28 (

5) 42

23 (

4) 33

17 (

3) 24

A = 11 (2) 15

A = 6 (1) 5

Chopper current

Vector

A = 0 (0)

TB62202AFG

2005-04-04

AC Characteristics

(Ta

= 25°C, V

= 24 V, V

= 5 V, 6.8 mH/5.7

)

Characteristics SymboL

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

Clock frequency

CLK

1.0

25 MHz

(CLK)

Minimum clock pulse width

wn (CLK)

STROBE

STROBE (H)

Minimum STROBE pulse width

STROBE (L)

suSIN-CLK

Data setup time

suST-CLK

hSIN-CLK

Data hold time

hCLK-ST

0.1

Output Load ; 6.8 mH/5.7

0.1

pLH (ST)

pHL (ST)

STROBE (

) to VOUT

Output Load; 6.8 mH/5.7

pLH (CR)

1.2

Output transistor switching
characteristic

pHL (CR)

CR to VOUT
Output Load; 6.8 mH/5.7

2.5

µs

Noise rejection dead band time

BLNK

out

1.0 A

200

300

400

CR reference signal oscillation
frequency

osc

560 pF, R

osc

3.6 k

800 kHz

Chopping frequency range

chop (min)

chop (typ.)

chop (max)

Output active (I

out

1.0 A)

Step fixed, Ccp1

0.22

µF,

Ccp2

= 0.01µF

40 100 150

kHz

Chopping frequency

chop

Output active (I

out

= 1.0 A)

CR CLK

= 800 kHz

100 kHz

Charge pump rise time

ONG

Ccp2

= 0.22µF, Ccp = 0.01 µF

= 24 V, V

= 5 V,

RESET

= L H

2 4 ms

TB62202AFG

2005-04-04

Calculation of Set Current

Determining R

and V

ref

determines the set current value.

out

(Max)

(GAIN)

ref

× V

ref

(V) ×

)

(

)

orque

data

serial

input

50%

70,

85,

100,

5.0 is V

ref

(gain) : V

ref

attenuation ratio (typ.).

For example,

to input V

ref

3 V and Torque

100% and to output I

out

0.8 A,

0.75 (0.5 W or more) is required.

Formulas for Calculating CR Oscillation Frequency

(Chopping reference frequency)

The CR oscillation frequency and f

chop

can be calculated by the following formulas:

[Hz]

KA (constant): 0.523

KB (constant): 600

chop

[Hz]

Example : When Cosc = 1,000 pF and Rosc = 2.0 k are connected, f

= 735 kHz.

At this time, the chopping frequency f

chop

is : f

chop

= f

8 = 92 kHz.

Note: f

Charge)

(Dis

(Charge)

CR oscillation CR charge

CR distance

cycle

time

At this time, t (CR-discharge) is subject to the following condition:

600 ns > t (CR-discharge) > 400 ns.

Be sure to set the CR value in accordance with this condition.

TB62202AFG

2005-04-04

CR Circuit Constants

OSC circuit oscillation waveform

The OSC circuit generates the chopping reference signal by charging and discharging the external capacitor Cosc
through current supplied from the external resistor Rosc in the OSC block.
Voltages E1 and E2 in the diagram are set by dividing the V

by approximately 3

5 (E1) and 2

5 (E2).

The actual current chopping time is 1

8 the CR frequency.

[Important: Setting the CR Circuit Constants]

The CR oscillation waveform is converted in the IC to the CLK waveform (CR-CLK signal) and used for control.
If the CR waveform discharge time is set outside the range shown below, the operation of the IC is not guaranteed.
Be sure to set the CR waveform discharge time within the following range.

600 ns > t (CR discharge) > 400 ns

= 0

= 1

= 2

t (CR-charge)

t (CR-dis-charge)

TB62202AFG

2005-04-04

IC Power Dissipation

IC power dissipation is classified into two: power consumed by transistors in the output block and power consumed
by the logic block and the charge pump circuit.

(1) Power consumed by the Power Transistor (calculated with R

= 1.3 )

In Charge mode, Fast Decay mode, or Slow Decay mode, power is consumed by the upper and lower
transistors of the H bridges. The following expression expresses the power consumed by the transistors of a
H bridge.
P

(out)

= 2 (T

) × I

out

(A) × V

(V) = 2 × I

out

^2 × R

·························(1)

The average power dissipation for output under 4-bit micro step operation (phase difference between
phases A and B is 90°) is determined by expression (1).
Thus, power dissipation for output per unit is determined as follows (2) under the conditions below.

= 1.3 (@1.0 A)

out

(Peak : Max) = 0.6 A

= 24 V

= 5 V

(out)

= 2 (T

) × 0.6 (A)^2 × 1.3 () ·················································(2)

= 0.936 (W)

(2) Power consumed by the logic block and IM

The following standard values are used as power dissipation of the logic block and IM at operation.
I

(LOGIC)

= 2 mA (Typ.):

unit

(IM3)

= 12.5 mA (Typ.): operation

unit

(IM1)

= 6.0 mA (Typ.): stop

unit

The logic block is connected to V

(5 V). IM (total of current consumed by the circuits connected to V

and current consumed by output switching) is connected to V

(24 V). Power dissipation is calculated as

follows:

P (Logic and IM) = 5 (V) × 0.002 (A) + 24 (V) × 0.0125 (A) ....................... (3)

= 0.31 (W)

(3) Thus, power dissipation for 1 unit (P) is determined as follows by (2) and (3) above.

= P (out) + P (Logic and IM) = 1.246 (W)

Power dissipation for 1 unit at standby is determined as follows:

(standby)

= 24 (V) × 0.006 (A) + 5 (V) × 0.002 (A)

= 0.154 (W)

When one motor driving = 100 %, power dissipation is determined as follows:

(all)

= 1.246 (W) + 0.154 (W) = 1.4 (W)

For thermal design on the board, evaluate by mounting the IC.

TB62202AFG

2005-04-04

MIXED DECAY Mode Waveforms

(concept of mixed decay mode)

NF is the point where the output current reaches the set current value. RNF is the timing for monitoring the set
current.
In Mixed Decay and Fast Decay modes, where the condition RNF (set current monitor signal) < (output current)
applies, Charge mode is cancelled at the next chopping cycle (charge cancel circuit). Therefore, at the next chopping
cycle, the IC enters Slow + Fast modes (Slow Fast at MDT).

chop

SLOW
DECAY
MODE

CR pin
input
waveform

Set current value

DECAY MODE 0

37.5%
MIXED
DECAY
MODE

RNF

DECAY MODE 1

75%
MIXED
DECAY
MODE

RNF

Set current value

MDT

DECAY MODE 2

FAST
DECAY
MODE

RNF

Set current value

DECAY MODE 3

100% 75% 50%

25%

MDT

Slow

Charge

Slow

Fast

Monitoring
set current
value

Charge

Fast

Charge

Fast

87.5% 62.5%

37.5%

12.5%

Set current value

Monitoring
set current
value

TB62202AFG

2005-04-04

Test Circuit

(A/B unit only. C/D unit conforms to A/B unit.)

1. V

IN (H)

, V

IN (L)

Test method

(H): Set RESET to High and vary the logic input voltage from 0 to 7 V.

Monitor I

and measure the change point (V

= 24 V).

VIN

(L): Set RESET to High and vary the logic input voltage from 5 to 0 V.

Monitor I

and measure the change point.

Setup data

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

DATA

CLK

STROBE

P-GND

STROBE AB

CLK AB

DATA AB

RESET

SETUP

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

osc AB

3.6 k

0.22

Ccp 1

0.01

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560 pF

No reset at testing

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

DD1

, I

DD2

0 V to 5 V

Vary V

IN (H)

, I

IN (L)

RS A

RS B

TB62202AFG

2005-04-04

2. I

IN (H)

IN (L)

DD1

, I

DD2

(A/B unit only. C/D unit conforms to A/B unit.)

Test method

IN (H)

: Set RESET to High, set the the logic input voltage to 5 V, and measure the input current.

IN (H)

: Set RESET to High, set the the logic input voltage to 0 V, and measure the input current.

DD1

: Apply

, input RESET, and measure I

DD2

: Input 6.25 MHz clock and measure the current when the logic is operating. Set output to OPEN.

Setup data

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

DATA

CLK

STROBE

osc AB

3.6 k

0.22

Ccp 1

0.01

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560 pF

No reset at testing

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

DD1

, I

DD2

0 V to 5 V

Vary V

IN (H)

, I

IN (L)

RS A

RS B

P-GND

STROBE AB

CLK AB

DATA AB

RESET

SETUP

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

TB62202AFG

2005-04-04

3. IM

, IM

B unit only. C

D unit conforms to A

B unit.)

Test method

: Set the logic block to non-active (DATA = all 0), V

= 5 V, V

= 24 V, and output to open. Measure the

current input from V

supply. RESET = L

: Set the logic block only to active (CLK = 6.25 MHz), V

= 24 V, and output to open. Measure the

current input from V

supply. RESET = H

Setup data

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

DATA

CLK

STROBE

P-GND

CR AB

STROBE AB

CLK AB

DATA AB

RESET

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

5 V

osc

3.6 k

0.22

Ccp 1

0.01

SETUP

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560 pF

At IM1 testing: RESET

= L (0 V)

At IM2 testing: RESET

= H (5 V)

5 V
0 V
5 V
0 V

5 V
0 V

TB62202AFG

2005-04-04

4. IM

B unit only. C

D unit conforms to A

B unit.)

This is the IM current when all of the circuits, including the output transistors, in the IC are operating.
The IM current includes the current dissipation in the charge pump circuit, output gate loss, and output
predriver.
Because the IM current (IM

) is input from the RS pin, which is also used for the output current, IM

cannot be

measured by the normal testing methods.
Use the method shown below.

Setup data

The serial data PHASE signal (both A and B) switch over to high or low.

Test method

Set output to open, change phase data from 1 0 1 0 and perform switching. When testing, input

phase data at double the chopping frequency (if f

chop

= 100 kHz, fDATA = 200 kHz) and measure the current

value of V

supply.

fDATA = 200 kHz means that the phase switches at 200 kHz.

0 1 2 3 4 5

13 14 15

DATA

CLK

STROBE

5 V

osc

3.6 k

0.22

Ccp 1

0.01

P-GND SETUP

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560 pF

No reset at testing

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

A IM

CR AB

STROBE AB

CLK AB

DATA AB

RESET

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

TB62202AFG

2005-04-04

Number of switchings at phase switching

Number of switchings at actual operation

Number of switchings at actual operation = 2 × number of switchings at phase switching.

Therefore, switching the phase at 2 × chopping cycle matches the number of switchings at actual operation

with the number of switchings at phase switching, and allows the actual current dissipation, IM

, to be

measured.

OFF

One phase switching

(16-bit data input)

Four transistors switching

To V

Load

PGND

One phase switching

(16-bit data input)

Four transistors switching

To V

Load

PGND

Switches by phase data

OFF

Four transistors are switched at one phase switching

Two transistors

switching

OFF

Charge

OFF

Slow

Two transistors

switching

OFF

Four transistors switching

Eight transistors switching

in one chopping cycle

Mode changes three times
in one chopping cycle.

Chopping cycle

Fast

TB62202AFG

2005-04-04

5. I

, I

(A/B unit only. C/D unit conforms to A/B unit.)

Test method

: With

= 24 V, V

= 5 V, and logic input all = 0 applied, set RESET = H, connect the output pins

to GND, and measure the supply current.

: With

= 24 V, V

= 5 V, and logic input all = 0 applied, set RESET = H, connect the output pins

to V

, and measure the supply current.

: With

= 24 V, V

= 5 V, and logic input all = 0 applied, set RESET = L, connect the output pins

to GND, and measure the supply current.

Setup data

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

DATA

CLK

STROBE

5 V

osc

3.6 k

0.22

Ccp 1

0.01

SGND

3 V

, I

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc AB

560 pF

No reset at testing

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

P-GND

CR AB

STROBE AB

CLK AB

DATA AB

RESET

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

TB62202AFG

2005-04-04

6. V

(H to L), V

ref

(GAIN) (when measuring phase A) after measurement

(A/B unit only. C/D unit conforms to A/B unit.)

RS (H to L):

Input torque data = 100% (HH) and vary the voltage between V

and R

pins.

Measure the voltage (V

) when output changes from fixed Charge mode to another mode.

Also measure V

when torque data = 85% (HL), 70% (LH), or 50% (LL) as above and calculate the

ratio using V

value at 100% as reference.

ref (GAIN)

: V

ref (GAIN)

ref

(*)

((*) V

: when torque data = 100%)

Setup data

0 1 2 3 4 5

13 14 15

DATA

CLK

STROBE

P-GND

CR AB

STROBE AB

CLK AB

DATA AB

RESET

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

5 V

osc AB

3.6 k

0.22

Ccp 1

0.01

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560 pF

No reset at testing

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

Oscilloscope

Vary between
0 and 1 V.

TB62202AFG

2005-04-04

7. I

out1

, I

out2

(A/B unit only. C/D unit conforms to A/B unit.)

With L load, perform chopping in Mixed Decay mode. Monitor the output current waveform and measure the
various output currents at constant current operation.

Setup data

5 V

0.22

Ccp 1

0.01

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

No reset at testing

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

RS B

RS A

Monitors

current

waveform.

P-GND

STROBE AB

CLK AB

DATA AB

RESET

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

0 1 2 3 4 5

13 14 15

Set to100%

DATA

CLK

STROBE

Output current

value (set

current value)

Current

waveform

Charge

Slow

MDT

100%

Fast

Charge

Slow

Fast

Measurement of
peak current

TB62202AFG

2005-04-04

8. I

(when measuring phase A)

(A/B unit only. C/D unit conforms to A/B unit)

With L input to RESET , connect V

and R

to the power supply, and measure the current input to the R

pin. (Either drop all the input pins to GND level or input all Low data to the DATA pin, then perform
measurement. At that time, leave all other output pins open.)

Setup data

P-GND

CR AB

STROBE AB

CLK AB

DATA AB

RESET

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

osc

3.6 k

0.22

Ccp 1

0.01

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560 pF

RESET

= L

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

DATA

CLK

STROBE

TB62202AFG

2005-04-04

9. R

ON (D-S)

ON (S-D)

when measuring output A

(A/B unit only. C/D unit conforms to A/B

unit.)

Input the current setting data (HHHH signal) to the DATA pin and measure the voltage between V

and OUT

when I

out

= 1000 mA or the voltage between OUT and GND. Then, change the phase and repeat measurement.

At that time, leave the output pins which are not measured open.

Setup data

(Vary the phase data during testing.)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

DATA

CLK

STROBE

P-GND

CR AB

STROBE AB

CLK AB

DATA AB

RESET

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

5 V

osc

3.6 k

0.22

Ccp 1

0.01

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560 pF

No reset at testing

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

Curve tracer

TB62202AFG

2005-04-04

10. V

ref

, I

ref

(A/B unit only. C/D unit conforms to A/B unit.)

ref

: Vary V

ref

= 2 to V

- 1 V and confirm that output is on.

ref

: When

= 24 V and V

= 5 V, apply the specified voltage of 3 V to the V

ref

and monitor the current

flow value.

5 V

osc AB

3.6 k

0.22

Ccp 1

0.01

SGND

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc AB

560 pF

No reset at testing

RESET

= 5 [V]

Oscilloscope

Monitor

ref

(*) Vary V

ref

= 2 to V

- 1.0 V

*: When measuring I

ref

fix V

ref

= 3 V and

measure.

P-GND

CR AB

STROBE AB

CLK AB

DATA AB

RESET

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

TB62202AFG

2005-04-04

11. T

TSD, T

TSD

(Measure in an environment such as an constant temperature chamber where

the temperature for the IC can be freely changed) (A/B unit only. C/D unit conforms to A/B
unit.)

TSD:

Increase the ambient temperature. Measure the temperature when output stops.

TSD: Gradually lower the temperature from the level when the TSD circuit was operating (output off). At

that time, control the RESET input thus : H L H L. Output will begin at a certain

temperature level.
T

TSD is the difference between the temperature at which output begins and the temperature at

which TSD is triggered.

Setup data

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

DATA

CLK

STROBE

P-GND

CR AB

STROBE AB

CLK AB

DATA AB

RESET

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

5 V

osc

3.6 k

0.22

Ccp 1

0.01

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560 pF

No reset at testing

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

Curve tracer

TB62202AFG

2005-04-04

12. V

DDR

(A/B unit only. C/D unit conforms to A/B unit.)

Monitor the output pins. Increase the V

voltage from 0. Measure the V

value when output starts.

Next, decrease the V

voltage and measure the V

value when output stops.

Setup data

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

DATA

CLK

STROBE

5 V

osc

3.6 k

0.22

Ccp 1

0.01

SGND

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

osc

560 pF

No reset at testing

RESET

= 5 [V]

RS A

Oscilloscope

SGND

5 V

Vary from 0 V

RS B

3 V

5 V
0 V
5 V
0 V

5 V
0 V

P-GND

CR AB

STROBE AB

CLK AB

DATA AB

RESET

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

TB62202AFG

2005-04-04

13. V

(A/B unit only. C/D unit conforms to A/B unit.)

With the CLK signal and DATA (all High) input, increase the V

voltage from 0.

Measure the V

value when output starts.

Next, decrease the V

voltage and measure the V

value when output stops.

Setup data

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

DATA

CLK

STROBE

P-GND

CR AB

STROBE AB

CLK AB

DATA AB

RESET

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

5 V

osc

3.6 k

0.22

Ccp 1

0.01

SGND

: PGND
: SGND (V

)

Ccp 2

SGND

osc

560 pF

No reset at testing

RESET

= 5 [V]

RS A

Oscilloscope

Vary from 0 V

RS B

3 V

5 V

5 V
0 V
5 V
0 V

5 V
0 V

TB62202AFG

2005-04-04

14. Overcurrent protector circuit

(ISD) (To measure output A : )

(A/B unit only. C/D unit conforms to A/B unit.)

Test method: To monitor operating current of the overcurrent protector circuit when output A is short-circuited

to the power supply

Input the current setting data (HHHH signal) to the DATA pin. If short-circuited to the supply, measure the
lower output transistors. If short-circuited to ground, measure the upper output transistors (see how to measure
R

When measuring R

, increase the current flow. There is a current value at which output is switched off and

cannot be measured. This value is the set current value for the overcurrent protector circuit.

Make sure to leave open the output pins not being measured.
Note that if the temperature changes, the value may fluctuate. Try to avoid applying power to the IC by
one-shot measuring.

Setup data

(Example : The phase signal must be changed depending on the pin.)

5 V

osc AB

3.6 k

0.22

Ccp 1

0.01

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc AB

560 pF

At measuring, non-reset

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

Curve tracer

P-GND

CR AB

STROBE AB

CLK AB

DATA AB

RESET

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

DATA

CLK

STROBE

TB62202AFG

2005-04-04

15. Current vector

(A/B unit only. C/D unit conforms to A/B unit.)

Perform chopping in Mixed Decay mode with load L. Monitor the output current waveform and measure the output
current at constant current operation. At this time, vary the 4-bit data for current setting and measure the
current values. Using the set output current as 100%, calculate the output current ratio.

P-GND

STROBE AB

CLK AB

DATA AB

RESET

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

5 V

osc

3.6 k

0.22

Ccp 1

0.01

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560 pF

At measuring, non-reset

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

RS B

RS A

Monitor

current

waveform

100%

(example)
71%

Output current

TB62202AFG

2005-04-04

16. f

CLK

, t

w (CLK)

, t

wp (CLK)

wn (CLK)

, t

STROBE

, t

STROBE (H)

, t

STOBE (L)

suSIN-CLK

, t

suST-CLK

, t

hSIN-CLK

, t

hCLK-ST

(A/B unit only. C/D unit conforms to A/B unit.)

Input any data at f

CLK

(max), perform chopping, and monitor the output waveform.

For the measuring points, see the timing chart below.

Setup data

Measuring points

0 1 2 3 4 5

13 14 15

DATA

CLK

STROBE

thSIN-CLK

CLK

STROBE

DATA

50%

tsuSIN-CLK

tSTROBE (L)

tSTROBE (H)

50%

tsuST-CLK

DATA15

50%

thCLK-ST

DATA0

twn (CLK) twp (CLK)

tw (CLK)

tSTROBE

P-GND

CR AB

STROBE AB

CLK AB

DATA AB

RESET

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

5 V

osc

3.6 k

0.22

Ccp 1

0.01

SGND

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

osc

560 pF

No reset at testing

RESET

= 5 [V]

RS A

RS B

3 V

5 V
0 V
5 V
0 V

5 V
0 V

5 V

TB62202AFG

2005-04-04

17. OSC-fast delay, OSC-charge delay

(A/B unit only. C/D unit conforms to A/B unit.)

Fix the output current value in Mixed Decay mode and turn the output on. Measure the time until the output
switches from the CR pin waveform and the output voltage waveform.

Setup data

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

out A

(Mode)

50%

50% 50%

50%

Osc-charge delay

Osc-fast delay

Slow

Charge Fast

Charge

Bottom

Top

DATA

CLK

STROBE

5 V

osc

3.6 k

0.22

Ccp 1

0.01

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560 pF

No reset at testing

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

RS B

RS A

P-GND

CR AB

STROBE AB

CLK AB

DATA AB

RESET

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

TB62202AFG

2005-04-04

18. t

pHL (ST)

, t

pLH (ST)

, t

(A/B unit only. C/D unit conforms to A/B unit.)

Setup data

Switch PHASE every 130 µs and measure the output pin voltage and the STROBE signal.

[Oscilloscope waveform (example)]

0 1 2 3 4 5

13 14 15

DATA

CLK

STROBE

50%

STROBE

OUTPUT

Voltage A

OUTPUT

Voltage A

50%

pHL (ST)

130

µs

pLH (ST)

90%

50%

10%

P-GND

CR AB

STROBE AB

CLK AB

DATA AB

RESET

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

RS A

5 V

osc

3.6 k

0.22

Ccp 1

0.01

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560 pF

No reset at testing

RESET

= 5 [V]

5 V
0 V
5 V
0 V

5 V
0 V

RS B

Monitor

= 5.7

6.8 mH

TB62202AFG

2005-04-04

19. t

BRANK

(A/B unit only. C/D unit conforms to A/B unit.)

BRANK

is the dead time band for avoiding malfunction caused by noise. Apply sufficient differential voltage

(when V

ref

= 3 V, 0.6 V or higher) to V

-R

and apply duty. When the pulse width reaches a certain value,

triggering feedback and changing the output. Check the value.

Setup data

0 1 2 3 4 5

13 14 15

DATA

CLK

STROBE

P-GND

CR AB

STROBE AB

CLK AB

DATA AB

RESET

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

RS A

5 V

osc AB

3.6 k

0.22

Ccp 1

0.01

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc AB

560 pF

No reset at testing

RESET

= 5 [V]

RS B

5 V
0 V
5 V
0 V

5 V
0 V

Apply pulse to the R

pin so that the

= V

voltage

- 1.0 V.

pin voltage

Output operation

Measure the pulse width

where output changes.

TB62202AFG

2005-04-04

20. f

chop

(min), f

chop

(max)) (A/B unit only. C/D unit conforms to A/B unit.)

Change the R

osc

and C

osc

values and measure the frequency on the CR pin using the oscilloscope.

At this time, 1

8 of the frequency of the measured CR waveform is f

chop

Oscilloscope waveform

(example)

RS A

osc AB

3.6 k

0.22

Ccp 1

0.01

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc AB

560 pF

RS B

Oscilloscope

P-GND

CR AB

STROBE AB

CLK AB

DATA AB

RESET

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

1/8 f

chop

(SYNC)

= f

= 0

= 1

TB62202AFG

2005-04-04

21. t

ONG

(A/B unit only. C/D unit conforms to A/B unit.)

Apply V

and V

and change RESET from L to H.

Measure the time until the CcpA pin becomes V

+ V

× 90%.

ONG

50%

5 V

0 V

RESET

+ V

+ (V

× 90%)

RS A

5 V

osc

3.6 k

0.22

Ccp 1

0.01

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560 pF

At measuring, change
from reset to non-reset.

RS B

5 V
0 V
5 V
0 V

5 V
0 V

P-GND

CR AB

STROBE AB

CLK AB

DATA AB

RESET

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

TB62202AFG

2005-04-04

22. Mixed decay timing

(A/B unit only. C/D unit conforms to A/B unit.)

With V

= 24 V, V

= 5 V, RESET = H, change the SETUP pin from L to H and overwrite the MIXED DECAY

TIMING TABLE.
Then change the SETUP pin from H to L. With load L, perform chopping and monitor the output current
waveform at that time. Confirm that the switching timing from Slow Decay Mode to Fast Decay Mode within an
fchop cycle is the specified MIXED DECAY TIMING.
(Depending on the load L value and the test environment, chopping may be performed every two cycles or there
may be no Slow Decay Mode. If so, conditions, for example, load condition, may need to be changed.

P-GND

STROBE AB

CLK AB

DATA AB

RESET

SETUP

ref AB

M A

RS A

RS B

M B

)

Ccp C

Ccp B

Ccp A

RS A

5 V

osc

3.6 k

0.22

Ccp 1

0.01

SGND

3 V

24 V

: PGND
: SGND (V

)

Ccp 2

SGND

5 V

osc

560 pF

RS B

5 V
0 V
5 V
0 V

5 V
0 V

At measuring, non-reset

RESET

= 5 [V]

5 V

Output current value

(set current value)

MDT

100% 0%

MDT

Charge

Slow

Fast

Current waveform

TB62202AFG

2005-04-04

Waveforms in Various Current Modes

(Ideal Waveform)

Normal MIXED DECAY MODE Waveform

When NF is after MIXED DECAY Timing

chop

RNF

Set current value

MDT (MIXED DECAY TIMING) point

NF is the point at which the output current
reaches the set current value.

CR CLK
signal

out

Set current
value

12.5% MIXED
DECAY MODE

RNF

Set current value

out

Set current
value

37.5% MIXED
DECAY MODE

Fast Decay mode after Charge mode.

MDT (MIXED DECAY TIMING) point

RNF

STROBE signal input

TB62202AFG

2005-04-04

In MIXED DECAY MODE, when the output current > the set current value

FAST DECAY MODE Waveform

Set current value

MDT (MIXED DECAY TIMING) point

Set
current
value

RNF

STROBE signal input

out

12.5%
MIXED
DECAY
MODE

chop

CHARGE MODE for one f

chop

cycle after STROBE signal input

RNF

Because the set current value > the

output current, no CHARGE MODE in

the next cycle.

Set current value

Set current
value

RNF

STROBE signal input

out

FAST DECAY
MODE
(0% MIXED
DECAY MODE)

chop

Response delay time

NF is the point at which the output
current reaches the set current value.

RNF

Because the set current value > the output current, CHARGE

MODE

NF FAST DECAY MODE in the next cycle, too

Because the set current value > the output current,

FAST DECAY MODE in the next cycle, too

TB62202AFG

2005-04-04

STROBE Signal, Internal CR CLK, and output Current Waveform

(When STROBE Signal is input in SLOW DECAY MODE)

When STROBE signal is input, the chopping counter (CR-CLK counter) is forced to reset at the next CR-CLK
timing.
Because of this, compared with a method in which the counter is not reset, response to the input data is faster.
(The delay time, the theoretical value in the logic portion, is expected to be a one-cycle CR waveform: 1.25 µS

@100 kHz CHOPPING.)
When the CR-CLK counter is reset due to STROBE signal input, CHARGE MODE is entered momentarily due to
current comparison.

Note: In FAST DECAY MODE, too, CHARGE MODE is entered momentarily due to current comparison.

Set current
value

STROBE signal input

out

chop

37.5% MIXED DECAY MODE

MDT

RNF

MDT

RNF

Momentarily enters
CHARGE MODE

Reset CR-CLK
counter here

TB62202AFG

2005-04-04

Current Modes

(MIXED (

= SLOW

FAST) Decay Mode Effect)

Sine wave in increasing (Slow Decay Mode (Charge

+ Slow + Fast) normally used)

Sine wave in decreasing (When using MIXED DECAY Mode with large attenuation ratio (MDT%) at attenuation)

Sine wave in decreasing (When using MIXED DECAY Mode with small attenuation ratio (MDT%) at attenuation)

Note: The above charts are schematics. The actual current transient responses are curves.

Set current
value

Slow

Charge

Fast

Slow

Fast

Charge

Fast Charge

Fast

Slow

Set current
value

Charge

Slow

Set current
value

Charge

Fast

Slow

Because current attenuates slowly, it takes a
long time for the current to follow the set current
value (or the current does not follow).

Set current
value

Slow

Charge

Fast

Slow

Charge

Fast

Slow

Fast

Charge

Set current
value

Because current attenuates so quickly, the current
immediately follows the set current value.

TB62202AFG

2005-04-04

Output Transistor Operating Mode

Output Transistor Operation Functions

CLK U

CHARGE ON OFF OFF

SLOW OFF OFF

FAST OFF ON ON

OFF

Note: The above table is an example where current flows in the direction of the arrows in the above figures.

When the current flows in the opposite direction of the arrows, see the table below.

CLK U

CHARGE OFF ON ON OFF

SLOW OFF OFF

FAST ON OFF

OFF

PGND

(Note)

Load

PGND

(Note)

Load

PGND

(Note)

Load

Charge mode

(Charges coil power)

Slow mode

(Slightly attenuates coil power)

Fast mode

(Drastically attenuates coil power)

To V

TB62202AFG

2005-04-04

Output Transistor Operating Mode 2

(Sequence of MIXED DECAY MODE)

The constant current is controlled by changing mode from Charge Slow Fast.

Set current

50%

Charge Mode

50%

Slow Mode

Fast Mode

OUTPUT
voltage A

OUPUT
current

PGND

OUT A

To V

TB62202AFG

2005-04-04

Current Discharge Path when Current Data

0000 are input during operation

In Slow Decay Mode, when all output transistors are forced to switch off, coil energy is discharged in the following
MODES :

Note: Parasitic diodes are located on dotted lines. In normal MIXED DECAY MODE, the current does not flow to the

parasitic diodes. However, when signal 0000 is input during operation, the current flows to them.

As shown in the figure at right, an output transistor has parasitic diodes.
To discharge energy from the coil, each transistor is switched on allowing current to flow in the reverse direction to
that in normal operation. As a result, the parasitic diodes are not used. If all the output transistors are forced to
switch off, the energy of the coil is discharged via the parasitic diodes.

PGND

OFF

(Note)

Load

PGND

OFF

(Note)

Load

PGND

(Note)

Load

Charge mode

Slow Decay mode

Forced OFF mode

OFF

Input Current DATA

= 0000

OFF

To V

power supply

TB62202AFG

2005-04-04

Power Supply Sequence

(Recommended)

Note 1: If the V

drops to the level of the V

DDR

or below while the specified voltage is input to the V

pin, the IC is

internally reset. This is a protective measure against malfunction. Likewise, if the V

drops to the level of the

or below while regulation voltage is input to the V

, the IC is internally reset as a protective measure

against malfunction. To avoid malfunction, when turning on V

or V

, we recommend you input the

RESET signal at the above timing.

It takes time for the output control charge pump circuit to stabilize. Wait up to t

ONG

time after power on

before driving the motors.

Note 2: When the V

value is between 3.3 to 5.5 V, the internal reset is released, thus output may be on. In such a

case, the charge pump cannot drive stably because of insufficient voltage. We recommend the RESET state
be maintained until V

reaches 20 V or more.

Note 3: Since V

0 V and V

voltage within the rating are applied, output is turned off by internal reset. At that

time, a current of several mA flows due to the Pass between V

and V

DD (max)

DD (min)

DDR

GND

M (min)

GND

NON-RESET

RESET

Internal reset

RESET

input
*

Takes up to t

ONG

until operable.

Non-operable area

RESET

TB62202AFG

2005-04-04

Relationship between V

and V

is the voltage of the CcpA pin. It is the highest voltage in this IC (power supply for driving the upper gate of the

H bridge).

V charge Up is the voltage to boost V

to V

. Usually equivalent to V

Supply voltage V

(V)

(& Vcharge up)

vol

t
age

, charg

e
up volt

age

volt

age

(V)

0 5 10 15 20 25 30 35 40

VMR

Recommended operation area

Usable area

Maximum

Input RESET.

(

RESET

= 0 V)

VH voltage

VM voltage

Charge up voltage

VDD = 5 V
Ccp1

= 0.22 µF

Ccp2

= 0.02 µF

VH = VDD + VM (CcpA)

TB62202AFG

2005-04-04

Operation of Charge Pump Circuit

Initial charging

(1) When RESET is released, T

is turned ON and T

turned OFF. Ccp2 is charged from Ccp2 via Di1

(This is the same as when TSD and ISD are operating and the IC is restored from Reset state.)

(2) T

is turned OFF, T

is turned ON, and Ccp1 is charged from Ccp2 via Di2.

(3) When the voltage difference between V

and V

(CcpA pin voltage = charge pump voltage) reaches V

higher, operation halts (Steady state : Because the capacitor is naturally discharged, the IC is continually
charging to the capacitor).

Actual operation

(4) Ccp1 charge is used at fchop switching and the V

potential drops.

(5) Charges up by (1) and (2) above.

= V

+ V

= charge pump voltage

= charge pump current

= gate block power dissipation

= 5 V

= 24 V

Comparator

Controller

Output

Output
H switch

Ccp 1

0.22

Ccp A

Ccp B

Ccp C

Ccp 2

0.01

Di2

Di1

Di3

(2)

(1)

(2)

3/16/21/34

1/18/19/36

Output switching

Initial charging

Normal state

(1)

(2) (3)

(4)

(5)

(4)

(5)

Charge p

u
mp voltage

TB62202AFG

2005-04-04

External Capacitors for Charge Pumps

When V

= 5V, fchop = 100 kHz, and L = 10 mH is driven with V

= 24 V, I

out

= 1100 mA, the theoretical values

for Ccp1 and Ccp2 are as shown below:

Combine Ccp1 and Ccp2 as shown in the shaded area in the above graph.
Select values 10: 1 or more for Ccp1: Ccp2.
When making a setting, evaluate properly and set values with a margin.

Ccp 1 Ccp 2

Ccp 1 capacitance (

µF)

Ccp 2

cap

a
ci

t
ance

(
µ

0.5

0.45

0.4

0.35

0.3

0.25

0.2

0.15

0.1

0.05

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

0.045

0.05

Usable area

Ccp 1

= (NG)

Ccp 2

= (OK)

Recommended area

Recommended value

TB62202AFG

2005-04-04

Charge Pump Rise Time

ONG

: Time taken for capacitor Ccp2 (charging capacitor) to fill up Ccp1 (capacitor used to save charge) to V

after a reset is released.

The internal IC cannot drive the gates correctly until the voltage of Ccp1 reaches V

+ V

. Be sure to

wait for t

ONG

or longer before driving the motors.

Basically, the larger the Ccp1 capacitance, the longer the initial charge-up time but the smaller the
voltage fluctuation.
The smaller the Ccp1 capacitance, the shorter the initial charge-up time but the larger the voltage
fluctuation.
Depending on the combination of capacitors (especially with small capacitance), voltage may not be
sufficiently boosted. Thus, use the capacitors under the capacitor combination conditions (Ccp1 = 0.22 µF,

Ccp2 = 0.01 µF) recommended by Toshiba.

50%

+ V

+ (V

× 90%)

5 V

0 V

RESET

ONG

TB62202AFG

2005-04-04

Operating Time for Overcurrent Protector Circuit

(ISD non-sensitivity time and ISD operating time)

A non-sensitivity time is set for the overcurrent protector circuit to avoid misdetection of overcurrent due to spike
current at irr or switching.
The non-sensitivity time synchronizes with the frequency of the CR for setting the chopping frequency. The
non-sensitivity time is set as follows :
Non-sensitivity

time

= 4 × CR cycle

The time required for the ISD to actually operate after the non-sensitivity time is as follows :
Minimum:

× CR cycle

Maximum:

× CR cycle

Therefore, from the time overcurrent flows to the output transistors to the time output halts is as follows.
Note that ideally, the operating time is the operating time when overcurrent flows. Depending on the output control
mode timing, the overcurrent protector circuit may not be triggered.
Therefore, to ensure safe operation, add a fuse to the V

power supply for protection.

The fuse capacity would vary according to the use conditions. However, select a fuse whose capacity avoids any
operating problems and does not exceed the power dissipation for the IC.

Point where overcurrent flows to output transistors (overcurrent status start)

Output halts (Reset status)

CR oscillation

(basic chopping waveform)

(Non-sensitivity time)

MIN

MAX

ISD operating time

MIN

MAX

ISD BLANK time

TB62202AFG

2005-04-04

Application Operation Input Data

(Example: 2-Phase Excitation Mode)

TORQUE

DECAY

PHASE B DECAY A

DECAY

PHASE A

Bit

4 5

10 11 12 13 14

1 1

0 1 1

0 1 1 1 1

2 1

0 1 1

0 1 1 1 1

3 1

0 1 1

0 1 1 1 1

4 1

0 1 1

0 1 1 1 1

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.
For the input conditions, see page 9, Functions.
We recommend Mixed Decay mode (37.5%) as Decay mode. Set torque to 100%.

Output current waveform of 2-phase excitation sine wave

Note: We recommended 2-phase excitation drive in 37.5% Mixed Decay mode.

Please refer to the caution of 2-phase excitation mode on next page.

(%)

100

-100

Phase A

Phase B

TB62202AFG

2005-04-04

Application Operation Input Data

(Example: 1-2 Phase Excitation Mode Typ.A)

TORQUE

DECAY

PHASE B

DECAY

PHASE A

Bit

4 5

10 11 12 13 14

1 1

0 1 1

0 1 1 1 1

2 1

0 1 0

0 1 1 1 1

3 1

0 1 1

0 1 1 1 1

4 1

0 1 1

0 1 0 0 0

5 1

0 1 1

0 1 1 1 1

6 1

0 1 0

0 1 1 1 1

7 1

0 1 1

0 1 1 1 1

8 1

0 1 1

0 1 0 0 0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.
For the input conditions, see page 10, Functions.
We recommend Mixed Decay Mode (37.5%) as Decay Mode.
Set torque to 100%.
When using this excitation mode, high efficiency can be achieved by setting the phase data to 10% (-10%). Set

current values in the order +100% -10% -100% +10%.

Output Current Waveform of 1-2 Phase Excitation Sine Wave

(Typ. A)

(%)

100

-10

-100

Phase A

(%)

100

-10

-100

Phase B

TB62202AFG

2005-04-04

Points for Control that Includes Current of 0%

In modes other than 2-Phase Excitation mode (from 1-2 Phase Excitation mode to 4W1-2 Phase Excitation mode),
when the current is controlled to 0%, the TB62201F's output transistors are all turned off.
At the time, the coil's energy returns to the power supply through the parasitic diodes. If the same current is
applied several times and is within the rated current, then : the power consumed by the on-resistance when current
flows to the output MOS will be less than the power consumed when current is applied to the parasitic diodes.
Therefore, when controlling the current, rather than setting 0%, set the current to the next step beyond 0% (the
minimum step in the reverse direction) for better power dissipation results.
However, if the 0% (actually 10%) current cycle is long, the power dissipation may be greater than in Off mode
because of the need for constant-current control.
Therefore, Toshiba recommend setting the current according to the actual operating pattern. (1-2 Phase Excitation
mode is the most effective.)

Flyback diode mode

Non-flyback diode mode

Output off

period

Diode parasite

Constant-

current

control

Constant-

current

control

[%]

100

-10

-100

Load

To V

power supply

OFF

Forced Off mode

PGND

Charge

The coil's energy returns through
the parasitic diodes.
Because V

< V

, the power

dissipation is large.

Constant-

current

control

Constant-

current

control

[%]

100

-10

-100

Charge

Specifies a level of 10%,
either side of 0.

OFF

Load

To V

Charge mode

PGND

The coil's energy returns through
the MOS, which is turned on.
Then the coil is charged to a level
of 10%.
The power dissipation is smaller
than when the energy is returned
via the parasitic diode.
(However, the longer the

±10%

rated current control time, the
longer the period of current
dissipation.)

Constant-

current

control

TB62202AFG

2005-04-04

Application Operation Input Data

(Example: 1-2 Phase Excitation mode Typ.B)

TORQUE

MDMB

DECAY

PHASE

MDM A

DECAY

PHASE

Bit

4 5

10 11 12 13 14

1 1

0 1 1

0 0 0 0 0

2 1

0 0 0

0 0 0 0 1

3 1

0 0 0

0 1 1 1 1

4 1

0 0 0

0 0 0 0 1

5 1

0 1 1

0 0 0 0 0

6 1

0 0 0

0 0 0 0 1

7 1

0 0 0

0 1 1 1 1

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.
For the input conditions, see page 10, Functions.
We recommend Mixed Decay Mode (37.5%) as Decay Mode.
Set torque to 100%. Same as 1-2 phase excitation (typ. A) in the previous section, power dissipation can be reduced
by changing 0% level to 10% or -10%.

Output Current Waveform of 1-2 Phase Excitation Sine Wave

(Typ. B)

Phase A

(%)

100

-100

-71

Phase B

TB62202AFG

2005-04-04

Application Operation Input Data

(Example: 4-bit micro steps)

(4-bit micro steps

= W1-2 phase excitation drive)

TORQUE

DECAY

PHASE

DECAY

PHASE

Bit 0

3 4

10 11

0 1

0 0 0 0 0

0 0

0 0 0 1 0

0 0

0 0 0 0 1

0 0

0 0 0 1 1

0 0

0 1 1 1 1

0 0

0 1 1 1 1

0 0

0 0 0 1 1

0 0

0 0 0 0 1

0 0

0 0 0 1 0

10 1

0 1

0 0 0 0 0

11 1

0 1

1 0 0 0 0

12 1

0 0

1 0 0 1 0

13 1

0 0

1 0 0 0 1

14 1

0 0

1 0 0 1 1

15 1

0 0

1 1 1 1 1

16 1

0 0

0 1 1 1 1

17 1

0 0

0 0 0 1 1

18 1

0 0

0 0 0 0 1

19 1

0 0

0 0 0 1 0

20 1

0 1

0 0 0 0 0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.
For the input conditions, see page 9, Functions.
We recommend Slow Decay Mode in the ascending direction of the sine wave ; Mixed Decay Mode (37.5%) in the
descending direction. Set torque to 100%.

TB62202AFG

2005-04-04

Output Current Waveform of Pseudo Sine Wave

(4-bit micro steps)

5 micro-step from 0 to 90° drive is possible by combining Current DATA (AB & CD) and phase data.
For input Current DATA at that time, see section on Current X in the list of the Functions.
Depending on the load, the optimum condition changes for selecting MIXED DECAY MODE when the sine wave
rises and falls. Select the appropriate MIXED DECAY TIMING according to the load.

100

(%)

-100

-92

-71

-38

Phase A

Phase B

STEP

TB62202AFG

2005-04-04

Application Operation Input Data

(Example: 3-bit micro steps)

(3-bit micro steps

= 2W1-2 phase excitation drive)

TORQUE

DECAY

PHASE

DECAY

PHASE

Bit

10 11 12 13 14

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.
For the input conditions, see page 10, Functions.
We recommend Slow Decay Mode in the ascending direction of the sine wave; Mixed Decay Mode (37.5%) in the
descending direction. Set torque to 100%.

TB62202AFG

2005-04-04

Output Current Waveform of Pseudo Sine Wave

(3-bit micro steps)

9 micro-step from 0 to 90° drive is possible by combining Current DATA (AB & CD) and phase data.
For input Current DATA at that time, see section on Current X in the list of the Functions.
Depending on the load, the optimum condition changes for selecting MIXED DECAY MODE when the sine wave
rises and falls. Select the appropriate MIXED DECAY TIMING according to the load.

100

[%]

-100

STEP

-83

-38

-20

-92

-98

-71

-56

Phase A

Phase B

TB62202AFG

2005-04-04

Application Operation Input Data

(Example: 4-bit micro steps)

TORQUE

DECAY

PHASE

DECAY

PHASE

Bit

10 11 12 13 14

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

1 1 1 0

0 1 0

TB62202AFG

2005-04-04

TORQUE

DECAY

PHASE

DECAY

PHASE

Bit

10 11 12 13 14

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

0 1 1

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

1 1 1 0

1 1 0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.
For the input conditions, see page 10, Functions. In the above input data example, Decay mode has a Mixed Decay
mode (37.5%) setting for both the rising and falling directions of the sine wave, and a torque setting of 100%.

TB62202AFG

2005-04-04

4W1-2 Output Current Waveform of Pseudo Sine Wave

(4-bit micro steps)

17 micro-step from 0 to 90° drive is possible by combining Current DATA (AB & CD) and phase data.
For input Current DATA at that time, see section on Current X in the list of the Functions.
Depending on the load, the optimum condition changes for selecting MIXED DECAY MODE when the sine wave
rises and falls. Select the appropriate MIXED DECAY TIMING according to the load.

-100

STEP

-98

-96

-88

-92

-77

-71

-56
-63

-47

-38

-29

-20

-10

-83

100

[%]

Phase A

Phase B

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TB62202AFG

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TB62202AFG