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TB62300FG
2005-04-04
1
TOSHIBA BiCD IC Silicon Monolithic
TB62300FG
Dual Full-Bridge Driver for DC Motor
The TB62300FG is a dual brushed DC motors driver IC
employing a chopper-based forward/reverse full-bridge
mechanism. It controls two brushed DC motors at high precision.
The motor supply voltage is up to 40 V and the V
DD
supply
voltage is 5.0 V.
Features
A single IC can drive two brushed DC motors.
Monolithic Bi-CMOS IC
Low ON-resistance (R
on
) = 0.3 (T
j
= 25C at 2.0 A typ.)
Selectable current control: PWM current control using the
PHASE pin or serial control
5-bit DA converter for specifying current value and 2-bit DA converter for determining torque
MIXED DECAY mode enables specification of current decay rate in four steps.
Self-oscillation chopping frequency with external resistor and capacitor
High-speed chopping at 100 kHz or higher
ISD, TSD, and POR (V
DD
/V
M
) protection circuits
Charge pump circuit (two external capacitors) for driving output
36-pin package: HSOP36 with heat sink
Output voltage: 40 V (max)
Output current: 2.5 A max (in steady-state phase) or 8 A max (pulsed output)
Note: The values specified in this document are designed values, which are not guaranteed.
Weight: 0.79 g (typ.)
TB62300FG
2005-04-04
2
Block Diagram
1.
Overview (for single axis)
High-voltage (V
M
)
Logic data
Analog data
IC pin
DATA
CLK
STROBE
R
S
Ccp 2
Ccp 1
Chopping reference
circuit
Mixed decay timming,
table logic circuit
Current feedback circuit
Protection circuit
V
ref
16-bit latch
Current range
controller
(2-bit D/A)
Current value controller
(5-bit D/A)
V
RS
circuit
R
S
comparator
circuit
Charge pump
circuit
Waveform
squaring
circuit
Chopping
waveform
generator
circuit
Output control circuit
Mixed decay control
Output pre driver
TSD
circuit
ISD
circuit
V
DDR
/V
MR
circuit
CR
V
M
Sleep
Circuits used to set current value
16-bit shift register
Out X
Output circuit
(H-bridge)
V
DD
MODE
PHASE
ENABLE
BRAKE
Brushed DC
Motor
Current control data logic circuit
TB62300FG
2005-04-04
3
Pin Assignment
Note: When designing a ground line, make sure that all ground pins are connected to the same ground trail and
remember to take heat radiation into account.
When pins that are used to toggle between modes are controlled by a switch, pull up or down the pins to avoid
high impedance.
The IC may be destroyed due to short circuit between outputs, to supply, or to ground. Design output lines,
V
DD
(V
M
) lines and ground lines with great care.
When power supply pins (V
M
, R
S
, OUT, P-GND, V
SS
and C
CP
) that are exposed to high current, or logic input
pins are not connected correctly, excessive current or malfunction may cause the IC to break down.
R
S A
V
REF A
R
S B
V
REF B
CR
Ccp 1
Ccp 2
Ccp 3
LGND
NC
TSTO
TSTI
BRAKE A
NC
OUT A
-
PGND
OUT A
+
ENABLE B
ENABLE A
PHASE B
PHASE A
DATA B
DATA A
CLK B
CLK A
STROBE B
STROBE A
MODE B
MODE A
NC
OUT B
-
OUT B
+
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
LGND
BRAKE B
V
M
SLEEP
PGND
TB62300FG
2005-04-04
4
Pin Description
Pin
Number
Symbol Function
Remarks
1 R
S A
A-ch output power supply pin (current
detection pin)
Reference pin for A-axis supply voltage
2 V
REF A
A-ch reference voltage input pin
Reference power supply pin for A-axis current
3 V
REF B
B-ch reference voltage input pin
Reference power supply pin for B-axis current
4
CR
External chopping reference pin
Pin used to set the chopping frequency
5 V
M
Supply voltage monitor pin
Monitor (reference) pin for motor supply voltage
6
Ccp 1
Charge pump capacitor pin
Pin for connecting a charge pump capacitor
7
Ccp 2
Charge pump capacitor pin
Pin for connecting a charge pump capacitor
8
Ccp 3
Charge pump capacitor pin
Pin for connecting a charge pump capacitor
9 V
DD
Logic power supply
Logic supply current input pin
10
NC
NC pin
Note: Usually, leave this pin open.
11
TSTO
Test pin (usually not used)
Note: Usually, leave this pin open.
12
TSTI
Test pin (usually not used)
Note: Usually, connect this pin to LGND.
13
BRAKE A
A-ch brake mode pin
Forced brake mode
14
BRAKE B
B-ch brake mode pin
Forced brake mode
15
NC
NC pin
Note: Usually, leave this pin open.
16 OUT
A
-
A-ch negative output pin
A
- output pin
17
PGND
V
M
ground
Power ground
18
OUT A
+
A-ch positive output pin
A
+ output pin
19 OUT
B
+
B-ch positive output pin
B
+ output pin
20 PGND
V
M
ground
Power ground
21 OUT
B
-
B-ch negative output pin
B
- output pin
22
NC
NC pin
Note: Usually, leave this pin open.
23
MODE A
A-ch data mode switching pin
Pin used to toggle between serial input and PWM control
24
MODE B
B-ch data mode switching pin
Pin used to toggle between serial input and PWM control
25
STROBE A
A-ch latch signal input pin
Data input: latched on rising edge
26
STROBE B
B-ch latch signal input pin
Data input: latched on rising edge
27
CLK A
A-ch clock input pin
Data input: referred to rising edge
28
CLK B
B-ch clock input pin
Data input: referred to rising edge
29
DATA A
A-ch data input pin
Data input:
30
DATA B
B-ch data input pin
Data input:
31
PHASE A
A-ch phase switching pin
PWM signal input pin:
32
PHASE B
B-ch phase switching pin
PWM signal input pin::
33
ENABLE A
A-ch output forced OFF pin
L: output stopped
34
ENABLE B
B-ch output forced OFF pin
L: output stopped
35
SLEEP
Operation stopped mode
Internal logic cleared and charge pump stopped
36 R
S B
B-ch output power supply pin (current
detection pin)
Reference pin for B-axis supply voltage
FIN1
LGND
Logic ground
Logic ground
FIN2
LGND
Logic ground
Logic ground
TB62300FG
2005-04-04
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Pin Description
(Supplementary)
Pull-up/pull-down status and operation within the IC for input pins
Pin
Number
Symbol
Internal Pull-up/down
Output Operation at High
Output Operation at Low
10 NC
Open
Does not affect normal operation of
the IC.
Does not affect normal operation of
the IC.
11
TSTO
Output pin (usually low)
Does not affect normal operation of
the IC (with the same withstand
voltage as for V
DD
).
Does not affect normal operation of
the IC.
12 TSTI
Input pin (no pull-up or
down)
Toshiba test mode
Normal operation mode
13
BRAKE A
No pull-up or down
14
BRAKE B
No pull-up or down
15 NC
Open
Does not affect normal operation of
the IC.
Does not affect normal operation of
the IC.
22 NC
Open
Does not affect normal operation of
the IC.
Does not affect normal operation of
the IC.
23
MODE A
No pull-up or down
24
MODE B
No pull-up or down
25
STROBE A No pull-up or down
26
STROBE B No pull-up or down
27
CLK A
No pull-up or down
28
CLK B
No pull-up or down
29
DATA A
No pull-up or down
30
DATA B
No pull-up or down
31
PHASE A
No pull-up or down
32
PHASE B
No pull-up or down
33
ENABLE A
No pull-up or down
34
ENABLE B
No pull-up or down
35
SLEEP
Pull-down with a 50-k
resistor
TB62300FG
2005-04-04
6
Truth Table (1)
Pin logic overview
Pin
Number
Symbol Function
Logic
23
MODE A
A-ch data mode switching pin
24
MODE B
B-ch data mode switching pin
H : Serial signal input control
L : PWM control
Note: When PWM control is selected, serial data
bits D0 to D6 are valid while D7 to D13 are
invalid.
25
STROBE A
A-ch latch signal input pin
26
STROBE B
B-ch latch signal input pin
H : Latched on rising edge
L : Pass-through
31
PHASE A
A-ch phase switching pin
32
PHASE B
B-ch phase switching pin
H : Positive phase
L : Negative phase
35
SLEEP
Operation stopped mode
H : Sleep released
L : Sleep state
All internal circuits, including charge pumps, are
stopped.
33
ENABLE A
A-ch output forced OFF pin
34
ENABLE B
B-ch output forced OFF pin
H : Output enabled
Output transistors turned on
L : Output disabled
Output transistors turned off
13
BRAKE A
A-ch brake mode pin
14
BRAKE B
B-ch brake mode pin
H : Brake applied
PHASE and ENABLE pins disabled
L : Brake released
Truth Table (2)
Overall logic
External Pins
Serial
Status
SLEEP ENABLE
A/B
BRAKE
A/B
MODE
A/B
PHASE
A/B
PHASE
0 X X X X X
Sleep
mode
0 X X X X
Disable mode
1 X X X
Breake
ON
0 1 X
Forward
0 0 X
Reverse
1 X 1
Forward
1
1
0
1 X 0
Reverse
TB62300FG
2005-04-04
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IC State for Each Function
Function
Internal Logic
Output
Charge Pump
OSC
Recovery Time
SLEEP Reset
OFF
OFF OFF
t
ONG
= 2.0 ms (typ.)/4.0 ms (max)
ENABLE Maintained
OFF Operating Operating
N/A
POR Reset
OFF OFF OFF
t
ONG
= 2.0 ms (typ.)/4.0 ms (max)
ISD Reset
OFF
OFF
OFF
t
ONG
= 2.0 ms (typ.)/4.0 ms (max)
TSD Reset
OFF
OFF
OFF
t
ONG
= 2.0 ms (typ.)/4.0 ms (max)
Serial Input Signals
Data Bit
Name
Function
Initial
Value
Initial State
When PWM is
Operating
0 TBlank
0
0
1 TBlank
1
1
2 TBlank
2
Set blanking time to prevent
false detection due to noise
1
1
fchop 16 7
Enabled
3 Torque
0
0
4 Torque
1
Set current range
0
25% Enabled
5 Decay
mode
0
1
6 Decay
mode
1
Set decay mode
0
Mixed decay mode
(37.5%)
Enabled
7 Current
0
1
8 Current
1
1
9 Current
2
1
10 Current
3
1
11 Current
4
Set current
1
100% Disabled
12 Phase
Switch
phase
0
Negative
Disabled
13
14
15
Notes on TBlank Setting
When using PWM control and serial control simultaneously, constant-current chopping may be disabled
depending on the TBlank setting. Using constant-current chopping requires the following phase width in
Fast Decay mode:
(TBlank setting + 2/fcr) 2
Order of data
input
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2 D1 D0
Strobe
Data
Register
Clock
A15 A14 A13
A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
TB62300FG
2005-04-04
8
Setting Table (1): D0, D1, D2
Blanking time settings
Data Bit
Name
Function
TBlank 2
TBlank 1
TBlank 0
Setting TBlank (typ.)
0 0 0
1
f
Chop
16 1
0 0 1
1
f
Chop
16 2
0 1 0
1
f
Chop
16 3
0 1 1
1
f
Chop
16 4
1 0 0
1
f
Chop
16 5
1 0 1
1
f
Chop
16 6
1 1 0
1
f
Chop
16 7
0
1
2
TBlank 0
TBlank 1
TBlank 2
Set blanking time to prevent
false detection due to noise
1 1 1
1
f
Chop
16 8
Setting Table (2): D3, D4
Torque settings
Data Bit
Name
Function
Torque 1
Torque 0
Setting Torque (typ.)
0 0
25%
0 1
50%
1 0
75%
3
4
Torque 0
Torque 1
Set current range
1 1
100%
Setting Table (3): D5, D6
Decay mode settings
Data Bit
Name
Function
Torque
Mode 1
Torque
Mode 0
Setting Decay Mode
0
0
Slow decay mode
0
1
Mixed decay mode: 37.5%
1
0
Mixed decay mode: 75.0%
5
6
Decay mode 0
Decay mode 1
Set decay mode
1
1
Fast decay mode
TB62300FG
2005-04-04
9
Setting Table (4): D7, D8, D9, D10, D11
Current settings
Data Bit
Name
Function
Current 4
Current 3
Current 2
Current 1
Current 0
Setting Current
0 0 0 0 0
0%
0 0 0 0 1
3%
0 0 0 1 0
6%
0 0 0 1 1
9%
0 0 1 0 0
12%
0 0 1 0 1
16%
0 0 1 1 0
19%
0 0 1 1 1
22%
0 1 0 0 0
25%
0 1 0 0 1
29%
0 1 0 1 0
32%
0 1 0 1 1
35%
0 1 1 0 0
38%
0 1 1 0 1
41%
0 1 1 1 0
45%
0 1 1 1 1
48%
1 0 0 0 0
51%
1 0 0 0 1
54%
1 0 0 1 0
58%
1 0 0 1 1
61%
1 0 1 0 0
64%
1 0 1 0 1
67%
1 0 1 1 0
70%
1 0 1 1 1
74%
1 1 0 0 0
77%
1 1 0 0 1
80%
1 1 0 1 0
83%
1 1 0 1 1
87%
1 1 1 0 0
90%
1 1 1 0 1
93%
1 1 1 1 0
96%
7
8
9
10
11
Current 0
Current 1
Current 2
Current 3
Current 4
Set current
1 1 1 1 1
100%
Setting Table (5): D12
Phase settings
Data Bit
Name
Function Phase Setting
Phase
0 Negative
12 Phase
Switch
phase
1 Positive
TB62300FG
2005-04-04
10
PWM Operation
Notes: f
cr
is 16 times the f
chop
frequency.
PHASE is an external signal.
The internal reset signal resets the internal clocks and counters.
Phase Blank Time is time between either edge of the external PHASE signal and the leading edge of serial blanking time.
Description
The output H bridge is driven by an external PHASE signal.
It, however, also uses the fcr signal, generated with external CR, to generate blanking time and Mixed Decay time. The above logic is configured to handle the two
signals, PHASE and fcr, which are asynchronous to each other. The logic generates internal reset signal edges from external PHASE edges, resulting in the width
equal to two fcr cycles.
The fcr-based counter assumes the first fcr falling edge following the PHASE edge as the first count. The maximum phase difference between the PHASE and fcr
signals is, therefore, one fcr cycle.
The serial blanking time starts at the second count based on the fcr clock (The first three samples of serial blanking time signal must be 000).
The last stage output is switched by the edge of the external PHASE signal. That means there is an interval of two fcr cycles before the set blanking time starts.
To cover the interval, the logic generates the time between the PHASE signal edge and blanking time start as phase blank time, during which comparison is masked
off in the same way as in blanking time.
Consequently, the blanking time as viewed from outside the IC is within the range from one fcr cycle (TBlank (000)) to eight fcr cycles (TBlank (111)) + I phase
difference between PHASE and fcr (up to two fcr cycles).
1 2 3 4 5 6
f
CR
(f
chop
*16)
PHASE
Phase Blank Time
Internal reset signal
Input range for fcr clock
1/fcr*2
Example:
1/fcr*2
Serial Blanking Time
1/fcr*TBlank
Total Blanking Time
Example: 1/fcr*2
+ 1/fcr*TBlank
Output control signal
TB62300FG
2005-04-04
11
Absolute Maximum Ratings
(T
opr
=
25C)
Characteristics Symbol
Test
Condition
Rating
Unit
Logic supply voltage
V
DD
-0.4 to 7.0
V
Maximum output voltage
V
M
40
V
Peak output current
(Note: preliminary specification)
I
OUT (Peak)
t
W
500 ns
8.0
A
Continuous output current
I
OUT (Cont)
2.5
A
Logic input voltage
V
IN
-0.5 to V
DD
V
Current detection pin voltage
V
RS
V
M
4.5 V
V
IC alone
1.4
W
Power dissipation
P
D
When mounted on a board
(Note)
3.2 W
Operating temperature
T
opr
-40 to 85
C
Storage temperature
T
stg
-55 to 150
C
Junction temperature
T
j
150
C
Note: When T
opr
= 45C, T
j
= 150C and ja = 32C
Recommended Operating Conditions
(T
opr
=
0 to 85C)
Characteristics Symbol Test
Condition Min
Typ.
Max
Unit
Supply voltage
(Note 1)
V
DD
4.5 5.0 5.5 V
Output voltage
(Note 1)
V
M
V
DD
= 5.0 V
18.0
24.0
33.0
V
I
OUT (Peak)
V
M
= 33.0 V, t
w
500 ns
6.4 7.2 A
Output current
(Note: preliminary specification)
I
OUT (Cont)
V
M
= 33.0 V
1.5 1.8 A
Logic input voltage range
V
IN
0
V
DD
V
Clock frequency
f
CLK
V
DD
= 5.0 V
1.0
25.0
MHz
Chopping frequency
f
chop
V
DD
= 5.0 V
20
30
150
kHz
V
ref
reference voltage
V
ref
V
M
= 24.0 V, T
ORQUE
= 100%
2.0
3.0
V
DD
V
Current detection pin voltage
V
RS
V
DD
= 5.0 V
0
1.0
1.5
V
Junction temperature
T
j
120
C
Oscillator capacitor
C
OSC
270 pF
Oscillator resistor
R
OSC
3.9
k
Charge pump capacitor A
C
CPA
0.22
F
Charge pump capacitor B
C
CPB
0.022
F
Input rise and fall rate
(Note 2)
tri/tfi
0.1 5.0 s
Note 1: Do not reduce V
DD
to 0 V (ground) while V
M
voltage is applied. Such an attempt may damage the IC
because there is a current path from the V
M
pin to V
DD
pin and the internal logic is undefined when V
DD
is
not applied. Leaving V
DD
open (Hi-Z) is less likely to damage the IC, although it is not recommended.
Note 2: The circuit configuration of this IC cannot handle extremely slow data input (on pins BREAK A, BREAK B,
SLEEP, ENABLE A, ENABLE B, PHASE A, PHASE B, DATA A, DATA B, CLK A, CLK B, STROBE A,
STROBE B, MODE A, and MODE B). Applying a slow signal having a period longer than 5
s may cause
the IC to oscillate.
(1) Calculating the current
I
OUT
= 1/3 V
ref
(V) (Torque (%) R
RS
() ) Current (%)
where 1/3 is the V
ref
(GAIN):V
ref
attenuation ratio.
(2) Calculating the oscillation frequency
f
CR
= 1/(KA) (C R + KB C)) [Hz]
KA = 0.523, KB = 600, f
chop
= f
CR
/16 [Hz]
[Example] When C
OSC
= 270 pF and R
OSC
= 3.9 k: f
CR
= 1.57 MHz and f
chop
= 1.57/16 = 98.4 kHz
TB62300FG
2005-04-04
12
Electrical Characteristics 1
DC Characteristics
(unless otherwise specified, V
M
=
24 V, V
DD
=
5.0 V, T
opr
=
25
)
Characteristics Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
High V
IH
2.0
Input voltage
Low V
IL
DC
CLK, STROBE, DATA, MODE,
PHASE, ENABLE and PHASE
pins
0.8
V
I
IH1
1.0
I
IL1
CLK, STROBE, DATA, MODE,
PHASE, ENABLE and PHASE
pins
1.0
A
I
IH2
200.0
Input current
I
IL2
DC
SLEEP pin
1.0
A
I
DD1
V
DD
= 5.0 V, fcr stopped
3.0 4.5
Current consumed by logic power
supply
I
DD2
DC
In SLEEP mode
0.3 1.0
mA
I
M1
Output open, f
CLK
= 1 kHz,
logic operating, V
DD
= 5 V,
V
M
= 24 V, all output stages
stopped, charge pump charged
4.3 7.0
I
M2
Output open, f
CLK
= 4 kHz,
internal logic operating
(100-kHz chopping), output
stages operating without load,
charge pump charged
20.0 28.0
V
M
current consumption
I
M3
DC
In SLEEP mode
0.5 1.0
mA
Output standby current
Upper
I
OH
V
RS
= V
M
= 24 V, V
out
= 0 V,
ENABLE
= Low,
DATA
= All low
-400
Output bias current
Upper
I
OB
V
RS
= V
M
= 24 V, V
out
= 24 V,
ENABLE
= Low,
DATA
= All low
-200
Output leakage current
Lower
I
OL
DC
V
RS
= V
M
= Ccp A = V
out
= 24 V, SLEEP= Low
1.0
A
High V
RS (H)
V
ref
= 3.0 V, V
ref
(gain)
= 1/3.0
TORQUE
= 11 = 100% set
100
Mid
High
V
RS (MH)
V
ref
= 3.0 V, V
ref
(gain)
= 1/3.0
TORQUE
= 10 = 75% set
73 75 77
Mid
Low
V
RS (ML)
V
ref
= 3.0 V, V
ref
(gain)
= 1/3.0
TORQUE
= 01 = 50% set
48 50 52
Comparator reference
voltage ratio
Low
V
RS (L)
DC
V
ref
= 3.0 V, V
ref
(gain)
= 1/3.0
TORQUE
= 00 = 25% set
23 25 27
%
TB62300FG
2005-04-04
13
Electrical Characteristics 2
DC Characteristics
(
unless otherwise specified,
V
M
=
24 V, V
DD
=
5.0 V, T
opr
=
25
)
Characteristics Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
Output current interchannel error
I
OUT1
DC
Error in output current between
channels (I
OUT
= 1.5 A)
-5.0
5.0
%
Output current setting error
I
OUT2
DC
I
OUT
= 1.5 A
-5.0
5.0 %
RS pin current
I
RS
DC
A
RON1
I
OUT
= 1.5 A, V
DD
= 5.0 V,
T
j
= 25 C, forward direction
0.3 0.4
RON1
I
OUT
= 1.5 A, V
DD
= 5.0 V,
T
j
= 25 C, reverse direction
0.3
0.4
RON2
I
OUT
= 1.5 A, V
DD
= 5.0 V,
T
j
= 105 C, forward direction
0.4 0.55
Output transistor drain-source
ON-resistance
RON2
DC
I
OUT
= 1.5 A, V
DD
= 5.0 V,
T
j
= 105 C, reverse direction
0.4 0.55
V
REF
input voltage
V
ref
DC
V
M
= 24 V, V
DD
= 5.0 V,
ENABLE, output operation
2.0
V
DD
V
V
REF
input current
I
ref
DC
V
ref
= 3.0 V,
V
M
= 24 V, V
DD
= 5.0 V,
SLEEP
100
A
V
REF
attenuation ratio
V
ref
(GAIN)
DC
V
ref
= 3.0 V,
V
M
= 24 V, V
DD
= 5.0 V,
SLEEP
1/2.82 1/3 1/3.18
TSD operating temperature (Note 1)
T
j
TSD DC
V
DD
= 5 V, V
M
= 24 V
130
170
C
Overcurrent protection circuit
operating current
ISD DC
V
DD
= 5 V, V
M
= 24 V
6.0 A
Vpor
(V
DD
)
DC
V
M
= 24 V
3.0
Output OFF mode supply voltage
Vpor
(V
M
)
DC
V
DD
= 5 V
15.0
V
Note 1: Thermal shutdown (TSD) circuit
When the IC junction temperature reaches the specified value and the TSD circuit is activated, the internal
reset circuit turns output off. The TSD activation temperature can be set within the range from 130
C (min)
to 170
C (max). Once the TSD circuit is activated, output is stopped until a pulse (L to H to L) is
subsequently applied to the SLEEP pin. The charge pump is halted while the TSD circuit is active.
The TSD circuit does not include hysteresis. Applying a pulse (L to H to L) to the SLEEP pin deactivates the
circuit.
Note 2: Overcurrent protection circuit (ISD)
This circuit is activated when a current pulse exceeding the specified output value is applied for a period of
1/2f
CHOP
(min) to f
CHOP
(max).
The circuit activates the internal reset circuit to turn output off.
Once it is activated, output is stopped until a pulse (L to H to L) is subsequently applied to the SLEEP pin.
While the ISD circuit is active, the IC is placed in SLEEP mode with the charge pump halted.
TB62300FG
2005-04-04
14
AC Characteristics
(T
opr
=
25C, V
M
=
24 V, V
DD
=
5 V
with load of
6.8 mH/5.7
)
Characteristics Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
Clock frequency
f
CLK
1.0
25.0
MHz
t
w
(t
CLK
)
40.0
t
wp
20.0
Minimum clock pulse width
t
wn
AC
20.0
ns
t
WSTROBE
40.0
t
STROBE (H)
20.0
Minimum STROBE pulse width
t
STROBE (L)
AC
20.0
ns
Minimum SLEEP pulse width
t
WSTROBE
AC
t
ONG
ns
Phase difference between PHASE
signal and fcr
tp AC
1/f
CR
ns
Blanking time for preventing false
detection
t
BLNIK
(Note
1)
300 ns
t
sSIN-CLK
20.0
Data setup time
t
sST-CLK
AC
20.0
ns
t
hSIN-CLK
20.0
Data hold time
t
hST-CLK
AC
20.0
ns
STROBE setup time (relative to CLK)
t
sSSB-CLK
AC
20.0
STROBE hold time (relative to CLK)
t
hSB-CLK
AC
20.0
ns
40.0 100
40.0 100
100 200
580 1000
100 200
350 700
1000 2000
Output transistor switching time
t
f
t
f
t
pLH
t
pHL
t
pLZ
t
pHZ
t
pZL
t
pZH
AC
350 700
ns
CR reference signal oscillation
frequency
f
CR
C
osc
= 270 pF, R
osc
= 3.9 k
1.1 1.3 1.5 MHz
Chopping frequency
f
chop (min)
f
chop (typ.)
f
chop (max)
20.0
150.0
kHz
Oscillation frequency
f
chop
When f
CR
= 480 kHz
30.0 kHz
Charge pump rise time
t
ONG
AC
2.0 4.0 ms
Note 1: The blanking time is internally fixed but it can be elongated by applying a serial blanking time signal.
TB62300FG
2005-04-04
15
Test Circuit
(DC)
R
osc
= 3.6 k
C
osc
= 560 pF
V
ref
A
V
M
R
RS A
A
B
A
B
R
RS B
ENABLE A
PHASE B
PHASE A
ENABLE B
MODE A
MODE B
LGND
(F
IN
)
CLK B
STROBE B
DATA A
CLK A
STROBE A
CR
V
DD
0.22
V
RS
I
OUT1, 2
Ccp 3
Ccp 2
Ccp 1
Ccp 2
0.022
F
Ccp 1
0.22
F
24 V
SGND
100
F
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
LGND
A
DC Motor
I
OL
I
OH
I
OB
LGND
DATA B
SLEEP
BRAKE A
BRAKE B
V
ref
B
P-GND
PGND
A
I
DD1
I
DD2
A
5 V
0 V
A
5 V
0 V
A
5 V
0 V
A
5 V
0 V
A
5 V
0 V
A
5 V
0 V
A
5 V
LGND
A
A
A
A
A
A
5 V
5 V
0 V
A
A
0 V
V
3 V
1
F
LGND
A
I
ref
V
ref
LGND
A
I
ref
I
M1
, I
M2
, I
M3
V
A
R
RS A
M
DC Motor
M
0.22
R
RS B
A
I
RS
3 V
1
F
V
ref
TB62300FG
2005-04-04
16
Test Circuit
(AC)
R
osc
= 3.6 k
C
osc
= 560 pF
V
ref
A
V
M
R
RS A
A
B
A
B
R
RS B
ENABLE A
PHASE B
PHASE A
ENABLE B
MODE A
MODE B
V
SS
(F
IN
)
CLK B
STROBE B
DATA A
CLK A
STROBE A
CR
V
DD
1.0
V
RS
I
OUT1, 2
Ccp 3
Ccp 2
Ccp 1
Ccp 2
0.022
F
24 V
PGND
100
F
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
LGND
DC Motor
I
OL
I
OH
I
OB
DATA B
SLEEP
BRAKE A
BRAKE B
V
ref
B
P-GND
PGND
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
5 V
SGND
A
A
A
A
A
A
5 V
5 V
0 V
A
A
0 V
t
ONG
Ccp 1
0.22
F
V
3 V
1
F
LGND
A
I
ref
V
ref
LGND
t
BLNIK
V
A
R
RS A
M
DC Motor
M
1.0
R
RS B
A
I
RS
f
CLK
, t
w
(t
CLK
), t
wp
, t
wn
,
t
wSTROBE
, t
STROBE (H)
, t
STROBE (L)
,
t
sSIN-CLK
, t
sST-CLK
, t
hSIN-CLK
, t
hST-CLK
f
chop
,
fosc
3 V
1
F
V
ref
TB62300FG
2005-04-04
17
AC Test Waveforms
CLOCK
DATA
DATA 15 50%
DATA 0
DATA 1
t
sDATA
t
hDATA
t
wn
t
wn
t
sSTROBE
t
dCLOOK
t
wSTROBE
50%
t
wSLEEP
STROBE
SLEEP
50%
t
w
(
t
CLK)
50%
PHASE
Out A
t
pLH
50%
t
pHL
PHASE
ENABLE
Out A
50%
t
pZH
t
pHZ
t
pZL
t
pLZ
TB62300FG
2005-04-04
18
Waveform in Mixed Decay Mode
(Current Waveform)
Output Transistor Operating Mode
Output Transistor Operation Functions
CLK U1 U2 L1 L2
Charge
ON OFF OFF ON
Slow OFF OFF ON ON
Fast OFF ON ON OFF
Note: The above table is an example where current flows in the direction of the arrows in the above figures.
When the current flows in the opposite direction of the arrows, see the table below.
CLK U1 U2 L1 L2
Charge OFF ON
ON OFF
Slow OFF OFF ON ON
Fast ON OFF OFF ON
NF
NF
25%
Mixed
Decay
Mode
Internal
CR CLK
signal
I
OUT
f
chop
f
chop
Set current
value
Set current value
RNF
MDT (Mixed Decay Timming) point
U1
L1
U2
L2
PGND
OFF
OFF
U1
L1
U2
L2
OFF
ON
ON
(Note)
Load
PGND
U1
L1
U2
L2
(Note)
Load
PGND
(Note)
R
S
pin
R
RS
V
M
ON
ON
Load
Charge mode
Slow mode
Fast mode
ON
R
S
pin
R
S
pin
OFF
OFF
ON
OFF
V
M
V
M
R
RS
R
RS
TB62300FG
2005-04-04
19
Power Supply Sequence
(Recommended)
Note 1: If V
DD
drops to the level of the V
DDR
or below while the specified voltage is applied to the V
M
pin, the IC is
internally reset.
This is a protective measure against malfunction. Likewise, if V
M
drops to the level of V
MR
or below while
regulation voltage is applied to V
DD
, the IC is internally reset as a protective measure against malfunction.
To avoid malfunction, when turning on V
M
or V
DD
, applying a signal to the SLEEP pin at the above timing is
recommended.
It takes time for the output control charge pump circuit to stabilize. Wait up to t
ONG
time after power on
before driving a motor.
Note 2: When the V
M
value is between 3.3 to 5.5 V, the internal reset is released, thus output may be active. In
such a case, the charge pump circuit cannot operate properly because of insufficient voltage. The IC should
be held in SLEEP mode until V
M
reaches 13 V or more.
Note 3: Since V
DD
= 0 V and V
M
= voltage within the rating are applied, output is turned off by internal reset.
At that time, a current of several mA flows due to a current path between V
M
and V
DD
.
When the output voltage is high, make sure that the specified voltage is applied to V
DD
.
V
DD (max)
V
DD (min)
V
DDR
GND
V
DD
V
M
V
M (min)
V
MR
GND
V
M
Non-reset
Reset
Internal reset
H
L
SLEEP input
(Note1)
Takes up to t
ONG
until operable
Non-operable area
TB62300FG
2005-04-04
20
P
D
Ta
(Package power dissipation)
Transient thermal resistance
(1) HSOP36 R
th (j-a)
without a board (96C/W)
(2) When mounted on a board (140 mm 70 mm 1.6 mm: 38C/W: typ.)
Note: R
th (j-a)
: 8.5C/W
Ambient temperature Ta (C)
P
D
Ta
Power
di
ssip
ation
P
D
(W)
(2)
(1)
0
0
3.5
25 50 75 100 125
150
0.5
1
1.5
2
2.5
3
TB62300FG
2005-04-04
21
Relationship between V
M
and V
H
(charge pump voltage)
Note: V
DD
= 5 V
Ccp 1
= 0.22 F, Ccp 2 = 0.022 F, f
chop
= 150 kHz
(Care must be taken about the temperature charges of charge pump capacitor.)
V
M
V
H
(& Vcharge UP)
V
H
vol
t
age
, charg
e
up volt
age
(V)
Supply voltage V
M
(V)
Charge pump voltage V
H
= V
DD
+ V
M
(
= Ccp A) (V)
(Maximum rating is V
DD
(7 V)
+ V
M
(40 V))
10
20
0
0
VH voltage
Charge up voltage
VM voltage
2 3
10
20
30
40
4 5 6 7 8 9
11 12 13 14 15 16 17 18
21 22 23 24 25 26
19
27 28 29
31 32 33 34 35 36 37 38 39
1
30
40
50
Apply SLEEP signal.
VMR
VM voltage
Maximum rating
Charge pump
output voltage
Recommended operation area
Usable area
TB62300FG
2005-04-04
22
Operation of Charge Pump Circuit
Initial charging
(1) When RESET is released, T
r1
is turned on and T
r2
turned off. Ccp 2 is charged from V
M
via Di1.
(2) After T
r1
is turned off and T
r2
is turned on, and Ccp 1 is charged from Ccp 2 via Di2.
(3) When the voltage difference between V
M
and V
H
(Ccp A pin voltage = charge pump voltage)
reaches V
DD
or higher, operation halts (in the steady-state phase).
Actual operation
(4) The charge of Ccp 1 charge is used at f
chop
switching and the potential of V
H
drops.
(5) The circuit is charged up by the operations of (1) and (2) above.
Output switching
Initial charging
Steady-state phase
(1)
(2) (3)
(4)
t
(5)
(4)
(5)
V
H
V
M
V
H
= V
M
+ V
DD
= charge pump voltage
i1
= charge pump current
i2
= gate block power dissipation
V
DD
= 5 V
V
M
= 24 V
Comparator
and
Controller
V
M
Output
Output
H switch
i2
Ccp 1
0.22
F
Ccp A
Ccp B
Ccp C
R
1
V
H
R
S
R
RS
Ccp 2
0.022
F
Di2
Di1
Di3
V
z
i1
(2)
T
r1
T
r2
7
(1)
(2)
TB62300FG
2005-04-04
23
Charge Pump Rise Time
t
ONG
: Time taken for capacitor Ccp 2 (charging capacitor) to fill up Ccp 1 (storing capacitor) to V
M
+ V
DD
after a reset is released.
The internal circuits cannot drive the gates correctly until the voltage of Ccp 1 reaches V
M
+ V
DD
.
Be sure to wait for t
ONG
or longer before driving the motors.
Basically, the larger the Ccp 1 capacitance is, the smaller the voltage fluctuation is, though the
initial charge up time is longer.
The smaller the Ccp 1 capacitance is, the shorter the initial charge-up time is, but the voltage
fluctuation is larger.
Depending on the combination of capacitors (especially with small capacitance), voltage may not be
sufficiently boosted. When the voltage does not increase sufficiently, R
ON
of output DMOS becomes
lower than the reference value, which raises the temperature.
Thus, use the capacitors under the capacitor combination conditions (Ccp 1 = 0.22 F, Ccp 2 = 0.022
F) recommended by Toshiba.
50%
V
DD
+ V
M
V
M
+ (V
DD
90%)
Ccp 1 voltage
V
M
5 V
0 V
STANDBY
t
ONG
TB62300FG
2005-04-04
24
External Capacitor for Charge Pump
When driving a motor while V
DD
= 5 V, f
chop
= 150 kHz, L = 10 mH under the conditions of V
M
= 27 V and
2.0 A, the logical values for Ccp 1 and Ccp 2 are as shown in the graph below:
Choose Ccp 1 and Ccp 2 to be combined from the above applicable range. We recommend Ccp 1:Ccp 2 at
10:1 or more. (If our recommended values (Ccp = 0.22 F, Ccp 2 = 0.022 F) are used, the drive conditions in
the specification sheet are satisfied. (There is no capacitor temperature characteristic as a condition.)
When setting the constants, make sure that the charge pump voltage is not below the specified value and
set the constants with a margin (the larger Ccp 1 and Ccp 2, the more the margin).
Some capacitors exhibit a large change in capacitance according to the temperature. Make sure the above
capacitance is obtained under the IC ambient temperature.
0.05
0
0
Recommended
value
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
0.045
0.05 0.1 0.15 0.2 0.25
0.35 0.4 0.45 0.5
0.3
Applicable range
Ccp 1 capacitance (
F)
Ccp 1 Ccp 2
Ccp 2
cap
a
ci
t
ance
(
F)
TB62300FG
2005-04-04
25
Recommended Application Circuit
The values of external constants are example recommended values. For values under different input
conditions, see the above-mentioned recommended operating conditions.
(The following shows an example when fcho = 501 Hz (CR frequency = 800 kHz and constant-current
limiter = 2.27 A) with serial signals placed in initial status.)
Note: It is recommended to add bypass capacitors as required.
Make sure that all gound pins are connected to the same ground rail.
STROBE, CLK, and DATA must be tied to LGND if serial input is not used for settings or motor control.
Because there may be short circuits between outputs, to supply, or to ground, be careful when designing
output lines, V
DD
(V
M
) lines, and ground lines.
R
osc
= 3.6 k
C
osc
= 560 pF
V
ref
A
V
M
R
RS A
A
B
A
B
R
RS B
ENABLE A
PHASE B
PHASE A
ENABLE B
MODE A
MODE B
LGND
(F
IN
)
CLK B
STROBE B
DATA A
CLK A
STROBE A
CR
V
DD
0.11
Ccp 3
Ccp 2
Ccp 1
Ccp 2
0.022
F
24 V
LGND
100
F
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
LGND
DC Motor
DATA B
SLEEP
BRAKE A
BRAKE B
V
ref
B
P-GND
PGND
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
10
F
SGND
5 V
5 V
0 V
0 V
LGND
Ccp 1
0.22
F
3 V
1
F
LGND
V
ref
R
RS A
M DC Motor
M
0.11
R
RS B
5 V
TB62300FG
2005-04-04
26
Connection Diagram
(when external forced PWM mode is used)
3 V
0.5
R
S B
ENABLE B
ENABLE A
PHASE B
PHASE A
DATA B
DATA A
CLK B
CLK A
STROBE B
STROBE A
MODE B
MODE A
NC
OUT B
-
OUT B
+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
LGND
R
S A
V
REF A
V
REF B
CR
Ccp 1
Ccp 2
Ccp 3
LGND
TEST A
TEST B
TEST C
BRAKE A
NC
OUT A
-
PGND
OUT A
+
V
DD
BRAKE B
V
M
SLEEP
PGND
M
M
0.5
3 V
10
F
10
F
3.9 k
270 pF
0.022
F
0.22
F
5 V
NC
NC
: Signal from central unit
24 V
100
F
10
F
5 V
TB62300FG
2005-04-04
27
Package Dimensions
HSOP36-P-450-0.65
Unit: mm
Weight: 0.79 g (typ.)
TB62300FG
2005-04-04
28
The information contained herein is subject to change without notice.
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
TOSHIBA or others.
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability
Handbook" etc..
The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer's own risk.
The products described in this document are subject to the foreign exchange and foreign trade laws.
TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced
and sold, under any law an
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