TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC220/223 SLI ASIC 0.3m
Standard Cell, Embedded
Arrays, Gate Arrays
Description
The 0.3m drawn TC220/223 ASIC technology
provides the optimum density and performance
needed for System-Level Integration (SLI) IC designs.
Product Features
2.1M usable gates
90ps loaded NAND gate delay for high-performance
systems
Extensive core and cell libraries for SLI
implementation
3 ranges of macrocells for speed/power optimization
Technology libraries compatible with TC200 series
ASIC family for ease of migration
TOSHIBA
Accurate delay modeling ensures system
predictability
Commercial EDA sign-off for flexibility
True mixed 3.3/5V I/O operation with TC223
A wide range of packaging options available,
including BGA, TAB-BGA, heatspreader plastic,
QFP, TAB-QFP, and others to suit all applications
Applications
The TC220 has been targeted at low-power and SLI
ASIC designs. Typical applications include LAN,
access, set-top boxes, printers, mass storage, and
graphics chipsets. The TC223 enables designers to
incorporate a 3V core and a true 5V I/O interface.
TC220C Standard Cell Product Summary
Usable Gates
Maximum I/O Pads
Part Number
DLM
TLM
Wirebond Pads
TCP-TBGA
PQFP{TAB} TBGA
TC220C040/540
59,000
98,000
104
148
200
TC220C060/560
83,000
137,000
128
184
248
TC220C080/580
113,000
186,000
144
212
288
TC220C100/600
137,000
225,000
160
236
316
TC220C120/620
167,000
273,000
176
260
348
TC220C140/640
200,000
327,000
192
284
380
TC220C160/660
224,000
360,000
208
312
420
TC220C180/680
260,000
418,000
224
336
452
TC220C200/700
299,000
481,000
240
360
484
TC220C220/720
341,000
547,000
256
384
516
TC220C240/740
385,000
618,000
272
408
548
TC220C260/760
432,000
694,000
288
432
TC220C280/780
481,000
773,000
304
456
TC220C300/800
534,000
857,000
320
480
TC220C320/820
589,000
945,000
336
504
TC220C340/840
635,000
1,024,000
360
540
TC220C360/860
723,000
1,166,000
384
576
TC220C380/880
817,000
1,317,000
408
612
TC220C400/900
916,000
1,477,000
432
648
TC220C420/920
1,288,000
2,100,000
512
768
NOTE: DLM = Double-Layer Metal, TLM = Triple-Layer Metal
TOSHIBA
NORTHWEST
San Jose, CA
TEL: (408) 526-2400
FAX: (408) 526-2410
Portland, OR
TEL: (503) 629-0818
FAX: (503) 629-0827
SOUTHWEST
Irvine, CA
TEL: (949) 453-0224
FAX: (949) 453-0125
Dallas, TX
TEL: (972) 480-0470
FAX: (972) 235-4114
CENTRAL
Chicago, IL
TEL: (847) 945-1500
FAX: (847) 945-1044
NORTHEAST
Boston, MA
TEL: (781) 224-0074
FAX: (781) 224-1096
Edison, NJ
TEL: (732) 248-8070
FAX: (732) 248-8030
SOUTHEAST
Atlanta, GA
TEL: (770) 931-3363
FAX: (770) 931-7602
TAEC Regional Sales Offices
System-Level IC Cores and Cells
Toshiba's SLI ASIC TC220/223 family is supported by
cores and cells such as Analog PLL, 10/100 Ethernet,
ATM, RISC, PCI, USB, 1394, LVDS, etc. In addition,
Toshiba has established partnerships with IP providers
so the broadest offering of IP can be accessed for a
design.
Optimized Macrocell Performance
The TC220 family has three ranges of macrocells for
speed/power optimization.
Cell Type*
Normal
High-Speed
Ultra-Speed
Delay 225ps
140ps
90ps
Power
1.42W/MHz 1.86W/MHz
2.73W/MHz
* 2-input NAND, fanout = 2 plus typical interconnect load, nominal operating
conditions
High-Performance I/O
The TC220/223 is supported by a range of high-perfor-
mance I/O options, including PCI, high-performance
GTL, 3V failsafe, and low undershoot buffers.
Accurate Models
The TC220/223 incorporates Toshiba's accurate delay
model which includes effect of via resistance and
interwire capacitance, as well as the following features:
Pin-to-pin timing
State-dependent delay
Table Look-up delay
Input slew
Non-linear equation
Commercial EDA Tool Sign-off
The TC220/223 is supported by Toshiba's open EDA
strategy based on sign-off on multiple commercial EDA
tools. Support includes Static Timing Sign-off (STSO)
and Toshiba's Timing-Driven Flow (TDF
TM
) that can
reduce SLI design iterations an order of magnitude and
achieve timing convergence.
Toshiba has a range of Design for Test (DFT) support,
including SCAN, Partial SCAN, BIST, and Boundary
SCAN.
Technology Resource Centers
Toshiba SLI ASIC Technology Resource Centers are
located throughout the U.S. to provide technical support
before, during, and after the design of a Toshiba ASIC.
This includes support dealing with EDA environments
and design kits, Toshiba design methodologies, ASIC
technologies, and design implementation.
In addition, Toshiba's North America Semiconductor
Engineering Development Center based in San Jose, CA
is staffed with system, technology, and EDA design
experts who work with customers on advanced System
IC applications.
High-Quality, High-Volume Manufacturing
Toshiba's ASIC manufacturing plants are among the
largest and most advanced in the world. They are all
certified to ISO9000. Rigorous quality control coupled
with a sophisticated batch tracking system allows
Toshiba to meet the needs of fast-ramping, high-volume
markets.
The technical data may be controlled under U.S. Export Administration Regulations and may be subject to the approval of the U.S. Department of Commerce prior to export. Any export or re-
export directly or indirectly, in contravention of the U.S. Export Administration regulations, is strictly prohibited.
TDF is a trademark of Toshiba Corporation.
All others are owned by their respective manufacturer and may be registered in certain jurisdictions.
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