TC55NEM216AFTN55,70
2002-07-04 1/11
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55NEM216AFTN is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by
16 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 5V
10% power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3
mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 1 A standby
current (typ) when chip enable ( CE ) is asserted high. There are two control inputs. CE is used to select the device
and for data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB ,
UB ) provides lower and upper byte access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. And, with a guaranteed operating extreme
temperature range of -40 to 85C, the TC55NEM216AFTN can be used in environments exhibiting extreme
temperature conditions. The TC55NEM216AFTN is available in a plastic 54-pin thin-small-outline package
(TSOP).
FEATURES
Low-power dissipation
Operating: 15 mW/MHz (typical)
Single power supply voltage of 5 V 10%
Power down features using CE
Data retention supply voltage of 2.0 to 5.5 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of -40 to 85C
Standby Current (maximum): 20 A
PIN ASSIGNMENT
(TOP VIEW)
54 PIN TSOP
PIN NAMES
A0~A17 Address
Inputs
CE
Chip
Enable
R/W
Read/Write Control
OE
Output
Enable
LB ,
UB
Data Byte Control
I/O1~I/O16 Data
Inputs/Outputs
V
DD
Power
(
+5 V)
GND Ground
NC No
Connection
OP* Option
*: OP pin must be open or connected to GND.
Access Times (maximum):
TC55NEM216AFTN
55 70
Access Time
55 ns
70 ns
CE
Access Time
55 ns
70 ns
OE
Access Time
30 ns
35 ns
Package:
TSOP II54-P-400-0.80
(Weight: g typ)
NC
A3
A2
A1
A0
I/O16
I/O15
V
DD
GND
I/O14
I/O13
OP
R/W
I/O12
I/O11
GND
V
DD
I/O10
I/O9
NC
A17
A16
A15
A14
A13
A4
A5
A6
A7
NC
I/O1
I/O2
V
DD
GND
I/O3
I/O4
OP
NC
I/O5
I/O6
GND
V
DD
I/O7
I/O8
A8
A9
A10
A11
A12
NC
1 54
2 53
3 52
4 51
5 50
6 49
7 48
8 47
9 46
10 45
11 44
12 43
13 42
14 41
15 40
16 39
17 38
18 37
19 36
20 35
21 34
22 33
23 32
24 31
25 30
26 29
27 28
CE
OE
UB
LB
TC55NEM216AFTN55,70
2002-07-04 3/11
OPERATING MODE
MODE
CE
OE
R/W LB
UB
I/O1~I/O8
I/O9~I/O16
POWER
L L H L L
Output
Output
I
DDO
L L H H L
High-Z
Output
I
DDO
Read
L L H L H
Output
High-Z
I
DDO
L
* L L L
Input
Input
I
DDO
L
* L H L
High-Z
Input
I
DDO
Write
L
* L L H
Input
High-Z
I
DDO
L H H L L
High-Z High-Z
I
DDO
L H H H L
High-Z High-Z
I
DDO
Output Deselect
L H H L H
High-Z High-Z
I
DDO
H
*
*
*
*
High-Z High-Z
I
DDS
Standby
*
*
* H H
High-Z High-Z
I
DDS
* = don't care
H = logic high
L = logic low
MAXIMUM RATINGS
SYMBOL RATING
VALUE
UNIT
V
DD
Power Supply Voltage
-0.3~7.0 V
V
IN
Input Voltage
-0.3*~7.0 V
V
I/O
Input/Output Voltage
-0.5~V
DD
+ 0.5
V
P
D
Power Dissipation
0.6
W
T
solder
Soldering Temperature (10s)
260
C
T
stg
Storage Temperature
-55~150 C
T
opr
Operating Temperature
-40~85 C
*:
-2.0 V when measured at a pulse width of 20ns
DC RECOMMENDED OPERATING CONDITIONS (
Ta
=
=
=
= ----40 to 85C
)
SYMBOL PARAMETER MIN
TYP
MAX
UNIT
V
DD
Power Supply Voltage
4.5
5.0
5.5
V
V
IH
Input High Voltage
2.2
V
DD
+ 0.3
V
V
IL
Input Low Voltage
-0.3*
0.6 V
V
DH
Data Retention Supply Voltage
2.0
5.5 V
*:
-2.0 V when measured at a pulse width of 20ns
TC55NEM216AFTN55,70
2002-07-04 5/11
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta
=
=
=
= ----40 to 85C, V
DD
=
=
=
= 5 V 10%)
READ CYCLE
TC55NEM216AFTN
55 70
SYMBOL PARAMETER
MIN MAX MIN MAX
UNIT
t
RC
Read
Cycle
Time
55
70
t
ACC
Address
Access
Time
55
70
t
CO
Chip Enable Access Time
55 70
t
OE
Output Enable Access Time
30 35
t
BA
Data Byte Control Access Time
55 70
t
COE
Chip Enable Low to Output Active
5
5
t
OEE
Output Enable Low to Output Active
0
0
t
BE
Data Byte Control Low to Output Active
5
5
t
OD
Chip Enable High to Output High-Z
25 30
t
ODO
Output Enable High to Output High-Z
25 30
t
BD
Data Byte Control High to Output High-Z
25 30
t
OH
Output Data Hold Time
10
10
ns
WRITE CYCLE
TC55NEM216AFTN
55 70
SYMBOL PARAMETER
MIN MAX MIN MAX
UNIT
t
WC
Write
Cycle
Time
55
70
t
WP
Write
Pulse
Width
40
50
t
CW
Chip Enable to End of Write
45
55
t
BW
Data Byte Control to End of Write
45
55
t
AS
Address
Setup
Time
0
0
t
WR
Write Recovery Time
0
0
t
ODW
R/W Low to Output High-Z
25 30
t
OEW
R/W High to Output Active
0
0
t
DS
Data
Setup
Time
25
30
t
DH
Data
Hold
Time
0
0
ns
Note: t
OD
, t
ODO
, t
BD
and t
ODW
are specified in time when an output becomes high impedance, and are not judged depending on
an output voltage level.
AC TEST CONDITIONS
PARAMETER TEST
CONDITION
Input pulse level
0.4 V, 2.4 V
t
R
, t
F
5 ns
Timing measurements
1.5 V
Reference level
1.5 V
Output load
100 pF
+ 1 TTL Gate
PDF 
ZIP
