TC55VBM316AFTN/ASTN40,55
2002-08-05 1/15
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 16-BIT/1,048,576-WORD BY 8-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55VBM316AFTN/ASTN is a 8,388,608-bit static random access memory (SRAM) organized as 524,288
words by 16 bits/1,048,576 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this
device operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provides both high speed and
low power at an operating current of 3 mA/MHz and a minimum cycle time of 40 ns. It is automatically placed in
low-power mode at 0.7 A standby current (at V
DD
= 3 V, Ta = 25C, typical) when chip enable ( CE1 ) is asserted
high or (CE2) is asserted low. There are three control inputs. CE1 and CE2 are used to select the device and for
data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB , UB )
provides lower and upper byte access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. And, with a guaranteed operating extreme
temperature range of -40 to 85C, the TC55VBM316AFTN/ASTN can be used in environments exhibiting extreme
temperature conditions. The TC55VBM316AFTN/ASTN is available in a plastic 48-pin thin-small-outline package
(TSOP).
FEATURES
Low-power dissipation
Operating: 9 mW/MHz (typical)
Single power supply voltage of 2.3 to 3.6 V
Power down features using CE1 and CE2
Data retention supply voltage of 1.5 to 3.6 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of -40 to 85C
Standby Current (maximum):
3.6 V
10
A
3.0 V
5
A
PIN ASSIGNMENT
(TOP VIEW)
PIN
NAMES
48 PIN TSOP
A0~A18
Address Inputs (Word Mode)
A-1~A18
Address Inputs (Byte Mode)
1
CE
, CE2
Chip Enable
R/W Read/Write
Control
OE
Output
Enable
LB ,
UB
Data Byte Control
I/O1~I/O16 Data
Inputs/Outputs
BYTE
Byte
(
8 mode) Enable
V
DD
Power
GND Ground
NC No
Connection
OP* Option
*: OP pin must be open or connected to GND.
Pin
No. 1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
16
Pin
Name A15 A14 A13 A12 A11 A10 A9 A8 NC NC R/W CE2 OP
UB
LB A18
Pin
No.
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Pin
Name A17 A7 A6 A5 A4 A3 A2 A1 A0
1
CE
GND
OE
I/O1 I/O9 I/O2 I/O10
Pin
No.
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Pin
Name
I/O3 I/O11 I/O4 I/O12 V
DD
I/O5 I/O13 I/O6 I/O14 I/O7 I/O15 I/O8 I/O16
/A-1
GND
BYTE
A16
Access Times (maximum):
TC55VBM316AFTN/ASTN
40 55
Access Time
40 ns
55 ns
1
CE
Access Time
40 ns
55 ns
CE2 Access Time
40 ns
55 ns
OE
Access Time
25 ns
30 ns
Package:
TSOP48-P-1220-0.50 (AFTN) (Weight:0.51 g typ)
TSOP48-P-1214-0.50 (ASTN) (Weight:0.36 g typ)
(Normal)
25
48
24
1
TC55VBM316AFTN/ASTN40,55
2002-08-05 3/15
OPERATING MODE
MODE
1
CE
CE2
OE
R/W BYTE LB
UB
I/O1~I/O8
I/O9~I/O15
I/O16
POWER
L H L H L *
* Output
High-Z
A-1
I
DDO
L H L H H L L
Output
Output
Output
I
DDO
L H L H H H L
High-Z
Output
Output
I
DDO
Read
L H L H H L H
Output
High-Z
High-Z
I
DDO
L H * L L *
* Input
High-Z
A-1
I
DDO
L H * L H L L
Input
Input
Input
I
DDO
L H * L H H L
High-Z
Input
Input
I
DDO
Write
L H *
L H L
H
Input
High-Z
High-Z
I
DDO
L H H H L *
* High-Z
High-Z
A-1
I
DDO
L H H H H L L
High-Z
High-Z
High-Z
I
DDO
L H H
H H H L
High-Z
High-Z
High-Z
I
DDO
Output Deselect
L H H H H L H
High-Z
High-Z
High-Z
I
DDO
H
*
*
*
H or L
*
* High-Z
High-Z
High-Z
I
DDS
* L *
*
H or L
*
* High-Z
High-Z
High-Z
I
DDS
Standby
*
*
*
* H H
H
High-Z
High-Z
High-Z
I
DDS
* = don't care
H = logic high
L = logic low
MAXIMUM RATINGS
SYMBOL RATING
VALUE
UNIT
V
DD
Power Supply Voltage
-0.3~4.2 V
V
IN
Input Voltage
-0.3*~4.2 V
V
I/O
Input/Output Voltage
-0.5~V
DD
+ 0.5
V
P
D
Power Dissipation
0.6
W
T
solder
Soldering Temperature (10s)
260
C
T
stg
Storage Temperature
-55~150 C
T
opr
Operating Temperature
-40~85 C
*:
-2.0 V when measured at a pulse width of 20ns
DC RECOMMENDED OPERATING CONDITIONS (
Ta
=
=
=
= ----40 to 85C
)
SYMBOL PARAMETER MIN
TYP
MAX
UNIT
V
DD
Power Supply Voltage
2.3
3.6 V
V
DD
= 2.3 V~2.7 V
2.0
V
IH
Input High Voltage
V
DD
= 2.7 V~3.6 V
2.2
V
DD
+ 0.3
V
V
IL
Input Low Voltage
-0.3*
V
DD
0.24
V
V
DH
Data Retention Supply Voltage
1.5
3.6 V
*:
-2.0 V when measured at a pulse width of 20ns
TC55VBM316AFTN/ASTN40,55
2002-08-05 5/15
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta
=
=
=
= ----40 to 85C, V
DD
=
=
=
= 2.7 to 3.6 V)
READ CYCLE
TC55VBM316AFTN/ASTN
40 55
SYMBOL PARAMETER
MIN MAX MIN MAX
UNIT
t
RC
Read
Cycle
Time
40
55
t
ACC
Address
Access
Time
40
55
t
CO1
Chip
Enable(
1
CE
) Access Time
40 55
t
CO2
Chip Enable(CE2) Access Time
40 55
t
OE
Output Enable Access Time
25 30
t
BA
Data Byte Control Access Time
40 55
t
COE
Chip Enable Low to Output Active
5
5
t
OEE
Output Enable Low to Output Active
0
0
t
BE
Data Byte Control Low to Output Active
5
5
t
OD
Chip Enable High to Output High-Z
20 25
t
ODO
Output Enable High to Output High-Z
20 25
t
BD
Data Byte Control High to Output High-Z
20 25
t
OH
Output Data Hold Time
10
10
ns
WRITE CYCLE
TC55VBM316AFTN/ASTN
40 55
SYMBOL PARAMETER
MIN MAX MIN MAX
UNIT
t
WC
Write
Cycle
Time
40
55
t
WP
Write
Pulse
Width
30
40
t
CW
Chip Enable to End of Write
35
45
t
BW
Data Byte Control to End of Write
35
45
t
AS
Address
Setup
Time
0
0
t
WR
Write Recovery Time
0
0
t
ODW
R/W Low to Output High-Z
20 25
t
OEW
R/W High to Output Active
0
0
t
DS
Data
Setup
Time
20
25
t
DH
Data
Hold
Time
0
0
ns
Note: t
OD
, t
ODO
, t
BD
and t
ODW
are specified in time when an output becomes high impedance, and are not judged depending on
an output voltage level.
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