TC55VCM208ASTN40,55
2002-07-04 1/12
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55VCM208ASTN is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by
8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to
3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of
3 mA/MHz and a minimum cycle time of 40 ns. It is automatically placed in low-power mode at 0.7
A standby
current (at V
DD
=
3 V, Ta
=
25C, typical) when chip enable ( CE1 ) is asserted high or (CE2) is asserted low. There
are three control inputs. CE1 and CE2 are used to select the device and for data retention control, and output
enable ( OE ) provides fast memory access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. And, with a guaranteed operating extreme
temperature range of
-
40 to 85C, the TC55VCM208ASTN can be used in environments exhibiting extreme
temperature conditions. The TC55VCM208ASTN is available in a plastic 40-pin thin-small outline package
(TSOP).
FEATURES
Low-power dissipation
Operating: 9 mW/MHz (typical)
Single power supply voltage of 2.3 to 3.6 V
Power down features using CE1 and CE2
Data retention supply voltage of 1.5 to 3.6 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of
-
40 to 85C
Standby Current (maximum):
3.6 V
10
A
3.0 V
5
A
PIN ASSIGNMENT
(TOP VIEW)
PIN
NAMES
40 PIN TSOP
A0~A18 Address
Inputs
1
CE , CE2
Chip Enable
R/W Read/Write
Control
OE Output
Enable
LB ,
UB
Data Byte Control
I/O1~I/O16 Data
Inputs/Outputs
V
DD
Power
GND Ground
NC No
Connection
OP* Option
*
: OP pin must be open or connected to GND.
Pin
No. 1 2 3 4 5 6 7 8 9 10
11 12
13
14 15 16 17 18 19
20
Pin
Name A16 A15 A14 A13
A12 A11 A9 A8 R/W CE2 OP
NC A18
A7
A6
A5 A4
A3
A2
A1
Pin
No. 21 22 23 24 25 26 27 28
29
30
31
32
33
34 35 36 37 38 39
40
Pin Name
A0
CE1
GND OE
I/O1 I/O2
I/O3
I/O4
NC V
DD
V
DD
I/O5 I/O6 I/O7 I/O8 A10 NC NC
GND A17
Access Times:
TC55VCM208ASTN
40 55
Access Time
40 ns
55 ns
1
CE Access Time
40 ns
55 ns
CE2 Access Time
40 ns
55 ns
OE Access Time
25 ns
30 ns
Package:
TSOP40-P-1014-0.50
(Weight:0.30 g typ)
(Normal)
21
40
20
1
TC55VCM208ASTN40,55
2002-07-04 2/12
BLOCK DIAGRAM
OPERATING MODE
MODE
1
CE CE2 OE R/W
I/O1~I/O8
POWER
Read
L H L H
Output
I
DDO
Write L
H
*
L Input
I
DDO
Output
Deselect
L H H H
High-Z
I
DDO
H
*
*
*
High-Z
I
DDS
Standby
*
L
*
*
High-Z
I
DDS
*
= don't care
H = logic high
L = logic low
MAXIMUM RATINGS
SYMBOL RATING
VALUE
UNIT
V
DD
Power Supply Voltage
-
0.3~4.2 V
V
IN
Input Voltage
-
0.3
*
~4.2 V
V
I/O
Input/Output Voltage
-
0.5~V
DD
+
0.5
V
P
D
Power Dissipation
0.6
W
T
solder
Soldering Temperature (10s)
260
C
T
stg
Storage Temperature
-
55~150 C
T
opr
Operating Temperature
-
40~85 C
*
:
-
2.0 V when measured at a pulse width of 20ns
COLUMN ADDRESS
BUFFER
A7
I/O1
MEMORY CELL ARRAY
2,048
256
8
(4,194,304)
COLUMN ADDRESS
DECODER
COLUMN ADDERSS
REGISTER
SENSE AMP
A8
A9
A11
A12
A14
A13
A15
A16
CE
V
DD
GND
CE
A6
A18
A2
A0 A1
A17
A3 A4 A5 A10
ROW ADDRESS
DECODER
ROW ADDRESS
BUFFER
ROW ADDRESS
REG
I
STER
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
DA
T
A
CON
T
R
O
L
CLOCK
GENERA
T
O
R
CE
1
CE
R/W
OE
CE2
TC55VCM208ASTN40,55
2002-07-04 3/12
DC RECOMMENDED OPERATING CONDITIONS (
Ta
=
-
40 to 85C
)
SYMBOL PARAMETER MIN
TYP
MAX
UNIT
V
DD
Power Supply Voltage
2.3
3.6 V
V
DD
=
2.3 V~2.7 V
2.0
V
IH
Input High Voltage
V
DD
=
2.7 V~3.6 V
2.2
V
DD
+
0.3
V
V
IL
Input Low Voltage
-
0.3
*
V
DD
0.24
V
V
DH
Data Retention Supply Voltage
1.5
3.6 V
*
:
-
2.0 V when measured at a pulse width of 20ns
DC CHARACTERISTICS
(Ta
=
-
40 to 85C, V
DD
=
2.3 to 3.6 V)
SYMBOL PARAMETER
TEST
CONDITION
MIN
TYP
MAX
UNIT
I
IL
Input Leakage
Current
V
IN
=
0 V~V
DD
1.0
A
I
OH
Output
High
Current
V
OH
=
V
DD
-
0.5 V
-
0.5
mA
I
OL
Output Low Current V
OL
=
0.4 V
2.1
mA
I
LO
Output Leakage
Current
1
CE
=
V
IH
or CE2
=
V
IL
or R/W
=
V
IL
or
OE
=
V
IH
,
V
OUT
=
0 V~V
DD
1.0
A
MIN
35
I
DDO1
1
CE
=
V
IL
and CE2
=
V
IH
and
R/W
=
V
IH
, I
OUT
=
0 mA,
Other Input
=
V
IH
/V
IL
1
s
8
mA
MIN
30
I
DDO2
Operating Current
1
CE
=
0.2 V and
CE2
=
V
DD
-
0.2 V and
R/W
=
V
DD
-
0.2 V,
I
OUT
=
0 mA,
Other Input
=
V
DD
-
0.2 V/0.2 V
t
cycle
1
s
3
mA
I
DDS1
1
CE
=
V
IH
or CE2
=
V
IL
1 mA
V
DD
=
3.3V
0.3 V
Ta
=
-
40~85C
10
Ta
=
25C
0.7
Ta
=
-
40~40C
2
I
DDS2
Standby Current
1
CE
=
V
DD
-
0.2 V or
CE2
=
0.2 V
V
DD
=
3.0 V
Ta
=
-
40~85C
5
A
CAPACITANCE
(Ta
=
25C, f
=
1 MHz)
SYMBOL PARAMETER
TEST
CONDITION
MAX
UNIT
C
IN
Input
Capacitance
V
IN
=
GND
10
pF
C
OUT
Output
Capacitance
V
OUT
=
GND
10
pF
Note: This parameter is periodically sampled and is not 100% tested.
TC55VCM208ASTN40,55
2002-07-04 4/12
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta
=
-
40 to 85C, V
DD
=
2.7 to 3.6 V)
READ CYCLE
TC55VCM208ASTN
40 55
SYMBOL PARAMETER
MIN MAX MIN MAX
UNIT
t
RC
Read
Cycle
Time
40
55
t
ACC
Address
Access
Time
40
55
t
CO1
Chip
Enable(
1
CE ) Access Time
40
55
t
CO2
Chip
Enable(CE2)
Access
Time
40
55
t
OE
Output
Enable
Access
Time
25
30
t
COE
Chip Enable Low to Output Active
5
5
t
OEE
Output Enable Low to Output Active
0
0
t
OD
Chip Enable High to Output High-Z
20
25
t
ODO
Output Enable High to Output High-Z
20
25
t
OH
Output
Data
Hold
Time
10
10
ns
WRITE CYCLE
TC55VCM208ASTN
40 55
SYMBOL PARAMETER
MIN MAX MIN MAX
UNIT
t
WC
Write
Cycle
Time
40
55
t
WP
Write Pulse Width
30
40
t
CW
Chip Enable to End of Write
35
45
t
AS
Address
Setup
Time
0
0
t
WR
Write
Recovery
Time
0
0
t
ODW
R/W Low to Output High-Z
20
25
t
OEW
R/W High to Output Active
0
0
t
DS
Data
Setup
Time
20
25
t
DH
Data
Hold
Time
0
0
ns
Note: t
OD
, t
ODO
and t
ODW
are specified in time when an output becomes high impedance, and are not judged depending on an
output voltage level.
TC55VCM208ASTN40,55
2002-07-04 5/12
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta
=
-
40 to 85C, V
DD
=
2.3 to 3.6 V)
READ CYCLE
TC55VCM208ASTN
40 55
SYMBOL PARAMETER
MIN MAX MIN MAX
UNIT
t
RC
Read
Cycle
Time
55
70
t
ACC
Address
Access
Time
55
70
t
CO1
Chip
Enable(
1
CE ) Access Time
55
70
t
CO2
Chip
Enable(CE2)
Access
Time
55
70
t
OE
Output
Enable
Access
Time
30
35
t
COE
Chip Enable Low to Output Active
5
5
t
OEE
Output Enable Low to Output Active
0
0
t
OD
Chip Enable High to Output High-Z
25
30
t
ODO
Output Enable High to Output High-Z
25
30
t
OH
Output
Data
Hold
Time
10
10
ns
WRITE CYCLE
TC55VCM208ASTN
40 55
SYMBOL PARAMETER
MIN MAX MIN MAX
UNIT
t
WC
Write
Cycle
Time
55
70
t
WP
Write Pulse Width
40
50
t
CW
Chip Enable to End of Write
45
55
t
AS
Address
Setup
Time
0
0
t
WR
Write
Recovery
Time
0
0
t
ODW
R/W Low to Output High-Z
25
30
t
OEW
R/W High to Output Active
0
0
t
DS
Data
Setup
Time
25
30
t
DH
Data
Hold
Time
0
0
ns
Note: t
OD
, t
ODO
and t
ODW
are specified in time when an output becomes high impedance, and are not judged depending on an
output voltage level.
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