TC581282AXB
2001-12-04 1/31
Power supply
V
CC
= 2.7 V to 3.6 V
Program/Erase Cycles 1E5 cycle (with ECC)
Access time
Cell array to register 25 s max
Serial Read Cycle
50 ns min
Operating current
Read (50 ns cycle)
10 mA typ.
Program (avg.)
10 mA typ.
Erase (avg.)
10 mA typ.
Standby 100
A
Package
P-TFBGA56-0710-0.80AZ (Weight: g typ.)
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
128-MBIT (16M
8 BITS) CMOS NAND E
2
PROM
DESCRIPTION
The TC581282A is a single 3.3 V 128-Mbit (138,412,032) bit NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E
2
PROM) organized as 528 bytes 32 pages 1024 blocks. The device has a 528-byte
static register which allows program and read data to be transferred between the register and the memory cell array
in 528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes
32 pages).
The TC581282A is a serial-type memory device which utilizes the I/O pins for both address and data input/output
as well as for command inputs. The Erase and Program operations are automatically executed making the device
most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras
and other systems which require high-density non-volatile memory data storage.
FEATURES
Organization
Memory cell allay 528 32K 8
Register 528
8
Page size
528 bytes
Block size
(16K + 512) bytes
Modes
Read, Reset, Auto Page Program
Auto Block Erase, Status Read
Mode control
Serial input/output
Command control
PIN ASSIGNMENT
(TOP VIEW)
PIN NAMES
1 2 3 4 5 6 7 8
A
NC
NC
B
NC
NC
C NU CLE NU NU NU NU
D
NU ALE NU NU NU NU
E WP
WE NU NU NU GND
F NU NU NU NU NU NU
G NU NU NU NU
BY
/
RY
NU
H
CE
I/O1 I/O3 NU NU NU
J RE NU NU V
CC
I/O8 I/O7
K V
SS
I/O2 I/O4 I/O6 I/O5 NC
L
NC
NC
M
NC
NC
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide
for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer's own risk.
The products described in this document are subject to the foreign exchange and foreign trade laws.
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
The information contained herein is subject to change without notice.
000707EBA1
I/O1 to I/O8
I/O port
CE
Chip
enable
WE Write
enable
RE Read
enable
CLE
Command latch enable
ALE
Address latch enable
WP Write
protect
BY
/
RY
Ready/Busy
GND
Ground input
V
CC
Power
supply
V
SS
Ground
NU : Not used, NC : Not Connected
TC581282AXB
2001-12-04 3/31
VALID BLOCKS
(1)
SYMBOL PARAMETER MIN
TYP.
MAX
UNIT
N
VB
Number of Valid Blocks
1004
1024 Blocks
(1) The TC581282A occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL PARAMETER MIN
TYP.
MAX
UNIT
V
CC
Power Supply Voltage
2.7
3.3
3.6
V
V
IH
High Level input Voltage
2.0
V
CC
+ 0.3
V
V
IL
Low Level Input Voltage
-0.3*
0.8 V
*
-2 V (pulse width lower than 20 ns)
DC CHARACTERISTICS
(Ta
=
=
=
=
-
-
-
-
40 to 85C, V
CC
=
=
=
= 2.7 V to 3.6 V)
SYMBOL PARAMETER
CONDITION
MIN
TYP.
MAX
UNIT
I
IL
Input Leakage Current
V
IN
= 0 V to V
CC
10
A
I
LO
Output Leakage Current
V
OUT
= 0.4 V to V
CC
10
A
I
CCO1
Operating Current (Serial Read)
CE
= V
IL
, I
OUT
= 0 mA, t
cycle
= 50 ns
10 30 mA
I
CCO3
Operating Current
(Command Input)
t
cycle
= 50 ns
10 30 mA
I
CCO4
Operating Current (Data Input)
t
cycle
= 50 ns
10 30 mA
I
CCO5
Operating Current
(Address Input)
t
cycle
= 50 ns
10 30 mA
I
CCO7
Programming
Current
10 30 mA
I
CCO8
Erasing
Current
10 30 mA
I
CCS1
Standby
Current
CE
= V
IH,
WP
= 0 V/V
CC
1 mA
I
CCS2
Standby
Current
CE
= V
CC
- 0.2 V
,
WP
= 0 V/V
CC
100 A
V
OH
High Level Output Voltage
I
OH
= -400 A 2.4
V
V
OL
Low Level Output Voltage
I
OL
= 2.1 mA
0.4 V
I
OL
(
BY
/
RY
) Output Current of
BY
/
RY
pin
V
OL
= 0.4 V
8 mA
TC581282AXB
2001-12-04 4/31
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta
=
=
=
=
-
-
-
-
40 to 85C, V
CC
=
=
=
= 2.7 V to 3.6 V)
SYMBOL PARAMETER
MIN
MAX
UNIT
NOTES
t
CLS
CLE Setup Time
0
ns
t
CLH
CLE Hold Time
10
ns
t
CS
CE Setup Time
0
ns
t
CH
CE Hold Time
10
ns
t
WP
Write
Pulse
Width
25
ns
t
ALS
ALE Setup Time
0
ns
t
ALH
ALE Hold Time
10
ns
t
DS
Data Setup Time
20
ns
t
DH
Data
Hold
Time
10
ns
t
WC
Write Cycle Time
50
ns
t
WH
WE High Hold Time
15
ns
t
WW
WP High to WE Low
100
ns
t
RR
Ready
to
RE Falling Edge
20
ns
t
RP
Read
Pulse
Width
35
ns
t
RC
Read Cycle Time
50
ns
t
REA
RE Access Time (Serial Data Access)
35 ns
t
CEA
CE Access Time (Serial Data Access)
45 ns
t
REAID
RE Access Time (ID Read)
35 ns
t
OH
Data Output Hold Time
10
ns
t
RHZ
RE High to Output High Impedance
30 ns
t
CHZ
CE High to Output High Impedance
20 ns
t
REH
RE High Hold Time
15
ns
t
IR
Output-High-impedance-to-
RE Falling Edge
0
ns
t
RSTO
RE Access Time (Status Read)
35 ns
t
CSTO
CE Access Time (Status Read)
45 ns
t
RHW
RE High to WE Low
0
ns
t
WHC
WE High to CE Low
30
ns
t
WHR
WE High to RE Low
30
ns
t
AR1
ALE Low to
RE Low (ID Read)
100
ns
t
CR
CE Low to
RE Low (ID Read)
100
ns
t
R
Memory Cell Array to Starting Address
25 s
t
WB
WE High to Busy
200 ns
t
AR2
ALE Low to
RE Low (Read Cycle)
50
ns
t
RST
Device Reset Time (Read/Program/Erase)
6/10/500 s
AC TEST CONDITIONS
PARAMETER CONDITION
Input level
2.4 V, 0.4 V
Input pulse rise and fall time
3 ns
Input comparison level
1.5 V, 1.5 V
Output data comparison level
1.5 V, 1.5 V
Output load
C
L
(100 pF)
+ 1 TTL
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