TC58NVG0S3AFT05

2003-08-20A 1/33

TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

1 GBIT (128M

8 BITS) CMOS NAND EEPROM

DESCRIPTION

The TC58NVG0S3A is a single 3.3-V 1G-bit (1,107,296,256 bits) NAND Electrically Erasable and Programmable

Read-Only Memory (NAND EEPROM) organized as (2048

+ 64) bytes × 64 pages × 1024 blocks. The device has a

2112-byte static registers which allow program and read data to be transferred between the register and the
memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes
+ 4 Kbytes: 2112 bytes × 64 pages).

The TC58NVG0S3A is a serial-type memory device which utilizes the I/O pins for both address and data

input/output as well as for command inputs. The Erase and Program operations are automatically executed
making the device most suitable for applications such as solid-state file storage, voice recording, image file
memory for still cameras and other systems which require high-density non-volatile memory data storage.

FEATURES

· Organization

Memory cell array 2112

× 64K × 8

× 8

Page size

2112 bytes

Block size

(128K

+ 4K) bytes

· Modes

Read, Reset, Auto Page Program
Auto Block Erase, Status Read

· Mode control

Serial input/output
Command control

PIN ASSIGNMENT

(TOP VIEW)

PIN

NAMES

I/O1 to I/O8

I/O port

Chip

enable

WE Write

enable

RE Read

enable

CLE

Command latch enable

ALE Address

latch

enable

WP Write

protect

Ready/Busy

GND Ground

Input

Power

supply

Ground

· Powersupply V

= 2.7 V to 3.6 V

· Program/Erase Cycles

1E5 Cycles (With ECC)

· Access time

Cell array to register

µs max

Serial Read Cycle

50 ns min

· Operating current

Read (50 ns cycle)

10 mA typ.

Program (avg.)

10 mA typ.

Erase (avg.)

10 mA typ.

Standby 50

µA max

· Package

TSOPI48-P-1220-0.50 (Weight: 0.53 g typ.)

1 48

2 47

3 46

4 45

5 44

6 43

7 42

8 41

9 40

10 39

11 38

12 37

13 36

14 35

15 34

16 33

17 32

18 31

19 30

20 29

21 28

22 27

23 26

24 25

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

GND

CLE

ALE

TC58NVG0S3AFT05

2003-08-20A 2/33

BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS

SYMBOL RATING

VALUE

UNIT

Power Supply Voltage

0.6 to 4.6

Input Voltage

0.6 to 4.6

I/O

Input /Output Voltage

0.6 V to V

0.3 V (

4.6 V)

Power Dissipation

0.3

SOLDER

Soldering Temperature (10 s)

260

°C

STG

Storage Temperature

55 to 150

°C

OPR

Operating Temperature

0 to 70

°C

CAPACITANCE

(Ta

=
=
=
=

25°C, f

=
=
=
=

1 MHz)

SYMB0L PARAMETER

CONDITION

MIN

MAX

UNIT

Input

0 V

10 pF

OUT

Output

OUT

0 V

10 pF

This parameter is periodically sampled and is not tested for every device.

I/O

Control

circuit

Status register

Address register

Command register

Column buffer

Column decoder

Data register

Sense amp

Memory

cell array

Control

circuit

HV generator

Row

addres

s
dec

order

Logic

control

I/O1

I/O8

CLE

ALE

Row

addres

s
buf

f
e
r

dec

oder

TC58NVG0S3AFT05

2003-08-20A 3/33

VALID BLOCKS

(1)

SYMBOL PARAMETER MIN

TYP.

MAX

UNIT

Number of Valid Blocks

1004

1024

Blocks

(1) The TC58NVG0S3A occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.
(2) The first block (block address #00) is guaranteed to be a valid block at the time of shipment.

RECOMMENDED DC OPERATING CONDITIONS

SYMBOL PARAMETER MIN

TYP.

MAX

UNIT

Power

Supply

Voltage

2.7 3.3 3.6 V

High

Level

input

Voltage

2.0

0.3

Low Level Input Voltage

0.3

0.8 V

2 V (pulse width lower than 20 ns)

DC CHARACTERISTICS

(Ta

=
=
=
=

0 to 70°C, V

=
=
=
=

2.7 V~3.3 V)

SYMBOL PARAMETER

CONDITION

MIN

TYP.

MAX

UNIT

Input

Leakage

Current

0 V to V

Output Leakage Current

OUT

0 V to V

CCO1

Reading

, I

OUT

0 mA, t

cycle

50 ns

10 30 mA

CCO2

Programming

Current

10 30 mA

CCO3

Erasing

Current

10 30 mA

CCS1

Standby

Current

IH,

0 V/V

1 mA

CCS2

Standby

Current

0.2 V, WP

0 V/V

High Level Output Voltage

, I

400

A 2.4

Low Level Output Voltage

, I

2.1 mA

0.4 V

(

) Output

current

pin V

0.4 V

TC58NVG0S3AFT05

2003-08-20A 4/33

AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS

(Ta

=
=
=
=

0 to 70°C, V

=
=
=
=

2.7 V~3.6 V)

SYMBOL PARAMETER

MIN

MAX

UNIT

NOTES

CLS

CLE

Setup

Time

CLH

CLE

Hold

Time

Setup Time

Hold Time

Write

Pulse

Width

ALS

ALE

Setup

Time

ALH

ALE

Hold

Time

Data

Setup

Time

Data

Hold

Time

Write

Cycle

Time

WE High Hold Time

WP High to WE Low

100

Ready

RE Falling Edge

Ready

WE Falling Edge

Read

Pulse

Width

Read

Cycle

Time

REA

RE Access Time (Serial Data Access)

35 ns

CEA

Access Time

45 ns

CLEA

CLE

Access

Time

45 ns

ALEA

ALE Access Time

45 ns

REAID

RE Access Time (ID Read)

35 ns

Data

Output

Hold

Time

RHZ

RE High to Output High Impedance

30 ns

CHZ

High to Output High Impedance

20 ns

REH

RE High Hold Time

Output-High-impedance-to- RE Falling Edge

RSTO

RE Access Time (Status Read)

35 ns

CSTO

Access Time (Status Read)

45 ns

CLSTO

CLE Access Time (Status Read)

45 ns

RHW

RE High to WE Low

WHC

WE High to

Low

WHR

WE High to RE Low

Low to RE Low (ID Read)

100

Memory Cell Array to Starting Address

WE High to Busy

200 ns

RST

Device

Reset

Time

(Read/Program/Erase)

6/10/500

TC58NVG0S3AFT05

2003-08-20A 5/33

AC TEST CONDITIONS

PARAMETER CONDITION

Input level

2.4 V, 0.4 V

Input pulse rise and fall time

3 ns

Input comparison level

1.5 V, 1.5 V

Output data comparison level

1.5 V, 1.5 V

Output load

(100 pF)

1 TTL

PROGRAMMING AND ERASING CHARACTERISTICS

(Ta

=
=
=
=

0 to 70°C, V

=
=
=
=

2.7 V~3.6 V)

SYMBOL PARAMETER MIN

TYP.

MAX

UNIT

NOTES

PROG

Average Programming Time

200 700

Number of Programming Cycles on Same Page
(per 512

16 bytes)

2 (1)

BERASE

Block

Erasing

Time

2 4 ms

(1) Refer to Application Note (12) toward the end of this document.

TC58NVG0S3AFT05

2003-08-20A 7/33

Address Input Cycle Timing Diagram

Data Input Cycle Timing Diagram

PA0 to 7

CA8 to 11

: V

or V

CLS

CLE

ALS

ALH

CA0 to 7

ALE

I/O1

to I/O8

PA8 to 15

: V

or V

ALS

CLH

ALE

CLE

I/O1

to I/O8

2111

TC58NVG0S3AFT05

2003-08-20A 9/33

Read Cycle Timing Diagram

Read Cycle Timing Diagram: When Interrupted by

CLEA

I/O1

to I/O8

CLS

CLH

00h

CA0 to 7

CA8 to 11

PA8 to 15

ALS

ALH

CLE

ALE

PA0 to 7

30h

ALH

CLS

CLH

ALS

OUT

REA

CEA

Col. Add. N

Data out from

Col. Add. N

CLEA

I/O1

to I/O8

CLS

CLH

00h

CA0 to 7

CA8 to 11

PA8 to 15

ALS

ALH

CLE

ALE

PA0 to 7

30h

ALH

CLS

CLH

ALS

OUT

REA

CEA

Col. Add. N

RHZ

CHZ

TC58NVG0S3AFT05

2003-08-20A 10/33

Column Address Change in Read Cycle Timing Diagram (1/2)

CLEA

I/O1

to I/O8

CLS

CLH

00h

CA0 to 7

CA8 to 11

PA8 to 15

ALS

ALH

CLE

ALE

Column address

PA0 to 7

30h

ALH

CLS

CLH

ALS

OUT

REA

OUT

CEA

Continues to 1 of next page

Page address

Column address

TC58NVG0S3AFT05

2003-08-20A 15/33

PIN FUNCTIONS

The device is a serial access memory which utilizes time-sharing input of address information. The device

pin-outs are configured as shown in Figure 1.

Command Latch Enable: CLE

The CLE input signal is used to control loading of the

operation mode command into the internal command register.
The command is latched into the command register from the
I/O port on the rising edge of the WE signal while CLE is
High.

Address Latch Enable: ALE

The ALE signal is used to control loading of either address

information or input data into the internal address/data
register.

Address information is latched on the rising edge of WE if

ALE is High.

Input data is latched if ALE is Low.

Chip Enable:

The device goes into a low-power Standby mode when CE goes High during the device is in Ready state.

The CE signal is ignored when device is in Busy state (

= L), such as during a Program or Erase or

Read operation, and will not enter Standby mode even if the CE input goes High.

Write Enable:

The WE signal is used to control the acquisition of data from the I/O port.

Read Enable:

The RE signal controls serial data output. Data is available t

REA

after the falling edge of RE .

The internal column address counter is also incremented (Address

= Address + 1) on this falling edge.

I/O Port: I/O1 to 8

The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from

the device.

Write Protect:

The WP signal is used to protect the device from accidental programming or erasing. The internal voltage

regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.

Ready/Busy:

The

output signal is used to indicate the operating condition of the device. The

signal is

in Busy state (

= L) during the Program, Erase and Read operations and will return to Ready state

(

= H) after completion of the operation. The output buffer for this signal is an open drain and has to

be pulled-up to Vccq with appropriate resister.

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

GND

CLE

ALE

Figure 1. Pinout

TC58NVG0S3AFT05

2003-08-20A 16/33

Schematic Cell Layout and Address Assignment

The Program operation works on page units while the Erase operation works on block units.

A page consists of 2112 bytes in which 2048 bytes are used
for main memory storage and 64 bytes are for redundancy
or for other uses.

1 page

= 2112 bytes

1 block

= 2112 bytes × 64 pages = (128K + 4K) bytes

Capacity

= 2112 bytes × 64 pages × 1024 blocks

An address is read in via the I/O port over four consecutive
clock cycles, as shown in Table 1.

Table 1. Addressing

I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1

First

cycle

CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0

Second

cycle

L L L L

CA11

CA10

CA9

CA8

Third

cycle

PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

CA0 to CA11 : Column address
PA0 to PA15 : Page address

PA6 to PA15 : Block address
PA0 to PA5 : NAND address in block

Fourth

cycle

PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8

Operation Mode: Logic and Command Tables

The operation modes such as Program, Erase, Read and Reset are controlled by the eleven different

command operations shown in Table 3. Address input, command input and data input/output are controlled by
the CLE, ALE, CE , WE , RE and WP signals, as shown in Table 2.

Table 2. Logic Table

CLE

ALE

Command Input

Data

Input

L L L H H

Address input

Serial

Data

Output

L L L H

During Programming (Busy)

* * * * *

During Erasing (Busy)

* * * * *

During Reading (Busy)

* * * * * *

Program, Erase Inhibit

* * * * *

Standby

* *

0 V/V

H: V

, L: V

: V

or V

1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit

64 Pages

1 block

8I/O

2112

65536
pages

1024 blocks

I/O1

I/O8

2048

Figure 2. Schematic Cell Layout

TC58NVG0S3AFT05

2003-08-20A 17/33

Table 3. Command table (HEX)

First Cycle

Second Cycle

Acceptable while Busy

Serial Data Input

Auto Program

Read Address Input

Column Address Change in Serial Data Output

Read Start

Read Column Change

Auto Block Erase

ID Read

Status Read

Reset FF

Table 4. shows the operation states for Read mode.

Table 4. Read mode operation states

CLE

ALE

I/O1 to I/O8

Power

Output select

Data output

Active

Output Deselect

High impedance

Active

Standby L

High impedance

Standby

Read Busy

* * * * *

High Impedance

Active

H: V

, L: V

: V

or V

I/O8

7 6 5 4 3 2 I/O1

Serial Data Input: 80h

(Example)

HEX data bit assignment

TC58NVG0S3AFT05

2003-08-20A 18/33

DEVICE OPERATION

Read Mode

Read mode is set when "00h" and "30h" commands are issued to the Command register. Between the

commands, start address for the Read mode need to be issued. Refer to Figure 3. below for sequence and the
block diagram (Refer to the detailed timing chart.).

Random Column Address Change in Read Cycle

A data transfer operation from the cell array to the register

starts on the rising edge of WE in the 30h command input
cycle (after the address information has been latched). The
device will be in Busy state during this transfer period.

After the transfer period the device returns to Ready state.

Serial data can be output synchronously with the RE clock
from the start address designated in the address input cycle.

Cell array

Select page

Figure 3. Read mode (1) operation

2111

CLE

00h

ALE

I/O

Busy

30h

Page Address N

Column Address M

M M

Page Address N

Start-address input

In the serial data out from the register, the column address

can be changed by inputting the column address with 05h and
E0h commands.

The data are read out in serial from the column address

which is input to the device by 05h and E0h commands with

RE clock.

Cell array

Select page

Figure 4. Random Column Address Change in Serial Read

Start-address input

CLE

00h

ALE

I/O

Busy

Page N

30h

05h E0h

Col. M

Page N

Col. M'

M M

1 M

2 M

M' M'

1 M'

2 M'

3 M'

Page N

Col. M

Start from Col. M

Start from Col. M'

TC58NVG0S3AFT05

2003-08-20A 19/33

Auto Page Program Operation

The device carries out an Automatic Page Program operation when it receives a "10h" Program command

after the address and data have been input. The sequence of command, address and data input is shown below.
(Refer to the detailed timing chart.)

Auto Block Erase

The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command "D0h"

which follows the Erase Setup command "60h". This two-cycle process for Erase operations acts as an extra
layer of protection from accidental erasure of data due to external noise. The device automatically executes the
Erase and Verify operations.

The data is transferred (programmed) from the register to the

selected page on the rising edge of WE following input of the "10h"
command. After programming, the programmed data is transferred
back to the register to be automatically verified by the device. If the
programming does not succeed, the Program/Verify operation is
repeated by the device until success is achieved or until the
maximum loop number set in the device is reached.

Figure 7. Auto Page Program operation

Data input

Selected

page

Reading & verification

Program

CLE

80h

ALE

I/O

Din

Page P

10h

Din

Col. M

Data

Status Out

Din

70h

Pass

I/O

Fail

Block Address
input: 2 cycles

Status Read

command

Busy

Erase Start

command

TC58NVG0S3AFT05

2003-08-20A 20/33

ID Read

The device contains ID code which identify the device type, the manufacturer, and some features of the

device. The ID codes can be read out under the following timing conditions:

Table 6. Code table

Descripton

I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1

Hex

Data

1st

Data

Maker

Code

1 0 0 1 1 0 0 0

98h

2nd

Data

Device

Code

1 1 1 1 0 0 0 1

F1h

3rd Data

Chip Number, Cell Type,

PGM Page

0 0 0 0 0 0 0 80h

00h

4th Data

Page Size, Block Size,

Redundant Size, Organization

0 0 1 0 1 0 1 95h

15h

5th Data

Plane Number, Plane Size

0 or 1

40h or C0h

3rd Data

Descripton

I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1

0 0

0 1

1 0

Internal Chip Number

1 1

2 level cell

4 level cell

8 level cell

Cell Type

level

cell

1 1

0 0

0 1

1 0

Number of simultaneously
programmed pages

1 1

Reserved

Reserved 2

0 or 1

For the specifications of the access times t

REAID

, t

and t

ALEA

refer to the AC Characteristics.

Figure 13. ID Read Timing

CLE

CEA

ALE

I/O

ALEA

REAID

ID Read

command

Address

Maker code

Device code

90h

00h

98h

F1h Note

1 Note

2 Note

Note 1: 80h or 00h
Note 2: 95h or 15h
Note 3: 40h or C0h

TC58NVG0S3AFT05

2003-08-20A 21/33

4th Data

Descripton

I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1

0 0

0 1

1 0

Page Size
(without redundant area)

1 1

0 0

128

0 1

256

1 0

Block Size
(without redundant area)

512

1 1

0 0

0 1

Reserved

1 0

Redundant area size
(byte/512 byte)

Reserved

1 1

Organization

Reserved

5th Data

Descripton

I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1

0 0

0 1

1 0

Plane Number

1 1

Mbit

0 0

128

Mbit

0 1

256

Mbit

1 0

512

Mbit

1 1

Gbit

0 0

Gbit

0 1

Gbit

1 0

Plane Size

Gbit

1 1

Reserved

0 or 1

TC58NVG0S3AFT05

2003-08-20A 22/33

Status Read

The device automatically implements the execution and verification of the Program and Erase operations.

The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass
/fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device status
is output via the I/O port on the RE clock after a "70h" command input.

The resulting information is outlined in Table 5.

Table 5. Status output table

STATUS

OUTPUT

I/O1

Chip Status 1

Pass: 0

Fail: 1

I/O2

Not Used

0 or 1

I/O3 Not

Used

I/O4 Not

Used

I/O5 Not

Used

I/O6 Ready/Busy

Ready:

Busy:

I/O7

Not Used

0 or 1

I/O8

Write Protect

Protect: 0

Not Protected: 1

The Pass/Fail status on I/O1 is only

valid when the device is in the Ready
state.

An application example with multiple devices is shown in Figure 6.

System Design Note: If the

pin signals from multiple devices are wired together as shown in the

diagram, the Status Read function can be used to determine the status of each individual device.

Status on Device 1

70h

ALE

I/O

70h

Status on Device N

CLE

Figure 6. Status Read timing application example

Busy

Device

CLE

Device

ALE

I/O1

to I/O8

Device

TC58NVG0S3AFT05

2003-08-20A 23/33

Reset

The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally

generated voltage is discharged to 0 volts and the device enters Wait state.

The response to an "FFh" Reset command input during the various device operations is as follows:

When a Reset (FFh) command is input during programming

When a Reset (FFh) command is input during erasing

When a Reset (FFh) command is input during Read operation

When a Status Read command (70h) is input after a Reset

When two or more Reset commands are input in succession

Internal V

RST

(max 10

Figure 8.

Internal erase

voltage

RST

(max 500

Figure 9.

RST

(max 6

Figure 10.

Figure 11.

I/O status : Pass/Fail

Pass

: Ready/Busy

Ready

I/O status : Ready/Busy

Busy

Figure 12.

(3)

(2)

(1)

The second command is invalid, but the third command is valid.

TC58NVG0S3AFT05

2003-08-20A 24/33

APPLICATION NOTES AND COMMENTS

(1) Power-on/off

sequence:

The timing sequence shown in Figure 15 is necessary for power-on/off sequence.
The device internal initialization start after the power supply reaches appropriate level in power on

sequence. During the initialization the device Ready/Busy signal outputs Busy state as shown in the Figure
15. In this time period, the acceptable commands are FFh or 70h.

The WP signal is useful for protecting against data corruption at power-on/off.

(2)

Status after power-on

The following sequence is necessary because some input signals may not be stable at power-on.

(3)

Prohibition of unspecified commands

The operation commands are listed in Table 3. Input of a command other than those specified in Table 3.

is prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.

(4)

Restriction of command while Busy state

During Busy state, do not input any command except 70h, and FFh.

Operation

0 V

2.7 V

2.5 V

Don't

care

Don't

care

Figure 15. Power-on/off Sequence

, WE , RE

CLE, ALE

Invalid

Don't

care

Ready/Busy

1 ms max

100

s max

Reset

Power on

Figure 16.

TC58NVG0S3AFT05

2003-08-20A 25/33

(5)

Acceptable commands after Serial Input command "80h"

Once the Serial Input command "80h" has been input, do not input any command other than the Column

Address Change in Auto Program command "10h" or the Reset command "FFh".

If a command other than "10h" or "FFh" is input, the Program operation is not performed and the device

operation is set to the mode which the input command specifies.

(6)

Addressing for program operation

Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of

the block to MSB (most significant bit) page of the block. Random page address programming is prohibited.

Address input

Command other than

"10h" or "FFh"

Programming cannot be executed.

Mode specified by the command.

DATA IN: Data (1)

Page 0

Data register

Page 2

Page 1

Page 31

Page 63

(1)
(2)
(3)

(32)

(64)

Data (64)

From the LSB page to MSB page

DATA IN: Data (1)

Page 0

Data register

Page 2

Page 1

Page 31

Page 63

(2)

(32)

(3)

(1)

(64)

Data (64)

Ex.) Random page program (Prohibition)

Figure 17. page programming within a block

TC58NVG0S3AFT05

2003-08-20A 26/33

(7)

Status Read during a Read operation

The device status can be read out by inputting the Status Read command "70h" in Read mode.
Once the device has been set to Status Read mode by a "70h" command, the device will not return to

Read mode.

Therefore, a Status Read during a Read operation is prohibited.
However, when the Read command "00h" is input during [A], Status mode is reset and the device returns

to Read mode. In this case, data output starts automatically from address N and address input is
unnecessary

(8)

Auto programming failure

(9)

: termination for the Ready/Busy pin (

)

A pull-up resistor needs to be used for termination because the

buffer consists of an open drain

circuit.

Address N

command

[A]

Status Read

command input

Status Read

Status output

Figure 18.

Fail

Address

Data
input

I/O

Address

Data
input

If the programming result for page address M is Fail, do not try to program the

page to address N in another block without the data input sequence.

Because the previous input data has been lost, the same input sequence of 80h

command, address and data is necessary.

Figure 19.

This data may vary from device to device.
We recommend that you use this data as a

reference when selecting a resistor value.

Device

1.5

1.0

0.5

1 K

3 K

2 K

15 ns

10 ns

5 ns

3.3 V

25°C

100 pF

Ready

3.0 V

1.0 V

3.0 V

1.0 V

Busy

TC58NVG0S3AFT05

2003-08-20A 29/33

(12)

Several programming cycles on the same page (Partial Page Program)

A page can be divided into up to 8 segments as follows:-

Data area (column address 0 to 2047): 512 bytes

× 4 segments

1st

segment: column address 0 to 511

2nd segment: column address 512 to 1023
3rd segment: column address 1024 to 1535
4th segment: column address 1536 to 2047

Redundant area (column address 2048 to 2111): 16 bytes

× 4 segments

1st segment: column address 2048 to 2063
2nd segment: column address 2064 to 2079
3rd segment: column address 2080 to 2095
4th segment: column address 2096 to 2111

Each segment can be programmed individually as follows:

Note: The input data for unprogrammed or previously programmed page segments must be "1"
(i.e. the inputs for all page bytes outside the segment which is to be programmed should be set to all "1").

Data Pattern 8

Data Pattern 1

All 1 s

Figure 24.

1st programming

Result

Data Pattern 1

Data Pattern 2

Data Pattern 8

Data Pattern 2

2nd programming

8th programming

TC58NVG0S3AFT05

2003-08-20A 30/33

(13)

Invalid blocks (bad blocks)

The device occasionally contains unusable blocks. Therefore, the following issues must be recognized:

At the time of shipment, all data bytes in a valid block are FFh. For

bad blocks, all bytes are not in the FFh state. Please don't perform erase
operation to bad blocks.

Check if the device has any bad blocks after installation into the

system. Figure 27. shows the test flow for bad block detection. Bad blocks
which are detected by the test flow must be managed as unusable blocks
by the system.

A bad block does not affect the performance of good blocks because it is

isolated from the bit line by the select gate

The number of valid blocks at the time of shipment is as follows:

MIN

TYP.

MAX

UNIT

Valid (Good) Block Number

1004

1024

Block

Bad Block Test Flow

Bad Block

Figure 26.

Read Check: Read the 1st page or the 2nd

page of each block. If the column
address 0 or 2048 of the 1st
page or the 2nd page is not FF
(Hex), define the block as a bad
block.

Figure 27.

1: No erase operation is allowed to detected bad blocks

Pass

Read Check

Start

Bad Block

Block No.

1024

End

Yes

Fail

Block No

Block No.

TC58NVG0S3AFT05

2003-08-20A 31/33

(14)

Failure phenomena for Program and Erase operations

The device may fail during a Program or Erase operation.

The following possible failure modes should be considered when implementing a highly reliable system.

FAILURE MODE

DETECTION AND COUNTERMEASURE SEQUENIE

Block

Erase Failure

Status Read after Erase

Block Replacement

Page

Programming Failure

Status Read after Program

Block Replacement

(1) Block Verify after Program

Retry

Single Bit

Programming Failure

"1 to 0"

(2) ECC

· ECC: Error Correction Code.

· Block Replacement

Program

Erase

When an error occurs in an Erase operation, prevent future accesses to this bad block
(again by creating a table within the system or by using another appropriate scheme).

(15)

Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery
is low. Power shortage and/or power failure before write/erase operation is complete will cause loss of data
and/or damage to data.

When an error happens in Block A, try to

reprogram the data into another Block (Block
B) by loading from an external buffer. Then,
prevent further system accesses to Block A (by
creating a bad block table or by using another
appropriate scheme).

Block A

Block B

Error occurs

Buffer

memory

Figure 28.

TC58NVG0S3AFT05

2003-08-20A 33/33

The information contained herein is subject to change without notice.

The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
TOSHIBA or others.

TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability
Handbook" etc..

The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer's own risk.

The products described in this document are subject to the foreign exchange and foreign trade laws.

TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced
and sold, under any law and regulations.

030619EBA

RESTRICTIONS ON PRODUCT USE

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TC58NVG0S3AFT05

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TC58NVG0S3AFT05