TC9470FN
2002-02-27
1
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9470FN
- Modulation DA Converter with Built-in 8-Times Oversampling Digital Filter/Dynamic
Digital Bass Boost/Analog Filter
The TC9470FN is a second-order - modulation system
1-bit DA converter incorporating an 8-times oversampling digital
filter, dynamic digital bass boost function for use with compressor
operations and an analog filter developed for digital audio
equipment.
Because the IC includes an analog filter, it can output a direct
analog waveform, thus reducing the size and cost of the DA
converter.
Features
Built-in 8-times oversampling digital filter
Low-voltage operations (2.4 V) possible
Built-in digital de-emphasis filter
Built-in dynamic digital bass boost function
In serial control mode, output amplitude can be set in 4096 steps of resolution using microcontroller commands
In parallel control mode, soft mute can be set for the output signal in 64 steps in 23 ms
Built-in LR common digital zero detection output circuit
Sampling frequency: 44.1 kHz
Supports 384 fs/256 fs (automatic switching)
DA converter oversampling ratio (OSR): 192 fs (at 384 fs)
Stereo/monaural output selection possible
Built-in third-order analog filter
The digital filter and DA converter characteristics are shown on the next page
Digital Filter
Digital
Filter
Passband
Ripple
Transient
Bandwidth
Attenuation
Standard operation
8 fs
0.11dB
20 k to 24.1 kHz
-26dB or less
DA Converter
(V
DD
= 2.7 V)
OSR
Noise
Distortion
S/N
Ratio
Standard operation
192 fs
-82dB (typ.)
90dB (typ.)
Weight: 0.14 g (typ.)
TC9470FN
2002-02-27
2
Pin Connection
Block Diagram
24
BCK
DATA
DBB2
ATT (DBB1)
SHIFT (EMP)
23
22
21
20
19
18
V
DD
1
2
3
4
5
6
7
T1
S
P/
V
DA
RO
GNDA
VR
LATCH (SM)
17
8
GNDA
V
DX
16
9
LO
XO
15
10
V
DA
XI
14
11
ZD
GNDX
13
12
GNDD
MCK
LRCK
LRCK
24
23
22
21
20
19
18
17
16
15
14
13
Data interface
circuit
Microcontroller
interface circuit
Oscillator circuit
Dynamic bus
boost circuit
Timing generator
Digital filter circuit,
de-emphasis filter circuit,
attenuator circuit
- modulator circuit
Output
circuit
Test
circuit
Analog
filter
1
2
3
4
5
6
7
8
9
10
11
12
Output
circuit
Analog
filter
+
BCK DATA DBB2
(DBB1)
ATT
V
DX
XO
XI GNDX MCK
(EMP)
SHIFT
(SM)
LATCH
LO
V
DA
ZD GNDD
S
P/
V
DA
VR GNDA
RO GNDA
V
DD
T1
TC9470FN
2002-02-27
3
Pin Function
Pin No.
Symbol
I/O
Function
Remarks
1 V
DD
Digital block power supply pin
2
T1
I
Test pin. Always set to "Low" level.
3
S
P/
I
Parallel/serial mode select pin
4 V
DA
Analog power supply pin
5
RO
O
Right channel analog signal output pin
6 GNDA
Analog GND pin
7 VR
Reference voltage pin
8 GNDA
Analog GND pin
9
LO
O
Left channel analog signal output pin
10 V
DA
Analog power supply pin
11
ZD
O
Zero data detection output pin common to left and right channels
12 GNDD Digital
GND
pin
13
MCK
O
System clock output pin
14 GNDX
Crystal oscillator GND pin
15 XI
I
16 XO
O
Crystal oscillator connecting pins.
Generate the clock required by the system.
17 V
DX
Crystal oscillator power supply pin
18
LATCH
(SM)
I
In serial mode, data latch signal input pin
In parallel mode, soft mute control pin
Schmidt input
19
SHIFT
(EMP)
I
In serial mode, shift clock input pin
In parallel mode, de-emphasis filter control pin
Schmidt input
20
ATT
(DBB1)
I
In serial mode, data input pin
In parallel mode, dynamic bass boost control pin 1
Schmidt input
21
DBB2
I
In parallel mode, dynamic bass boost control pin 2
22
DATA
I
Audio data input pin
Schmidt input
23
BCK
I
Bit clock input pin
Schmidt input
24
LRCK
I
LR clock input pin
Schmidt input
XI XO
TC9470FN
2002-02-27
4
Description of Block Operations
1. Crystal Oscillator Circuit and Timing Generator
The clock required for internal operations is generated by connecting a crystal and condensers as shown
in the diagram below.
The IC will also operate when a system clock is input from an external source through the XI pin (pin 15).
However, in this situation, due consideration must be given to the fact that waveform characteristics, such
as jitter and rising/falling characteristics of the system clock, significantly affect the DA converter's noise
distortion and the S/N ratio.
The timing generator generates the clocks and process timing signals required for such functions as
digital filtering and de-emphasis filtering.
Figure 1 Crystal Oscillator Circuit Configuration (when in the 384 fs mode)
C
L
= 10 to 33 pF
To internal circuit
GNDX
16.9344 MHz
C
L
XI
XO V
DX
C
L
X'tal
MCK
Use a crystal with a low CI value and favorable start-up characteristics.
TC9470FN
200
2-
02-
2
7
5
2.
Dat
a
I
nput Circuit
D
A
T
A
and t
h
e LR
C
K
ar
e
loa
d
ed t
o
t
h
e LS
I i
n
t
e
r
n
al
shift
r
e
g
i
st
er
s
on t
h
e B
C
K
s
i
g
n
al r
i
sing
edg
e
.
It
is c
o
nse
q
ue
nt
ly
nec
e
ss
ar
y
fo
r
t
h
e D
A
T
A
a
n
d
LR
C
K
sig
n
als t
o
be
sy
nc
hr
oniz
ed
and
inp
u
t
on t
h
e B
C
K
sig
n
al
f
a
l
ling
ed
g
e
as
i
n
d
i
c
a
t
e
d
in
t
h
e t
i
ming
ex
amp
l
e b
e
l
o
w
.
A
l
s
o
, a
s
D
A
T
A
has
b
een d
e
sig
n
ed
s
o
tha
t
th
e
1
6
b
i
ts
b
e
f
o
re
th
e
c
h
ang
e
po
int
of LR
C
K
ar
e r
e
g
a
r
d
ed as v
a
l
i
d dat
a
,
t
h
e dat
a
must
b
e
input
w
i
t
h
R
i
g
h
t
-
j
u
st
ifi
e
d mod
e
w
h
e
n
t
h
e B
C
K
is 48
fs or
64 f
s
,
as show
n in Fig
u
r
e
2a.
Figure 2a
Examp
l
e
of Input T
i
ming Chart
L-c
h
R-c
h
LRCK
BC
K
M
SB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
LS
B
MS
B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
L
SB
DA
T
A
Figure 2b
Ex
ample
of Input T
i
ming Chart
I
n
val
i
d
dat
a
I
n
val
i
d
dat
a
L-c
h
R-c
h
LRCK
BC
K
M S B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
L S B
M S B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
L S B
DA
T
A
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