TC94A29FAG/FB

2003-04-01

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC94A29FAG, TC94A29FB

Single-Chip CD Processor with Built-in Controller (CD-CX)

The TC94A29FAG/FB is a single-chip CD processor for digital

servo, which incorporates a 4-bit microcontroller.

The controller features an LCD driver, 4-channel 6-bit AD

converter, 1 port 2-channel 2/3-line or UART serial interface
module, a buzzer, 20-bit general-purpose counter function,
interrupt function, and 8-bit timer/counter. The CPU can select
one of four operating clocks (16.9344-MHz, 75-kHz or 32.768-kHz
crystal oscillator and CR oscillator), facilitating interface with the
CD processor.

The CD processor incorporates sync separation protection and

interpolation, EFM demodulator, error correction, digital
equalizer for servo, and servo controller. The CD processor also
incorporates a 1-bit DA converter. In combination with the
TA2157F/FN digital servo head amplifier, the TC94A29FAG/FB
can very simply configure an adjustment-free CD player.

Thus, the IC is suitable for CD systems for automobiles and

radio-cassette players.

Features

· Single-chip CD processor with on-chip CMOS LCD driver and

4-bit microcontroller

· Operating supply voltage:

CD in operation: V

= 3.0 to 3.6 V (3.3 V typ.)

CD stopped: V

= 1.8 to 3.6 V (only CPU in operation)

· Supply current:

CD in operation: I

= 30 mA (typ.)

CD stopped: I

= 1.5 mA (CD standby mode, with 16.9344-MHz crystal oscillator, CPU in operation)

CD stopped: I

= 50 µA (CD standby mode, with 75-kHz crystal oscillator, CPU in operation)

· Operating temperature range: Ta = -40 to 85°C
· Package: LQFP/QFP-64 (0.5/0.65-mm pitch, 1.4 mm thick)
· E

PROM: TC94AE29FAG/FB

TC94A29FAG

TC94A29FB

Weight
LQFP64-P-1010-0.50: 0.32 g (typ.)
QFP64-P-1212-0.65: 0.45 g (typ.)

TC94A29FAG/FB

2003-04-01

4-bit Microcontroller

· Program memory (ROM): 16 bits ´ 8 Ksteps
· Data memory (RAM): 4 bits ´ 512 words
· Instruction execution time: 1.42 ms, 40 ms, 91.6 ms, TOSC ´ 3 (Every instruction consists of a single word.)
· Crystal oscillator frequency: 16.9344 MHz, 75 kHz, 32.768 kHz, CR oscillation frequency
· Stack levels: 6
· AD converter: 6 bits ´ 4 channels
· LCD driver: 1/4 duty, 1/2 or 1/3 bias method, 64 segments (max.)
· I/O ports: CMOS I/O ports: 26 (max.)

N-channel open-drain I/O ports (for up to 5.5 V): 3 (max.)

· Timer/counter: 8 bits (timer mode, pulse width detector and measure function)
· General-purpose counter: 20 bits, 0.1 MHz to 20 MHz, Vin = 0.2 Vpp (min.), input amplifier incorporated
· Serial interface module: 1 port 2 channel supporting 2/3-line method or UART

(two input channels)

· Four buzzer types: 0.75 kHz, 1 kHz, 1.5 kHz, and 3 kHz
· Four modes: continuous, single-shot, 10 Hz intermittent, and 10 Hz intermittent at 1 Hz intervals
· Interrupts: 1 external, 3 internal (CD sub-sync, serial interface, 8-bit timer)
· Back-up mode: Four types: CD standby (CD processor stopped)

Clock stop (oscillator stopped)

Hardware wait (only crystal oscillator in operation)

Software wait (CPU in intermittent operation)

· Reset function: Power-on reset circuit, supply voltage detector (detection voltage = 1.5 V typ.)

CD Processor

· Reliable sync pattern detection, sync signal protection and interpolation
· Built-in EFM demodulator and subcode decoder
· High-correction capability using Cross Interleave Read Solomon Code (CIRC) logical equation

C1 correction: dual
C2

correction:

quadruple

· Jitter absorption capability of ± 6 frames
· Built-in 16 KB RAM
· Built-in digital output circuit
· Built-in L/R independent digital attenuator
· Bilingual audio output
· Audio output: 32fs, 48fs or 64fs selectable
· Subcode Q data is read-timing free and can be driven out in sync with audio data.
· Built-in data slicer and analog PLL (adjustment-free VCO used) circuit
· Automatic adjustment of loop gain, offset, and balance at focus servo and tracking servo
· Built-in RF gain auto-adjusting circuit
· Built-in digital equalizer for phase compensation
· Supports different pickups using on-chip digital equalizer coefficient RAM.
· Built-in focus and tracking servo control circuit
· Search control supports all modes and realizes high-speed, stable search.
· Lens kick and feed kick use speed control method.
· Built-in AFC and APC circuits for disc motor CLV servo
· Built-in defect/shock detector
· Built-in 8 times over-sampling digital filter and 1-bit DA converter
· Built-in analog filter for 1-bit DA converter
· Built-in zero-data detection output circuit
· Supports double-speed operation.

Note:

Output pins for subcode Q data and audio data have multiplexed functions for controller-dedicated pins. The
function of each pin can be switched by program.

TC94A29FAG/FB

2003-04-01

Pin Connections

TEZI

LQFP/QFP-64

(0.5/0.65-mm pitch)

Top view

FMO

SEL

TEBC

FOO

39 38 37 36

10 11 12 13

RESET

P8-0/MXI/OSC (BRK1)

P8-1/MXO (BRK2)

P2-0/COM1

P2-1/COM2

P2-2/COM3

P2-3/COM4

TEST/P3-0/S1

P3-1/S2

P3-2/S3

P3-3/S4

P4-0/S5

P4-1/S6

P4-2/S7

P4-3/S8

P5-0/S9

-
1
/S1

0
/BC

(

3
)

-
2
/S1

1
/L

K (

4
)

-
3
/S1

2
/AO

(

5
)

6
-0/

/
A

n1/

DOU

6
-1/

/
A

n2/

I
P

F (B

6
-2/

/
A

n3/

6
-3/

/
A

n4/

CLC

1
-0/

1
/
CTi

n
/
D

10)

-
1
/SD

I
O

1
/T

/
S

(

1
1
)

1
-
2
/
S

I
1
/S

Y (

1
2
)

1
-3/

13)

7
-0/

2
(B

14)

-
1
/SD

I
O

2
/T

(

1
5
)

7
-2/

I
NTR

/
S

I
2 (B

16)

TEI

SBAD

FEI

RFRP

RFZI

REF

RFI

SLCO

VCOF

LPFO

LPFN

TMAX

PDO

1-bit DAC

16.9344-MHz

oscillator

CD proc

ess

o
r-dedi

c
a
t
e
d
c

o
n
t
rol

i
n
put

/
out

put

n
s

75-kHz /

32.768-kHz/CR

LCD dri

v
er (4

64 s

egm

t
s
m

a
x.

)

AD converter

Controller-dedicated pins

Serial interface 1

Pull-up/pull-down can be specified.

Reset input

Tes

t
m

ode

i
nput

CMOS I/O ports (up to 26 ports)

u
l
l
-
up/

pul

l
-
down c

be s

p
e
c
i
f
i
ed.

Also used for CD function

N-ch open-drain I/O

(3 pins, 5.5 V max.)

Serial interface 2

I
n
t
e
rrupt

i
npu

u
zz

er out

Frequenc

y c

ount

i
npu

Note:

For BRK1 to BRK16, the backup state can be set to be released in
port units.

Note:

The TEST pin (pin 56) is pulled down during a reset, thus accepting
test mode input. Therefore, it should be applied low or left open
during a reset.

TC94A29FAG/FB

2003-04-01

Block Diagram

P7-0/SCK2/RX2 (BRK14)

DVR

TMAX

PDO

VCOF

FZI

FEI

TEI

TEZ

FOO

FMO

SEL

TEBC

REF

P7-2/INTR/SI2 (BRK16)

P7-1/SDIO2/TX2 (BRK15)

LPFN

RFI

SLCO

P8-0/MX1/OSC (BRK1)

LPFO

MPX

Clock gene.

CPU clock

OSC

LCD Driver/IO Port 2, 3, 4, 5, 6

Port 1

Bias

1-bi

t
DA

ZDET

PWM

CD clock

REF

SBSY

Servo

control

Digital equalizer

Automatic adjustment

circuit

ROM

RAM

16-k SRAM

CLV

servo

REF

Synchronous

guarantee EFM

decoder

Sub code decoder

Data

slicer

REF

PLL

TMAX

VCO

Correction circuit

ddres

Digital out

Audio out

Microcontroller interface

Data Reg (16 bits)

Mask ROM

(16

8192 Steps)

Program

Counter

Stack Reg.
(16 Levels)

G-Reg.

R/W Buf.

ALU

Power on Reset

F/F

Reset

BCK, LRCK, AOUT, DOUT, IPF, SBOK,

CLCK, DATA, SFSY, SBSY

RAM

512 words)

Instruction

Decoder

SBSY

BCK, LRCK, AOUT, DOUT

IPF, SBOK, CLCK, DATA, SFSY

CD Reset

Reset

REF

Crystal

OSC

Port 8

Timer

Interrupt

cont.

Serial

interface

(SIO)

Port 7

Buzzer

20-bit

counter

conv.

-
0
/C

SIO

RESET

-
1
/C

-
2
/C

-
3
/C

/
P

3-0/

-
1
/S2

-
0
/S9

-
1
/S1

0
/BC

(

3
)

5
-2/

/
L
RCK

5
-3/

/
A

OUT

6
-0/

/
A

n1/

DOU

6
-1/

/
A

n2/

I
P

F (B

6
-2/

/
A

n3/

6
-3/

/
A

n4/

CLC

1
-0/

1
/
CTi

n
/
D

10)

-
1
/SD

I
O

1
/T

/
S

(

1
1
)

-
2
/S

/
S

(

1
2
)

1
-3/

UZR

13)

P8-1/MXO (BRK2)

INTR

Crystal

OSC

TC94A29FAG/FB

2003-04-01

Pin Functions

No.

Symbol

Pin Name

Function and Operation

Remarks

RESET

Reset

input

System reset input pin for the device.

A reset is applied while the

RESET

signal is low.

When it is high, the 16.9344-MHz crystal
oscillator (XI, XO) starts operating. The
controller counts clock pulses from this oscillator
and waits a specified standby time
(approximately 50 ms) before starting the
controller program from address 0. The CD
processor is placed in the standby state at this
time.

Normally, raising the voltage on MVDD from 0
to 1.8 V or higher triggers a system reset
(power-on reset) so that the

RESET

pin should

be held at high.

P8-0
/MXI

/OSC

(BRK1)

P8-1

/MXO

(BRK2)

I/O port 8-0

/crystal oscillator

/CR oscillator

I/O port 8-1

/crystal oscillator

2-bit CMOS I/O port.

Input/output can be specified for each bit. When
the pins are used as I/O port input, each pin can
be pulled up or down by program. When backup
release for clock stop mode or wait mode is
enabled for the pins, a change in a pin can
release the backup state.

The program can set these pins to be used for a
75-kHz or 32.768-kHz dedicated crystal
oscillator. The P8-0 pin can also be used for a
CR oscillator. These clocks are used for the
operation of the controller and peripheral
devices. Upon a system reset, the 16.9344-MHz
crystal oscillator (XI, XO) is selected as the
clock for controller and peripheral device
operation. The program can subsequently set
the pins to oscillator pins and switch the clock
generated from the oscillator to the controller
clock. When the pins are used for an oscillator,
executing the CKSTP instruction causes its
oscillation to stop.

(Note) When the P8-0 pin is used for a CR

oscillator, the P8-1 pin can used as an
I/O port pin.

(Note) Backup release is enabled for both pins

simultaneously.

(Note) Use a crystal oscillator having a good

startup characteristic.

(Note) Upon a system reset, the pins are set to

I/O port input.

(Note) After setting the pins to oscillator pins,

wait until oscillation settles before
switching the controller clock.

MXO

out2

fXT2

MXI

(When used for crystal oscillator)

OSC

(When P8-0 is used

for CR oscillator)

IN1

Input

instructio

(When used for I/O port)

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TC94A29FB

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TC94A29FB